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mfd: rtsx: Update PETXCFG address
PETXCFG is defined at 0xFF03, the old 0xFE49 not used any more. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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@ -118,11 +118,9 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
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rts5227_fill_driving(pcr, OUTPUT_3V3);
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/* Configure force_clock_req */
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if (pcr->flags & PCR_REVERSE_SOCKET)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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AUTOLOAD_CFG_BASE + 3, 0xB8, 0xB8);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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AUTOLOAD_CFG_BASE + 3, 0xB8, 0x88);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
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return rtsx_pci_send_cmd(pcr, 100);
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@ -116,11 +116,9 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
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/* Configure driving */
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rts5249_fill_driving(pcr, OUTPUT_3V3);
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if (pcr->flags & PCR_REVERSE_SOCKET)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
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return rtsx_pci_send_cmd(pcr, 100);
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@ -572,7 +572,6 @@
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#define MSGTXDATA2 0xFE46
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#define MSGTXDATA3 0xFE47
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#define MSGTXCTL 0xFE48
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#define PETXCFG 0xFE49
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#define LTR_CTL 0xFE4A
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#define OBFF_CFG 0xFE4C
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@ -606,6 +605,7 @@
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#define DUMMY_REG_RESET_0 0xFE90
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#define AUTOLOAD_CFG_BASE 0xFF00
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#define PETXCFG 0xFF03
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#define PM_CTRL1 0xFF44
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#define PM_CTRL2 0xFF45
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