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m68k: use the coherent DMA code for coldfire without data cache
Coldfire cores configured without a data cache are DMA coherent and
should thus simply use the simple coherent version of dma-direct.
Introduce a new COLDFIRE_COHERENT_DMA Kconfig symbol as a convenient
short hand for such configurations, and a M68K_NONCOHERENT_DMA symbol
for all cases where we need to build non-coherent DMA infrastructure
to simplify the Kconfig and code conditionals.
Not building the non-coherent DMA code slightly reduces the code
size for such configurations.
Numers for m5249evb_defconfig below:
text data bss dec hex filename
2896158 401052 65392 3362602 334f2a vmlinux.before
2895166
400988 65392 3361546 334b0a vmlinux.after
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Greg Ungerer <gerg@linux-m68k.org>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Tested-by: Greg Ungerer <gerg@linux-m68k.org>
This commit is contained in:
parent
63f067e33c
commit
9e28bf8bdf
@ -6,16 +6,16 @@ config M68K
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select ARCH_HAS_BINFMT_FLAT
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select ARCH_HAS_CPU_FINALIZE_INIT if MMU
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select ARCH_HAS_CURRENT_STACK_POINTER
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select ARCH_HAS_DMA_ALLOC if !MMU || COLDFIRE
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select ARCH_HAS_DMA_PREP_COHERENT if HAS_DMA && MMU && !COLDFIRE
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE if HAS_DMA
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select ARCH_HAS_DMA_ALLOC if M68K_NONCOHERENT_DMA && COLDFIRE
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select ARCH_HAS_DMA_PREP_COHERENT if M68K_NONCOHERENT_DMA && !COLDFIRE
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE if M68K_NONCOHERENT_DMA
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select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS
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select ARCH_MIGHT_HAVE_PC_PARPORT if ISA
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select ARCH_NO_PREEMPT if !COLDFIRE
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select ARCH_USE_MEMTEST if MMU_MOTOROLA
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select ARCH_WANT_IPC_PARSE_VERSION
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select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
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select DMA_DIRECT_REMAP if HAS_DMA && MMU && !COLDFIRE
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select DMA_DIRECT_REMAP if M68K_NONCOHERENT_DMA && !COLDFIRE
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select GENERIC_ATOMIC64
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select GENERIC_CPU_DEVICES
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select GENERIC_IOMAP
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@ -535,3 +535,15 @@ config CACHE_COPYBACK
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The ColdFire CPU cache is set into Copy-back mode.
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endchoice
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endif # HAVE_CACHE_CB
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# Coldfire cores that do not have a data cache configured can do coherent DMA.
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config COLDFIRE_COHERENT_DMA
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bool
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default y
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depends on COLDFIRE
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depends on !HAVE_CACHE_CB && !CACHE_D && !CACHE_BOTH
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config M68K_NONCOHERENT_DMA
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bool
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default y
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depends on HAS_DMA && !COLDFIRE_COHERENT_DMA
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@ -23,7 +23,7 @@ obj-$(CONFIG_MMU_MOTOROLA) += ints.o vectors.o
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obj-$(CONFIG_MMU_SUN3) += ints.o vectors.o
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obj-$(CONFIG_PCI) += pcibios.o
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obj-$(CONFIG_HAS_DMA) += dma.o
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obj-$(CONFIG_M68K_NONCOHERENT_DMA) += dma.o
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obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
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obj-$(CONFIG_BOOTINFO_PROC) += bootinfo_proc.o
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@ -17,7 +17,7 @@
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#include <asm/cacheflush.h>
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#if defined(CONFIG_MMU) && !defined(CONFIG_COLDFIRE)
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#ifndef CONFIG_COLDFIRE
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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cache_push(page_to_phys(page), size);
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