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ARM: dts: Add initial support for Arndale Octa board

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Arndale Octa board is based on Exynos5420 SoC. This patch
adds the basic support required for booting it through DT.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Sachin Kamat 2013-12-12 07:32:39 +09:00 committed by Kukjin Kim
parent a22d060e32
commit 9dd51c9f77
2 changed files with 67 additions and 0 deletions
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1
arch/arm/boot/dts/Makefile
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@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb

66
arch/arm/boot/dts/exynos5420-arndale-octa.dts Normal file
View File

@ -0,0 +1,66 @@
/*
* Samsung's Exynos5420 based Arndale Octa board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos5420.dtsi"
/ {
model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
compatible = "insignal,arndale-octa", "samsung,exynos5420";
memory {
reg = <0x20000000 0x80000000>;
};
chosen {
bootargs = "console=ttySAC3,115200";
};
fixed-rate-clocks {
oscclk {
compatible = "samsung,exynos5420-oscclk";
clock-frequency = <24000000>;
};
};
mmc@12200000 {
status = "okay";
broken-cd;
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
};
mmc@12220000 {
status = "okay";
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
};