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- Make sure 32-bit syscall registers are properly sign-extended
- Add detection for AMD's Zen5 generation CPUs and Intel's Clearwater Forest CPU model number - Make a stub function export non-GPL because it is part of the paravirt alternatives and that can be used by non-GPL code -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmW2JvkACgkQEsHwGGHe VUozlQ//VJDOBaZ/rEoKPK/mhoTHvcBBb8WyhoVfV0/MNOW7CFoFw3RocDxg6BYI h4w4vCCuhca0ZO0u5k9AKgWUVbheaUv3e4J0hTqIgEsN6qDY/3pYSxUy8cv+Gxwq dkNTZyfsmpgVDKM5NrFUOK6njDu2nmWjJmGWlu9pGJ4gyyK5+gkPUwxKXj2QVqTg oemAWHbwkXgXGt5SW9nr0ihNMMGIMGTp0rR8ax4Mr9Ge1d4LXnPQSuo3DnxRVdx5 sdW/XFf9wRIa95ig9lUGD9Uh7Mkcx3L5aggP62jrMPZkzWFKWKpW5Br4HlSo1SWv YOLrjkLj45GqzQFOn2S+RY5GZC4woLjZZTjmt6Rvk+C+LL2C0w+jsEmuS/sPDeKN MJb09FZs5FnqcX+hpcBvmIkRYIF6KbEwVGmYh1+23ffW8Cih4A2XCWmfrADpOdbW h16irylL7tTwt4jL7dAxEzL9ViUtfi1l1pgD+BzbMOqac3/tSBdrKXWgEAnssXx5 QLYFrG3i+6M6ls2qigsLKp5w4r9IHU5Lx3oZDfd2xX89bCYpp1ua/H3JO3eBeUCw YqkUEYUg+5XIqN+90QuHMHPzc6Hyd4p6meliiQzHqKO55/QRj8s037tuydzjRcvy 8h0Y3UuUg/+Sb/qLwGeY3rRy/zknIvFc8lL5MBWVCW0iaYV0XAk= =7vE4 -----END PGP SIGNATURE----- Merge tag 'x86_urgent_for_v6.8_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Borislav Petkov: - Make sure 32-bit syscall registers are properly sign-extended - Add detection for AMD's Zen5 generation CPUs and Intel's Clearwater Forest CPU model number - Make a stub function export non-GPL because it is part of the paravirt alternatives and that can be used by non-GPL code * tag 'x86_urgent_for_v6.8_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/CPU/AMD: Add more models to X86_FEATURE_ZEN5 x86/entry/ia32: Ensure s32 is sign extended to s64 x86/cpu: Add model number for Intel Clearwater Forest processor x86/CPU/AMD: Add X86_FEATURE_ZEN5 x86/paravirt: Make BUG_func() usable by non-GPL modules
This commit is contained in:
Linus Torvalds
commit
9d451912db
@ -81,10 +81,8 @@
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#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
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#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
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#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
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/* CPU types for specific tunings: */
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#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
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/* FREE, was #define X86_FEATURE_K7 ( 3*32+ 5) "" Athlon */
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#define X86_FEATURE_ZEN5 ( 3*32+ 5) /* "" CPU based on Zen5 microarchitecture */
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#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
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#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
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#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
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@ -162,6 +162,8 @@
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#define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */
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#define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */
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#define INTEL_FAM6_ATOM_DARKMONT_X 0xDD /* Clearwater Forest */
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/* Xeon Phi */
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#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
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@ -58,12 +58,29 @@ extern long __ia32_sys_ni_syscall(const struct pt_regs *regs);
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,,regs->di,,regs->si,,regs->dx \
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,,regs->r10,,regs->r8,,regs->r9) \
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/* SYSCALL_PT_ARGS is Adapted from s390x */
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#define SYSCALL_PT_ARG6(m, t1, t2, t3, t4, t5, t6) \
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SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5), m(t6, (regs->bp))
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#define SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5) \
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SYSCALL_PT_ARG4(m, t1, t2, t3, t4), m(t5, (regs->di))
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#define SYSCALL_PT_ARG4(m, t1, t2, t3, t4) \
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SYSCALL_PT_ARG3(m, t1, t2, t3), m(t4, (regs->si))
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#define SYSCALL_PT_ARG3(m, t1, t2, t3) \
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SYSCALL_PT_ARG2(m, t1, t2), m(t3, (regs->dx))
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#define SYSCALL_PT_ARG2(m, t1, t2) \
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SYSCALL_PT_ARG1(m, t1), m(t2, (regs->cx))
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#define SYSCALL_PT_ARG1(m, t1) m(t1, (regs->bx))
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#define SYSCALL_PT_ARGS(x, ...) SYSCALL_PT_ARG##x(__VA_ARGS__)
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#define __SC_COMPAT_CAST(t, a) \
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(__typeof(__builtin_choose_expr(__TYPE_IS_L(t), 0, 0U))) \
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(unsigned int)a
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/* Mapping of registers to parameters for syscalls on i386 */
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#define SC_IA32_REGS_TO_ARGS(x, ...) \
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__MAP(x,__SC_ARGS \
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,,(unsigned int)regs->bx,,(unsigned int)regs->cx \
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,,(unsigned int)regs->dx,,(unsigned int)regs->si \
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,,(unsigned int)regs->di,,(unsigned int)regs->bp)
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SYSCALL_PT_ARGS(x, __SC_COMPAT_CAST, \
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__MAP(x, __SC_TYPE, __VA_ARGS__)) \
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#define __SYS_STUB0(abi, name) \
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long __##abi##_##name(const struct pt_regs *regs); \
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@ -403,7 +403,7 @@ noinstr void BUG_func(void)
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{
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BUG();
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}
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EXPORT_SYMBOL_GPL(BUG_func);
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EXPORT_SYMBOL(BUG_func);
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#define CALL_RIP_REL_OPCODE 0xff
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#define CALL_RIP_REL_MODRM 0x15
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@ -538,7 +538,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
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/* Figure out Zen generations: */
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switch (c->x86) {
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case 0x17: {
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case 0x17:
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switch (c->x86_model) {
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case 0x00 ... 0x2f:
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case 0x50 ... 0x5f:
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@ -554,8 +554,8 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
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goto warn;
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}
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break;
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}
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case 0x19: {
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case 0x19:
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switch (c->x86_model) {
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case 0x00 ... 0x0f:
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case 0x20 ... 0x5f:
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@ -569,7 +569,20 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
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goto warn;
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}
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break;
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}
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case 0x1a:
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switch (c->x86_model) {
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case 0x00 ... 0x0f:
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case 0x20 ... 0x2f:
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case 0x40 ... 0x4f:
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case 0x70 ... 0x7f:
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setup_force_cpu_cap(X86_FEATURE_ZEN5);
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break;
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default:
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goto warn;
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}
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break;
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default:
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break;
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}
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@ -1039,6 +1052,11 @@ static void init_amd_zen4(struct cpuinfo_x86 *c)
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msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
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}
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static void init_amd_zen5(struct cpuinfo_x86 *c)
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{
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init_amd_zen_common();
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}
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static void init_amd(struct cpuinfo_x86 *c)
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{
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u64 vm_cr;
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@ -1084,6 +1102,8 @@ static void init_amd(struct cpuinfo_x86 *c)
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init_amd_zen3(c);
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else if (boot_cpu_has(X86_FEATURE_ZEN4))
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init_amd_zen4(c);
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else if (boot_cpu_has(X86_FEATURE_ZEN5))
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init_amd_zen5(c);
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/*
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* Enable workaround for FXSAVE leak on CPUs
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@ -128,6 +128,7 @@ struct mnt_id_req;
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#define __TYPE_IS_LL(t) (__TYPE_AS(t, 0LL) || __TYPE_AS(t, 0ULL))
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#define __SC_LONG(t, a) __typeof(__builtin_choose_expr(__TYPE_IS_LL(t), 0LL, 0L)) a
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#define __SC_CAST(t, a) (__force t) a
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#define __SC_TYPE(t, a) t
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#define __SC_ARGS(t, a) a
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#define __SC_TEST(t, a) (void)BUILD_BUG_ON_ZERO(!__TYPE_IS_LL(t) && sizeof(t) > sizeof(long))
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