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ARM: EXYNOS: local definitions for pm.c into mach-exynos dir
Some of definitions in the regs-clock.h are used only for pm.c, so this moves them into the file. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -18,25 +18,6 @@
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#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
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#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
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#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
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#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)
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#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)
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#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)
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#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)
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#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)
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#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)
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#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)
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#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)
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#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)
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#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)
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#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
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#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
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#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
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#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
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#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
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@ -45,16 +26,9 @@
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#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)
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#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)
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#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
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#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
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#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
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#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
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/* Only for EXYNOS4210 */
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#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
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/* For EXYNOS5250 */
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#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
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@ -29,12 +29,36 @@
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#include <plat/pll.h>
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#include <plat/regs-srom.h>
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#include <mach/regs-clock.h>
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#include <mach/map.h>
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#include <mach/pm-core.h>
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#include "common.h"
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#include "regs-pmu.h"
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#define EXYNOS4_EPLL_LOCK (S5P_VA_CMU + 0x0C010)
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#define EXYNOS4_VPLL_LOCK (S5P_VA_CMU + 0x0C020)
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#define EXYNOS4_EPLL_CON0 (S5P_VA_CMU + 0x0C110)
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#define EXYNOS4_EPLL_CON1 (S5P_VA_CMU + 0x0C114)
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#define EXYNOS4_VPLL_CON0 (S5P_VA_CMU + 0x0C120)
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#define EXYNOS4_VPLL_CON1 (S5P_VA_CMU + 0x0C124)
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#define EXYNOS4_CLKSRC_MASK_TOP (S5P_VA_CMU + 0x0C310)
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#define EXYNOS4_CLKSRC_MASK_CAM (S5P_VA_CMU + 0x0C320)
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#define EXYNOS4_CLKSRC_MASK_TV (S5P_VA_CMU + 0x0C324)
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#define EXYNOS4_CLKSRC_MASK_LCD0 (S5P_VA_CMU + 0x0C334)
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#define EXYNOS4_CLKSRC_MASK_MAUDIO (S5P_VA_CMU + 0x0C33C)
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#define EXYNOS4_CLKSRC_MASK_FSYS (S5P_VA_CMU + 0x0C340)
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#define EXYNOS4_CLKSRC_MASK_PERIL0 (S5P_VA_CMU + 0x0C350)
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#define EXYNOS4_CLKSRC_MASK_PERIL1 (S5P_VA_CMU + 0x0C354)
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#define EXYNOS4_CLKSRC_MASK_DMC (S5P_VA_CMU + 0x10300)
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#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
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#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
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#define EXYNOS4210_CLKSRC_MASK_LCD1 (S5P_VA_CMU + 0x0C338)
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static const struct sleep_save exynos4_set_clksrc[] = {
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{ .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
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{ .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
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