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drm/i915: Set PIPECONF color range bit on Valleyview

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VLV has the color range selection bit in the PIPECONF register.
Configure it appropriately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: fixup rebase issues due to slightly different baseline.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2013-04-02 16:10:09 +03:00 committed by Daniel Vetter
parent 84b046f398
commit 9c8e09b7a5
1 changed files with 7 additions and 0 deletions
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7
drivers/gpu/drm/i915/intel_display.c
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@ -4583,6 +4583,13 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
else
pipeconf |= PIPECONF_PROGRESSIVE;
if (IS_VALLEYVIEW(dev)) {
if (intel_crtc->config.limited_color_range)
pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
else
pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
}
I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
POSTING_READ(PIPECONF(intel_crtc->pipe));
}