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x86, perf: Fix few cosmetic dabs for P4 pmu (comments and constantify)

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- A few ESCR have escaped fixing at previous attempt.
- p4_escr_map is read only, make it const.

Nothing serious.

Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Lin Ming <ming.m.lin@intel.com>
LKML-Reference: <20100318211256.GH5062@lenovo>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Cyrill Gorcunov 2010-03-19 00:12:56 +03:00 committed by Ingo Molnar
parent 4b24a88b35
commit 9c8c6bad31
2 changed files with 3 additions and 3 deletions
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4
arch/x86/include/asm/perf_event_p4.h
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@ -401,13 +401,13 @@ static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
#define P4_RETIRED_MISPRED_BRANCH_TYPE P4_EVENT_PACK(0x05, 0x02) #define P4_RETIRED_MISPRED_BRANCH_TYPE P4_EVENT_PACK(0x05, 0x02)
/* /*
* MSR_P4_TBPU_ESCR0: 4, 5 * MSR_P4_TBPU_ESCR0: 4, 5
* MSR_P4_TBPU_ESCR0: 6, 7 * MSR_P4_TBPU_ESCR1: 6, 7
*/ */
#define P4_RETIRED_BRANCH_TYPE P4_EVENT_PACK(0x04, 0x02) #define P4_RETIRED_BRANCH_TYPE P4_EVENT_PACK(0x04, 0x02)
/* /*
* MSR_P4_TBPU_ESCR0: 4, 5 * MSR_P4_TBPU_ESCR0: 4, 5
* MSR_P4_TBPU_ESCR0: 6, 7 * MSR_P4_TBPU_ESCR1: 6, 7
*/ */
#define P4_RESOURCE_STALL P4_EVENT_PACK(0x01, 0x01) #define P4_RESOURCE_STALL P4_EVENT_PACK(0x01, 0x01)

2
arch/x86/kernel/cpu/perf_event_p4.c
View File

@ -545,7 +545,7 @@ static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
} }
/* ESCRs are not sequential in memory so we need a map */ /* ESCRs are not sequential in memory so we need a map */
static unsigned int p4_escr_map[ARCH_P4_TOTAL_ESCR] = { static const unsigned int p4_escr_map[ARCH_P4_TOTAL_ESCR] = {
MSR_P4_ALF_ESCR0, /* 0 */ MSR_P4_ALF_ESCR0, /* 0 */
MSR_P4_ALF_ESCR1, /* 1 */ MSR_P4_ALF_ESCR1, /* 1 */
MSR_P4_BPU_ESCR0, /* 2 */ MSR_P4_BPU_ESCR0, /* 2 */