From 9c5c92e35cf5c4f7ee523d62a6bf9d5dc290350b Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 25 Jun 2014 12:12:41 +0100 Subject: [PATCH] iommu/arm-smmu: prefer stage-1 mappings where we have a choice For an SMMU that supports both Stage-1 and Stage-2 mappings (but not nested translation), then we should prefer stage-1 mappings as we otherwise rely on the memory attributes of the incoming transactions for IOMMU_CACHE mappings. Signed-off-by: Will Deacon --- drivers/iommu/arm-smmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 2961b8c474eb..7638b579e08d 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -876,12 +876,12 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, */ cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; start = smmu->num_s2_context_banks; - } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) { - cfg->cbar = CBAR_TYPE_S2_TRANS; - start = 0; - } else { + } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) { cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; start = smmu->num_s2_context_banks; + } else { + cfg->cbar = CBAR_TYPE_S2_TRANS; + start = 0; } ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,