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mt76x0: phy: use proper name convention
Use mt76x0_phy as prefix for routines in mt76x0/phy.c Moreover use mt76x0_rf_set to enable vco calibration in mt76x0_phy_vco_cal Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Lorenzo Bianconi
Felix Fietkau
parent
989582e50c
commit
9c41078247
@ -113,7 +113,7 @@ static int mt76x0_init_bbp(struct mt76x02_dev *dev)
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{
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int ret, i;
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ret = mt76x0_wait_bbp_ready(dev);
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ret = mt76x0_phy_wait_bbp_ready(dev);
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if (ret)
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return ret;
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@ -65,7 +65,7 @@ int mt76x0_set_rts_threshold(struct ieee80211_hw *hw, u32 value);
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/* PHY */
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void mt76x0_phy_init(struct mt76x02_dev *dev);
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int mt76x0_wait_bbp_ready(struct mt76x02_dev *dev);
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int mt76x0_phy_wait_bbp_ready(struct mt76x02_dev *dev);
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int mt76x0_phy_set_channel(struct mt76x02_dev *dev,
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struct cfg80211_chan_def *chandef);
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void mt76x0_phy_recalibrate_after_assoc(struct mt76x02_dev *dev);
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@ -110,7 +110,7 @@ out:
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}
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static int
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rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val)
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mt76x0_rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val)
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{
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if (mt76_is_usb(dev)) {
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struct mt76_reg_pair pair = {
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@ -126,8 +126,7 @@ rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val)
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}
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}
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static int
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rf_rr(struct mt76x02_dev *dev, u32 offset)
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static int mt76x0_rf_rr(struct mt76x02_dev *dev, u32 offset)
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{
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int ret;
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u32 val;
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@ -149,38 +148,38 @@ rf_rr(struct mt76x02_dev *dev, u32 offset)
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}
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static int
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rf_rmw(struct mt76x02_dev *dev, u32 offset, u8 mask, u8 val)
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mt76x0_rf_rmw(struct mt76x02_dev *dev, u32 offset, u8 mask, u8 val)
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{
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int ret;
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ret = rf_rr(dev, offset);
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ret = mt76x0_rf_rr(dev, offset);
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if (ret < 0)
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return ret;
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val |= ret & ~mask;
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ret = rf_wr(dev, offset, val);
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if (ret)
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return ret;
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return val;
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val |= ret & ~mask;
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ret = mt76x0_rf_wr(dev, offset, val);
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return ret ? ret : val;
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}
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static int
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rf_set(struct mt76x02_dev *dev, u32 offset, u8 val)
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mt76x0_rf_set(struct mt76x02_dev *dev, u32 offset, u8 val)
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{
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return rf_rmw(dev, offset, 0, val);
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return mt76x0_rf_rmw(dev, offset, 0, val);
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}
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#if 0
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static int
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rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask)
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{
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return rf_rmw(dev, offset, mask, 0);
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return mt76x0_rf_rmw(dev, offset, mask, 0);
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}
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#endif
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static void
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mt76x0_rf_csr_wr_rp(struct mt76x02_dev *dev, const struct mt76_reg_pair *data,
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int n)
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mt76x0_phy_rf_csr_wr_rp(struct mt76x02_dev *dev,
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const struct mt76_reg_pair *data,
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int n)
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{
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while (n-- > 0) {
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mt76x0_rf_csr_wr(dev, data->reg, data->value);
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@ -190,12 +189,12 @@ mt76x0_rf_csr_wr_rp(struct mt76x02_dev *dev, const struct mt76_reg_pair *data,
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#define RF_RANDOM_WRITE(dev, tab) do { \
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if (mt76_is_mmio(dev)) \
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mt76x0_rf_csr_wr_rp(dev, tab, ARRAY_SIZE(tab)); \
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mt76x0_phy_rf_csr_wr_rp(dev, tab, ARRAY_SIZE(tab)); \
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else \
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mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, tab, ARRAY_SIZE(tab));\
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} while (0)
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int mt76x0_wait_bbp_ready(struct mt76x02_dev *dev)
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int mt76x0_phy_wait_bbp_ready(struct mt76x02_dev *dev)
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{
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int i = 20;
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u32 val;
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@ -215,11 +214,11 @@ int mt76x0_wait_bbp_ready(struct mt76x02_dev *dev)
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return 0;
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}
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static void mt76x0_vco_cal(struct mt76x02_dev *dev, u8 channel)
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static void mt76x0_phy_vco_cal(struct mt76x02_dev *dev, u8 channel)
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{
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u8 val;
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val = rf_rr(dev, MT_RF(0, 4));
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val = mt76x0_rf_rr(dev, MT_RF(0, 4));
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if ((val & 0x70) != 0x30)
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return;
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@ -235,20 +234,20 @@ static void mt76x0_vco_cal(struct mt76x02_dev *dev, u8 channel)
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* 40MHz channel: 101
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* 20MHz channel: 100
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*/
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val = rf_rr(dev, MT_RF(0, 6));
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val = mt76x0_rf_rr(dev, MT_RF(0, 6));
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val &= ~0xf;
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val |= 0x09;
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rf_wr(dev, MT_RF(0, 6), val);
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mt76x0_rf_wr(dev, MT_RF(0, 6), val);
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val = rf_rr(dev, MT_RF(0, 5));
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val = mt76x0_rf_rr(dev, MT_RF(0, 5));
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if (val != 0)
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rf_wr(dev, MT_RF(0, 5), 0x0);
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mt76x0_rf_wr(dev, MT_RF(0, 5), 0x0);
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val = rf_rr(dev, MT_RF(0, 4));
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val = mt76x0_rf_rr(dev, MT_RF(0, 4));
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val &= ~0x07;
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rf_wr(dev, MT_RF(0, 4), val);
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mt76x0_rf_wr(dev, MT_RF(0, 4), val);
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val = rf_rr(dev, MT_RF(0, 3));
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val = mt76x0_rf_rr(dev, MT_RF(0, 3));
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val &= ~0x77;
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if (channel == 1 || channel == 7 || channel == 9 || channel >= 13) {
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val |= 0x63;
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@ -261,12 +260,9 @@ static void mt76x0_vco_cal(struct mt76x02_dev *dev, u8 channel)
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WARN(1, "Unknown channel %u\n", channel);
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return;
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}
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rf_wr(dev, MT_RF(0, 3), val);
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mt76x0_rf_wr(dev, MT_RF(0, 3), val);
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/* TODO replace by mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7)); */
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val = rf_rr(dev, MT_RF(0, 4));
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val = ((val & ~(0x80)) | 0x80);
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rf_wr(dev, MT_RF(0, 4), val);
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mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7));
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msleep(2);
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}
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@ -278,8 +274,8 @@ mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band)
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case NL80211_BAND_2GHZ:
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RF_RANDOM_WRITE(dev, mt76x0_rf_2g_channel_0_tab);
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rf_wr(dev, MT_RF(5, 0), 0x45);
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rf_wr(dev, MT_RF(6, 0), 0x44);
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mt76x0_rf_wr(dev, MT_RF(5, 0), 0x45);
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mt76x0_rf_wr(dev, MT_RF(6, 0), 0x44);
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mt76_wr(dev, MT_TX_ALC_VGA3, 0x00050007);
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mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x003E0002);
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@ -287,8 +283,8 @@ mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band)
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case NL80211_BAND_5GHZ:
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RF_RANDOM_WRITE(dev, mt76x0_rf_5g_channel_0_tab);
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rf_wr(dev, MT_RF(5, 0), 0x44);
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rf_wr(dev, MT_RF(6, 0), 0x45);
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mt76x0_rf_wr(dev, MT_RF(5, 0), 0x44);
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mt76x0_rf_wr(dev, MT_RF(6, 0), 0x45);
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mt76_wr(dev, MT_TX_ALC_VGA3, 0x00000005);
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mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x01010102);
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@ -326,103 +322,103 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
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else
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freq_item = &(mt76x0_frequency_plan[i]);
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rf_wr(dev, MT_RF(0, 37), freq_item->pllR37);
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rf_wr(dev, MT_RF(0, 36), freq_item->pllR36);
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rf_wr(dev, MT_RF(0, 35), freq_item->pllR35);
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rf_wr(dev, MT_RF(0, 34), freq_item->pllR34);
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rf_wr(dev, MT_RF(0, 33), freq_item->pllR33);
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mt76x0_rf_wr(dev, MT_RF(0, 37), freq_item->pllR37);
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mt76x0_rf_wr(dev, MT_RF(0, 36), freq_item->pllR36);
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mt76x0_rf_wr(dev, MT_RF(0, 35), freq_item->pllR35);
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mt76x0_rf_wr(dev, MT_RF(0, 34), freq_item->pllR34);
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mt76x0_rf_wr(dev, MT_RF(0, 33), freq_item->pllR33);
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rf_val = rf_rr(dev, MT_RF(0, 32));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 32));
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rf_val &= ~0xE0;
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rf_val |= freq_item->pllR32_b7b5;
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rf_wr(dev, MT_RF(0, 32), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 32), rf_val);
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/* R32<4:0> pll_den: (Denomina - 8) */
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rf_val = rf_rr(dev, MT_RF(0, 32));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 32));
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rf_val &= ~0x1F;
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rf_val |= freq_item->pllR32_b4b0;
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rf_wr(dev, MT_RF(0, 32), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 32), rf_val);
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/* R31<7:5> */
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rf_val = rf_rr(dev, MT_RF(0, 31));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 31));
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rf_val &= ~0xE0;
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rf_val |= freq_item->pllR31_b7b5;
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rf_wr(dev, MT_RF(0, 31), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 31), rf_val);
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/* R31<4:0> pll_k(Nominator) */
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rf_val = rf_rr(dev, MT_RF(0, 31));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 31));
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rf_val &= ~0x1F;
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rf_val |= freq_item->pllR31_b4b0;
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rf_wr(dev, MT_RF(0, 31), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 31), rf_val);
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/* R30<7> sdm_reset_n */
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rf_val = rf_rr(dev, MT_RF(0, 30));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30));
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rf_val &= ~0x80;
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if (bSDM) {
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rf_wr(dev, MT_RF(0, 30), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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rf_val |= 0x80;
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rf_wr(dev, MT_RF(0, 30), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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} else {
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rf_val |= freq_item->pllR30_b7;
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rf_wr(dev, MT_RF(0, 30), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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}
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/* R30<6:2> sdmmash_prbs,sin */
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rf_val = rf_rr(dev, MT_RF(0, 30));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30));
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rf_val &= ~0x7C;
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rf_val |= freq_item->pllR30_b6b2;
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rf_wr(dev, MT_RF(0, 30), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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/* R30<1> sdm_bp */
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rf_val = rf_rr(dev, MT_RF(0, 30));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30));
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rf_val &= ~0x02;
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rf_val |= (freq_item->pllR30_b1 << 1);
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rf_wr(dev, MT_RF(0, 30), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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/* R30<0> R29<7:0> (hex) pll_n */
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rf_val = freq_item->pll_n & 0x00FF;
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rf_wr(dev, MT_RF(0, 29), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 29), rf_val);
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rf_val = rf_rr(dev, MT_RF(0, 30));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 30));
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rf_val &= ~0x1;
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rf_val |= ((freq_item->pll_n >> 8) & 0x0001);
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rf_wr(dev, MT_RF(0, 30), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 30), rf_val);
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/* R28<7:6> isi_iso */
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rf_val = rf_rr(dev, MT_RF(0, 28));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28));
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rf_val &= ~0xC0;
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rf_val |= freq_item->pllR28_b7b6;
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rf_wr(dev, MT_RF(0, 28), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
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/* R28<5:4> pfd_dly */
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rf_val = rf_rr(dev, MT_RF(0, 28));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28));
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rf_val &= ~0x30;
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rf_val |= freq_item->pllR28_b5b4;
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rf_wr(dev, MT_RF(0, 28), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
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/* R28<3:2> clksel option */
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rf_val = rf_rr(dev, MT_RF(0, 28));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28));
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rf_val &= ~0x0C;
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rf_val |= freq_item->pllR28_b3b2;
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rf_wr(dev, MT_RF(0, 28), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
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/* R28<1:0> R27<7:0> R26<7:0> (hex) sdm_k */
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rf_val = freq_item->pll_sdm_k & 0x000000FF;
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rf_wr(dev, MT_RF(0, 26), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 26), rf_val);
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rf_val = ((freq_item->pll_sdm_k >> 8) & 0x000000FF);
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rf_wr(dev, MT_RF(0, 27), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 27), rf_val);
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rf_val = rf_rr(dev, MT_RF(0, 28));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 28));
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rf_val &= ~0x3;
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rf_val |= ((freq_item->pll_sdm_k >> 16) & 0x0003);
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rf_wr(dev, MT_RF(0, 28), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 28), rf_val);
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/* R24<1:0> xo_div */
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rf_val = rf_rr(dev, MT_RF(0, 24));
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rf_val = mt76x0_rf_rr(dev, MT_RF(0, 24));
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rf_val &= ~0x3;
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rf_val |= freq_item->pllR24_b1b0;
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rf_wr(dev, MT_RF(0, 24), rf_val);
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mt76x0_rf_wr(dev, MT_RF(0, 24), rf_val);
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break;
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}
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@ -430,19 +426,22 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
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for (i = 0; i < ARRAY_SIZE(mt76x0_rf_bw_switch_tab); i++) {
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if (rf_bw == mt76x0_rf_bw_switch_tab[i].bw_band) {
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rf_wr(dev, mt76x0_rf_bw_switch_tab[i].rf_bank_reg,
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mt76x0_rf_bw_switch_tab[i].value);
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mt76x0_rf_wr(dev,
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mt76x0_rf_bw_switch_tab[i].rf_bank_reg,
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mt76x0_rf_bw_switch_tab[i].value);
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} else if ((rf_bw == (mt76x0_rf_bw_switch_tab[i].bw_band & 0xFF)) &&
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(rf_band & mt76x0_rf_bw_switch_tab[i].bw_band)) {
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rf_wr(dev, mt76x0_rf_bw_switch_tab[i].rf_bank_reg,
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mt76x0_rf_bw_switch_tab[i].value);
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mt76x0_rf_wr(dev,
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mt76x0_rf_bw_switch_tab[i].rf_bank_reg,
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mt76x0_rf_bw_switch_tab[i].value);
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}
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}
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for (i = 0; i < ARRAY_SIZE(mt76x0_rf_band_switch_tab); i++) {
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if (mt76x0_rf_band_switch_tab[i].bw_band & rf_band) {
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rf_wr(dev, mt76x0_rf_band_switch_tab[i].rf_bank_reg,
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mt76x0_rf_band_switch_tab[i].value);
|
||||
mt76x0_rf_wr(dev,
|
||||
mt76x0_rf_band_switch_tab[i].rf_bank_reg,
|
||||
mt76x0_rf_band_switch_tab[i].value);
|
||||
}
|
||||
}
|
||||
|
||||
@ -470,8 +469,9 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
|
||||
/* External PA */
|
||||
for (i = 0; i < ARRAY_SIZE(mt76x0_rf_ext_pa_tab); i++)
|
||||
if (mt76x0_rf_ext_pa_tab[i].bw_band & rf_band)
|
||||
rf_wr(dev, mt76x0_rf_ext_pa_tab[i].rf_bank_reg,
|
||||
mt76x0_rf_ext_pa_tab[i].value);
|
||||
mt76x0_rf_wr(dev,
|
||||
mt76x0_rf_ext_pa_tab[i].rf_bank_reg,
|
||||
mt76x0_rf_ext_pa_tab[i].value);
|
||||
}
|
||||
|
||||
if (rf_band & RF_G_BAND) {
|
||||
@ -516,7 +516,7 @@ mt76x0_phy_set_chan_bbp_params(struct mt76x02_dev *dev, u16 rf_bw_band)
|
||||
}
|
||||
}
|
||||
|
||||
static void mt76x0_ant_select(struct mt76x02_dev *dev)
|
||||
static void mt76x0_phy_ant_select(struct mt76x02_dev *dev)
|
||||
{
|
||||
struct ieee80211_channel *chan = dev->mt76.chandef.chan;
|
||||
|
||||
@ -536,7 +536,7 @@ static void mt76x0_ant_select(struct mt76x02_dev *dev)
|
||||
}
|
||||
|
||||
static void
|
||||
mt76x0_bbp_set_bw(struct mt76x02_dev *dev, enum nl80211_chan_width width)
|
||||
mt76x0_phy_bbp_set_bw(struct mt76x02_dev *dev, enum nl80211_chan_width width)
|
||||
{
|
||||
enum { BW_20 = 0, BW_40 = 1, BW_80 = 2, BW_10 = 4};
|
||||
int bw;
|
||||
@ -684,7 +684,7 @@ int mt76x0_phy_set_channel(struct mt76x02_dev *dev,
|
||||
}
|
||||
|
||||
if (mt76_is_usb(dev)) {
|
||||
mt76x0_bbp_set_bw(dev, chandef->width);
|
||||
mt76x0_phy_bbp_set_bw(dev, chandef->width);
|
||||
} else {
|
||||
if (chandef->width == NL80211_CHAN_WIDTH_80 ||
|
||||
chandef->width == NL80211_CHAN_WIDTH_40)
|
||||
@ -696,7 +696,7 @@ int mt76x0_phy_set_channel(struct mt76x02_dev *dev,
|
||||
mt76x02_phy_set_bw(dev, chandef->width, ch_group_index);
|
||||
mt76x02_phy_set_band(dev, chandef->chan->band,
|
||||
ch_group_index & 1);
|
||||
mt76x0_ant_select(dev);
|
||||
mt76x0_phy_ant_select(dev);
|
||||
|
||||
mt76_rmw(dev, MT_EXT_CCA_CFG,
|
||||
(MT_EXT_CCA_CFG_CCA0 |
|
||||
@ -722,10 +722,10 @@ int mt76x0_phy_set_channel(struct mt76x02_dev *dev,
|
||||
mt76x02_init_agc_gain(dev);
|
||||
|
||||
if (mt76_is_usb(dev)) {
|
||||
mt76x0_vco_cal(dev, channel);
|
||||
mt76x0_phy_vco_cal(dev, channel);
|
||||
} else {
|
||||
/* enable vco */
|
||||
rf_set(dev, MT_RF(0, 4), BIT(7));
|
||||
mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7));
|
||||
}
|
||||
|
||||
if (scan)
|
||||
@ -749,7 +749,7 @@ void mt76x0_phy_recalibrate_after_assoc(struct mt76x02_dev *dev)
|
||||
|
||||
mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0, false);
|
||||
|
||||
mt76x0_vco_cal(dev, channel);
|
||||
mt76x0_phy_vco_cal(dev, channel);
|
||||
|
||||
tx_alc = mt76_rr(dev, MT_TX_ALC_CFG_0);
|
||||
mt76_wr(dev, MT_TX_ALC_CFG_0, 0);
|
||||
@ -774,18 +774,18 @@ void mt76x0_phy_recalibrate_after_assoc(struct mt76x02_dev *dev)
|
||||
mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 1, false);
|
||||
}
|
||||
|
||||
static void mt76x0_temp_sensor(struct mt76x02_dev *dev)
|
||||
static void mt76x0_phy_temp_sensor(struct mt76x02_dev *dev)
|
||||
{
|
||||
u8 rf_b7_73, rf_b0_66, rf_b0_67;
|
||||
s8 val;
|
||||
|
||||
rf_b7_73 = rf_rr(dev, MT_RF(7, 73));
|
||||
rf_b0_66 = rf_rr(dev, MT_RF(0, 66));
|
||||
rf_b0_67 = rf_rr(dev, MT_RF(0, 67));
|
||||
rf_b7_73 = mt76x0_rf_rr(dev, MT_RF(7, 73));
|
||||
rf_b0_66 = mt76x0_rf_rr(dev, MT_RF(0, 66));
|
||||
rf_b0_67 = mt76x0_rf_rr(dev, MT_RF(0, 67));
|
||||
|
||||
rf_wr(dev, MT_RF(7, 73), 0x02);
|
||||
rf_wr(dev, MT_RF(0, 66), 0x23);
|
||||
rf_wr(dev, MT_RF(0, 67), 0x01);
|
||||
mt76x0_rf_wr(dev, MT_RF(7, 73), 0x02);
|
||||
mt76x0_rf_wr(dev, MT_RF(0, 66), 0x23);
|
||||
mt76x0_rf_wr(dev, MT_RF(0, 67), 0x01);
|
||||
|
||||
mt76_wr(dev, MT_BBP(CORE, 34), 0x00080055);
|
||||
|
||||
@ -809,9 +809,9 @@ static void mt76x0_temp_sensor(struct mt76x02_dev *dev)
|
||||
}
|
||||
|
||||
done:
|
||||
rf_wr(dev, MT_RF(7, 73), rf_b7_73);
|
||||
rf_wr(dev, MT_RF(0, 66), rf_b0_66);
|
||||
rf_wr(dev, MT_RF(0, 67), rf_b0_67);
|
||||
mt76x0_rf_wr(dev, MT_RF(7, 73), rf_b7_73);
|
||||
mt76x0_rf_wr(dev, MT_RF(0, 66), rf_b0_66);
|
||||
mt76x0_rf_wr(dev, MT_RF(0, 67), rf_b0_67);
|
||||
}
|
||||
|
||||
static void mt76x0_phy_set_gain_val(struct mt76x02_dev *dev)
|
||||
@ -861,13 +861,13 @@ static void mt76x0_phy_calibration_work(struct work_struct *work)
|
||||
|
||||
mt76x0_phy_update_channel_gain(dev);
|
||||
if (!mt76x0_tssi_enabled(dev))
|
||||
mt76x0_temp_sensor(dev);
|
||||
mt76x0_phy_temp_sensor(dev);
|
||||
|
||||
ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
|
||||
MT_CALIBRATE_INTERVAL);
|
||||
}
|
||||
|
||||
static void mt76x0_rf_init(struct mt76x02_dev *dev)
|
||||
static void mt76x0_phy_rf_init(struct mt76x02_dev *dev)
|
||||
{
|
||||
int i;
|
||||
u8 val;
|
||||
@ -881,16 +881,16 @@ static void mt76x0_rf_init(struct mt76x02_dev *dev)
|
||||
const struct mt76x0_rf_switch_item *item = &mt76x0_rf_bw_switch_tab[i];
|
||||
|
||||
if (item->bw_band == RF_BW_20)
|
||||
rf_wr(dev, item->rf_bank_reg, item->value);
|
||||
mt76x0_rf_wr(dev, item->rf_bank_reg, item->value);
|
||||
else if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20))
|
||||
rf_wr(dev, item->rf_bank_reg, item->value);
|
||||
mt76x0_rf_wr(dev, item->rf_bank_reg, item->value);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mt76x0_rf_band_switch_tab); i++) {
|
||||
if (mt76x0_rf_band_switch_tab[i].bw_band & RF_G_BAND) {
|
||||
rf_wr(dev,
|
||||
mt76x0_rf_band_switch_tab[i].rf_bank_reg,
|
||||
mt76x0_rf_band_switch_tab[i].value);
|
||||
mt76x0_rf_wr(dev,
|
||||
mt76x0_rf_band_switch_tab[i].rf_bank_reg,
|
||||
mt76x0_rf_band_switch_tab[i].value);
|
||||
}
|
||||
}
|
||||
|
||||
@ -899,32 +899,32 @@ static void mt76x0_rf_init(struct mt76x02_dev *dev)
|
||||
E1: B0.R22<6:0>: xo_cxo<6:0>
|
||||
E2: B0.R21<0>: xo_cxo<0>, B0.R22<7:0>: xo_cxo<8:1>
|
||||
*/
|
||||
rf_wr(dev, MT_RF(0, 22),
|
||||
min_t(u8, dev->cal.rx.freq_offset, 0xbf));
|
||||
val = rf_rr(dev, MT_RF(0, 22));
|
||||
mt76x0_rf_wr(dev, MT_RF(0, 22),
|
||||
min_t(u8, dev->cal.rx.freq_offset, 0xbf));
|
||||
val = mt76x0_rf_rr(dev, MT_RF(0, 22));
|
||||
|
||||
/*
|
||||
Reset the DAC (Set B0.R73<7>=1, then set B0.R73<7>=0, and then set B0.R73<7>) during power up.
|
||||
*/
|
||||
val = rf_rr(dev, MT_RF(0, 73));
|
||||
val = mt76x0_rf_rr(dev, MT_RF(0, 73));
|
||||
val |= 0x80;
|
||||
rf_wr(dev, MT_RF(0, 73), val);
|
||||
mt76x0_rf_wr(dev, MT_RF(0, 73), val);
|
||||
val &= ~0x80;
|
||||
rf_wr(dev, MT_RF(0, 73), val);
|
||||
mt76x0_rf_wr(dev, MT_RF(0, 73), val);
|
||||
val |= 0x80;
|
||||
rf_wr(dev, MT_RF(0, 73), val);
|
||||
mt76x0_rf_wr(dev, MT_RF(0, 73), val);
|
||||
|
||||
/*
|
||||
vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration.
|
||||
*/
|
||||
rf_set(dev, MT_RF(0, 4), 0x80);
|
||||
mt76x0_rf_set(dev, MT_RF(0, 4), 0x80);
|
||||
}
|
||||
|
||||
void mt76x0_phy_init(struct mt76x02_dev *dev)
|
||||
{
|
||||
INIT_DELAYED_WORK(&dev->cal_work, mt76x0_phy_calibration_work);
|
||||
|
||||
mt76x0_rf_init(dev);
|
||||
mt76x0_phy_rf_init(dev);
|
||||
mt76x02_phy_set_rxpath(dev);
|
||||
mt76x02_phy_set_txdac(dev);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user