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ARM: tegra: second round of cleanups

Browse Source 
This branch mainly removes dead code following the removal of all board
 files. The removals depend on various changes in other branches, so they
 are all merged together and form the basis of this branch, as enumerated
 below.
 
 Finally, there are no remaining users of pinconf-tegra.h outside the
 pinctrl subsystem, so that header is incorporated into an existing file
 there. This reduces the number of headers in mach-tegra/include, and so
 helps move towards single zImage.
 
 This branch is based on tegra-for-3.7-cleanup, followed by a merge of
 tegra-for-3.7-board-removal, followed by a merge of
 tegra-for-3.7-common-clk, followed by a merge of:
 
 git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git xceiv-for-v3.7
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Merge tag 'tegra-for-3.7-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/cleanup2

ARM: tegra: second round of cleanups

This branch mainly removes dead code following the removal of all board
files. The removals depend on various changes in other branches, so they
are all merged together and form the basis of this branch, as enumerated
below.

Finally, there are no remaining users of pinconf-tegra.h outside the
pinctrl subsystem, so that header is incorporated into an existing file
there. This reduces the number of headers in mach-tegra/include, and so
helps move towards single zImage.

This branch is based on tegra-for-3.7-cleanup, followed by a merge of
tegra-for-3.7-board-removal, followed by a merge of
tegra-for-3.7-common-clk, followed by a merge of:

git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git xceiv-for-v3.7

By Stephen Warren (16) and others
via Stephen Warren
* tag 'tegra-for-3.7-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (29 commits)
  pinctrl: tegra: move pinconf-tegra.h content into drivers/pinctrl
  ARM: tegra: delete unused headers
  ARM: tegra: remove useless includes of <mach/*.h>
  ARM: tegra: remove dead code
  ARM: dt: tegra: harmony: configure power off
  ARM: dt: tegra: harmony: add regulators
  ARM: tegra: remove board (but not DT) support for Harmony
  ARM: tegra: remove board (but not DT) support for Paz00
  ARM: tegra: remove board (but not DT) support for TrimSlice
  ARM: Tegra: Add smp_twd clock for Tegra20
  ARM: tegra: cpu-tegra: explicitly manage re-parenting
  ARM: tegra: fix overflow in tegra20_pll_clk_round_rate()
  ARM: tegra: Fix data type for io address
  ARM: tegra: remove tegra_timer from tegra_list_clks
  ARM: tegra30: clocks: fix the wrong tegra_audio_sync_clk_ops name
  ARM: tegra: clocks: separate tegra_clk_32k_ops from Tegra20 and Tegra30
  ARM: tegra: Remove duplicate code
  ARM: tegra: Port tegra to generic clock framework
  ARM: tegra: Add clk_tegra structure and helper functions
  ARM: tegra: Rename tegra20 clock file
  ...
This commit is contained in:
Olof Johansson 2012-09-20 20:07:28 -07:00
commit 9c0cc5785d
48 changed files with 5498 additions and 7193 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

65
Documentation/devicetree/bindings/regulator/tps6586x.txt
View File

@ -8,7 +8,8 @@ Required properties:
- gpio-controller: mark the device as a GPIO controller
- regulators: list of regulators provided by this controller, must have
property "regulator-compatible" to match their hardware counterparts:
sm[0-2], ldo[0-9] and ldo_rtc
sys, sm[0-2], ldo[0-9] and ldo_rtc
- sys-supply: The input supply for SYS.
- vin-sm0-supply: The input supply for the SM0.
- vin-sm1-supply: The input supply for the SM1.
- vin-sm2-supply: The input supply for the SM2.
@ -20,6 +21,9 @@ Required properties:
Each regulator is defined using the standard binding for regulators.
Note: LDO5 and LDO_RTC is supplied by SYS regulator internally and driver
take care of making proper parent child relationship.
Example:
pmu: tps6586x@34 {
@ -30,6 +34,7 @@ Example:
#gpio-cells = <2>;
gpio-controller;
sys-supply = <&some_reg>;
vin-sm0-supply = <&some_reg>;
vin-sm1-supply = <&some_reg>;
vin-sm2-supply = <&some_reg>;
@ -43,8 +48,16 @@ Example:
#address-cells = <1>;
#size-cells = <0>;
sm0_reg: regulator@0 {
sys_reg: regulator@0 {
reg = <0>;
regulator-compatible = "sys";
regulator-name = "vdd_sys";
regulator-boot-on;
regulator-always-on;
};
sm0_reg: regulator@1 {
reg = <1>;
regulator-compatible = "sm0";
regulator-min-microvolt = < 725000>;
regulator-max-microvolt = <1500000>;
@ -52,8 +65,8 @@ Example:
regulator-always-on;
};
sm1_reg: regulator@1 {
reg = <1>;
sm1_reg: regulator@2 {
reg = <2>;
regulator-compatible = "sm1";
regulator-min-microvolt = < 725000>;
regulator-max-microvolt = <1500000>;
@ -61,8 +74,8 @@ Example:
regulator-always-on;
};
sm2_reg: regulator@2 {
reg = <2>;
sm2_reg: regulator@3 {
reg = <3>;
regulator-compatible = "sm2";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <4550000>;
@ -70,72 +83,72 @@ Example:
regulator-always-on;
};
ldo0_reg: regulator@3 {
reg = <3>;
ldo0_reg: regulator@4 {
reg = <4>;
regulator-compatible = "ldo0";
regulator-name = "PCIE CLK";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo1_reg: regulator@4 {
reg = <4>;
ldo1_reg: regulator@5 {
reg = <5>;
regulator-compatible = "ldo1";
regulator-min-microvolt = < 725000>;
regulator-max-microvolt = <1500000>;
};
ldo2_reg: regulator@5 {
reg = <5>;
ldo2_reg: regulator@6 {
reg = <6>;
regulator-compatible = "ldo2";
regulator-min-microvolt = < 725000>;
regulator-max-microvolt = <1500000>;
};
ldo3_reg: regulator@6 {
reg = <6>;
ldo3_reg: regulator@7 {
reg = <7>;
regulator-compatible = "ldo3";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;
};
ldo4_reg: regulator@7 {
reg = <7>;
ldo4_reg: regulator@8 {
reg = <8>;
regulator-compatible = "ldo4";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <2475000>;
};
ldo5_reg: regulator@8 {
reg = <8>;
ldo5_reg: regulator@9 {
reg = <9>;
regulator-compatible = "ldo5";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;
};
ldo6_reg: regulator@9 {
reg = <9>;
ldo6_reg: regulator@10 {
reg = <10>;
regulator-compatible = "ldo6";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;
};
ldo7_reg: regulator@10 {
reg = <10>;
ldo7_reg: regulator@11 {
reg = <11>;
regulator-compatible = "ldo7";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;
};
ldo8_reg: regulator@11 {
reg = <11>;
ldo8_reg: regulator@12 {
reg = <12>;
regulator-compatible = "ldo8";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;
};
ldo9_reg: regulator@12 {
reg = <12>;
ldo9_reg: regulator@13 {
reg = <13>;
regulator-compatible = "ldo9";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;

1
arch/arm/Kconfig
View File

@ -686,6 +686,7 @@ config ARCH_TEGRA
select NEED_MACH_IO_H if PCI
select ARCH_HAS_CPUFREQ
select USE_OF
select COMMON_CLK
help
This enables support for NVIDIA Tegra based systems (Tegra APX,
Tegra 6xx and Tegra 2 series).

220
arch/arm/boot/dts/tegra20-harmony.dts
View File

@ -275,6 +275,160 @@
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
interrupts = <0 86 0x4>;
ti,system-power-controller;
#gpio-cells = <2>;
gpio-controller;
sys-supply = <&vdd_5v0_reg>;
vin-sm0-supply = <&sys_reg>;
vin-sm1-supply = <&sys_reg>;
vin-sm2-supply = <&sys_reg>;
vinldo01-supply = <&sm2_reg>;
vinldo23-supply = <&sm2_reg>;
vinldo4-supply = <&sm2_reg>;
vinldo678-supply = <&sm2_reg>;
vinldo9-supply = <&sm2_reg>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
sys_reg: regulator@0 {
reg = <0>;
regulator-compatible = "sys";
regulator-name = "vdd_sys";
regulator-always-on;
};
regulator@1 {
reg = <1>;
regulator-compatible = "sm0";
regulator-name = "vdd_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
regulator@2 {
reg = <2>;
regulator-compatible = "sm1";
regulator-name = "vdd_sm1,vdd_cpu";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
sm2_reg: regulator@3 {
reg = <3>;
regulator-compatible = "sm2";
regulator-name = "vdd_sm2,vin_ldo*";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
};
regulator@4 {
reg = <4>;
regulator-compatible = "ldo0";
regulator-name = "vdd_ldo0,vddio_pex_clk";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator@5 {
reg = <5>;
regulator-compatible = "ldo1";
regulator-name = "vdd_ldo1,avdd_pll*";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
regulator@6 {
reg = <6>;
regulator-compatible = "ldo2";
regulator-name = "vdd_ldo2,vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
regulator@7 {
reg = <7>;
regulator-compatible = "ldo3";
regulator-name = "vdd_ldo3,avdd_usb*";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
regulator@8 {
reg = <8>;
regulator-compatible = "ldo4";
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
regulator@9 {
reg = <9>;
regulator-compatible = "ldo5";
regulator-name = "vdd_ldo5,vcore_mmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
regulator@10 {
reg = <10>;
regulator-compatible = "ldo6";
regulator-name = "vdd_ldo6,avdd_vdac";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@11 {
reg = <11>;
regulator-compatible = "ldo7";
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator@12 {
reg = <12>;
regulator-compatible = "ldo8";
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@13 {
reg = <13>;
regulator-compatible = "ldo9";
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
regulator@14 {
reg = <14>;
regulator-compatible = "ldo_rtc";
regulator-name = "vdd_rtc_out,vdd_cell";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
pmc {
@ -310,6 +464,72 @@
bus-width = <8>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_5v0_reg: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "vdd_1v5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&pmic 0 0>;
};
regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "vdd_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
gpio = <&pmic 1 0>;
enable-active-high;
};
regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "vdd_1v05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
gpio = <&pmic 2 0>;
enable-active-high;
/* Hack until board-harmony-pcie.c is removed */
status = "disabled";
};
regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio 22 0>; /* gpio PC6 */
enable-active-high;
};
regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio 176 0>; /* gpio PW0 */
enable-active-high;
};
};
sound {
compatible = "nvidia,tegra-audio-wm8903-harmony",
"nvidia,tegra-audio-wm8903";

20
arch/arm/mach-tegra/Kconfig
View File

@ -34,7 +34,6 @@ config ARCH_TEGRA_3x_SOC
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB
select USB_ULPI_VIEWPORT if USB_SUPPORT
select USE_OF
select ARM_ERRATA_743622
select ARM_ERRATA_751472
select ARM_ERRATA_754322
@ -60,25 +59,6 @@ config TEGRA_AHB
comment "Tegra board type"
config MACH_HARMONY
bool "Harmony board"
depends on ARCH_TEGRA_2x_SOC
help
Support for nVidia Harmony development platform
config MACH_PAZ00
bool "Paz00 board"
depends on ARCH_TEGRA_2x_SOC
help
Support for the Toshiba AC100/Dynabook AZ netbook
config MACH_TRIMSLICE
bool "TrimSlice board"
depends on ARCH_TEGRA_2x_SOC
select TEGRA_PCI
help
Support for CompuLab TrimSlice platform
choice
prompt "Default low-level debug console UART"
default TEGRA_DEBUG_UART_NONE

17
arch/arm/mach-tegra/Makefile
View File

@ -1,6 +1,4 @@
obj-y += board-pinmux.o
obj-y += common.o
obj-y += devices.o
obj-y += io.o
obj-y += irq.o
obj-y += clock.o
@ -12,9 +10,11 @@ obj-y += powergate.o
obj-y += apbio.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_CPU_IDLE) += sleep.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_SMP) += reset.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
@ -25,13 +25,6 @@ obj-$(CONFIG_TEGRA_PCI) += pcie.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
obj-$(CONFIG_MACH_HARMONY) += board-harmony.o
obj-$(CONFIG_MACH_HARMONY) += board-harmony-pinmux.o
obj-$(CONFIG_MACH_HARMONY) += board-harmony-pcie.o
obj-$(CONFIG_MACH_HARMONY) += board-harmony-power.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o
obj-$(CONFIG_MACH_PAZ00) += board-paz00.o
obj-$(CONFIG_MACH_PAZ00) += board-paz00-pinmux.o
obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o
obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o

4
arch/arm/mach-tegra/apbio.c
View File

@ -293,12 +293,12 @@ static apbio_write_fptr apbio_write;
static u32 tegra_apb_readl_direct(unsigned long offset)
{
return readl(IO_TO_VIRT(offset));
return readl(IO_ADDRESS(offset));
}
static void tegra_apb_writel_direct(u32 value, unsigned long offset)
{
writel(value, IO_TO_VIRT(offset));
writel(value, IO_ADDRESS(offset));
}
void tegra_apb_io_init(void)

51
arch/arm/mach-tegra/board-dt-tegra20.c
View File

@ -28,9 +28,11 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pda_power.h>
#include <linux/platform_data/tegra_usb.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/i2c-tegra.h>
#include <linux/usb/tegra_usb_phy.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
@ -42,9 +44,31 @@
#include <mach/irqs.h>
#include "board.h"
#include "board-harmony.h"
#include "clock.h"
#include "devices.h"
struct tegra_ehci_platform_data tegra_ehci1_pdata = {
.operating_mode = TEGRA_USB_OTG,
.power_down_on_bus_suspend = 1,
.vbus_gpio = -1,
};
struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
.reset_gpio = -1,
.clk = "cdev2",
};
struct tegra_ehci_platform_data tegra_ehci2_pdata = {
.phy_config = &tegra_ehci2_ulpi_phy_config,
.operating_mode = TEGRA_USB_HOST,
.power_down_on_bus_suspend = 1,
.vbus_gpio = -1,
};
struct tegra_ehci_platform_data tegra_ehci3_pdata = {
.operating_mode = TEGRA_USB_HOST,
.power_down_on_bus_suspend = 1,
.vbus_gpio = -1,
};
struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
@ -71,6 +95,7 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
/* name parent rate enabled */
{ "uarta", "pll_p", 216000000, true },
{ "uartd", "pll_p", 216000000, true },
{ "usbd", "clk_m", 12000000, false },
{ "usb2", "clk_m", 12000000, false },
@ -95,54 +120,40 @@ static void __init tegra_dt_init(void)
tegra20_auxdata_lookup, NULL);
}
#ifdef CONFIG_MACH_TRIMSLICE
static void __init trimslice_init(void)
{
#ifdef CONFIG_TEGRA_PCI
int ret;
ret = tegra_pcie_init(true, true);
if (ret)
pr_err("tegra_pci_init() failed: %d\n", ret);
}
#endif
}
#ifdef CONFIG_MACH_HARMONY
static void __init harmony_init(void)
{
#ifdef CONFIG_TEGRA_PCI
int ret;
ret = harmony_regulator_init();
if (ret) {
pr_err("harmony_regulator_init() failed: %d\n", ret);
return;
}
ret = harmony_pcie_init();
if (ret)
pr_err("harmony_pcie_init() failed: %d\n", ret);
}
#endif
}
#ifdef CONFIG_MACH_PAZ00
static void __init paz00_init(void)
{
tegra_paz00_wifikill_init();
}
#endif
static struct {
char *machine;
void (*init)(void);
} board_init_funcs[] = {
#ifdef CONFIG_MACH_TRIMSLICE
{ "compulab,trimslice", trimslice_init },
#endif
#ifdef CONFIG_MACH_HARMONY
{ "nvidia,harmony", harmony_init },
#endif
#ifdef CONFIG_MACH_PAZ00
{ "compal,paz00", paz00_init },
#endif
};
static void __init tegra_dt_init_late(void)

49
arch/arm/mach-tegra/board-harmony-pcie.c
View File

@ -18,35 +18,57 @@
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/err.h>
#include <linux/of_gpio.h>
#include <linux/regulator/consumer.h>
#include <asm/mach-types.h>
#include "board.h"
#include "board-harmony.h"
#ifdef CONFIG_TEGRA_PCI
int __init harmony_pcie_init(void)
{
struct device_node *np;
int en_vdd_1v05;
struct regulator *regulator = NULL;
int err;
err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05");
if (err)
np = of_find_node_by_path("/regulators/regulator@3");
if (!np) {
pr_err("%s: of_find_node_by_path failed\n", __func__);
return -ENODEV;
}
en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0);
if (en_vdd_1v05 < 0) {
pr_err("%s: of_get_named_gpio failed: %d\n", __func__,
en_vdd_1v05);
return en_vdd_1v05;
}
err = gpio_request(en_vdd_1v05, "EN_VDD_1V05");
if (err) {
pr_err("%s: gpio_request failed: %d\n", __func__, err);
return err;
}
gpio_direction_output(TEGRA_GPIO_EN_VDD_1V05_GPIO, 1);
gpio_direction_output(en_vdd_1v05, 1);
regulator = regulator_get(NULL, "pex_clk");
if (IS_ERR_OR_NULL(regulator))
regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk");
if (IS_ERR_OR_NULL(regulator)) {
pr_err("%s: regulator_get failed: %d\n", __func__,
(int)PTR_ERR(regulator));
goto err_reg;
}
regulator_enable(regulator);
err = tegra_pcie_init(true, true);
if (err)
if (err) {
pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err);
goto err_pcie;
}
return 0;
@ -54,20 +76,9 @@ err_pcie:
regulator_disable(regulator);
regulator_put(regulator);
err_reg:
gpio_free(TEGRA_GPIO_EN_VDD_1V05_GPIO);
gpio_free(en_vdd_1v05);
return err;
}
static int __init harmony_pcie_initcall(void)
{
if (!machine_is_harmony())
return 0;
return harmony_pcie_init();
}
/* PCI should be initialized after I2C, mfd and regulators */
subsys_initcall_sync(harmony_pcie_initcall);
#endif

156
arch/arm/mach-tegra/board-harmony-pinmux.c
View File

@ -1,156 +0,0 @@
/*
* arch/arm/mach-tegra/board-harmony-pinmux.c
*
* Copyright (C) 2010 Google, Inc.
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include "board-harmony.h"
#include "board-pinmux.h"
static struct pinctrl_map harmony_map[] = {
TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
TEGRA_MAP_MUXCONF("dta", "sdio2", up, driven),
TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, driven),
TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
TEGRA_MAP_MUXCONF("dtd", "sdio2", up, driven),
TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
TEGRA_MAP_MUXCONF("dtf", "i2c3", none, tristate),
TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
TEGRA_MAP_MUXCONF("gpu", "gmi", none, tristate),
TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
TEGRA_MAP_MUXCONF("irrx", "uarta", up, tristate),
TEGRA_MAP_MUXCONF("irtx", "uarta", up, tristate),
TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
TEGRA_MAP_MUXCONF("owc", "rsvd2", na, tristate),
TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, tristate),
TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
TEGRA_MAP_MUXCONF("slxd", "spdif", none, tristate),
TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, tristate),
TEGRA_MAP_MUXCONF("spia", "gmi", none, driven),
TEGRA_MAP_MUXCONF("spib", "gmi", none, driven),
TEGRA_MAP_MUXCONF("spic", "gmi", up, tristate),
TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
TEGRA_MAP_MUXCONF("uac", "rsvd2", none, tristate),
TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
TEGRA_MAP_CONF("ck32", none, na),
TEGRA_MAP_CONF("ddrc", none, na),
TEGRA_MAP_CONF("pmca", none, na),
TEGRA_MAP_CONF("pmcb", none, na),
TEGRA_MAP_CONF("pmcc", none, na),
TEGRA_MAP_CONF("pmcd", none, na),
TEGRA_MAP_CONF("pmce", none, na),
TEGRA_MAP_CONF("xm2c", none, na),
TEGRA_MAP_CONF("xm2d", none, na),
TEGRA_MAP_CONF("ls", up, na),
TEGRA_MAP_CONF("lc", up, na),
TEGRA_MAP_CONF("ld17_0", down, na),
TEGRA_MAP_CONF("ld19_18", down, na),
TEGRA_MAP_CONF("ld21_20", down, na),
TEGRA_MAP_CONF("ld23_22", down, na),
};
static struct tegra_board_pinmux_conf conf = {
.maps = harmony_map,
.map_count = ARRAY_SIZE(harmony_map),
};
void harmony_pinmux_init(void)
{
tegra_board_pinmux_init(&conf, NULL);
}

148
arch/arm/mach-tegra/board-harmony-power.c
View File

@ -1,148 +0,0 @@
/*
* Copyright (C) 2010 NVIDIA, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307, USA
*/
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/mfd/tps6586x.h>
#include <linux/of.h>
#include <linux/of_i2c.h>
#include <asm/mach-types.h>
#include <mach/irqs.h>
#include "board-harmony.h"
static struct regulator_consumer_supply tps658621_ldo0_supply[] = {
REGULATOR_SUPPLY("pex_clk", NULL),
};
static struct regulator_init_data ldo0_data = {
.supply_regulator = "vdd_sm2",
.constraints = {
.name = "vdd_ldo0",
.min_uV = 3300 * 1000,
.max_uV = 3300 * 1000,
.valid_modes_mask = (REGULATOR_MODE_NORMAL |
REGULATOR_MODE_STANDBY),
.valid_ops_mask = (REGULATOR_CHANGE_MODE |
REGULATOR_CHANGE_STATUS |
REGULATOR_CHANGE_VOLTAGE),
.apply_uV = 1,
},
.num_consumer_supplies = ARRAY_SIZE(tps658621_ldo0_supply),
.consumer_supplies = tps658621_ldo0_supply,
};
#define HARMONY_REGULATOR_INIT(_id, _name, _supply, _minmv, _maxmv, _on)\
static struct regulator_init_data _id##_data = { \
.supply_regulator = _supply, \
.constraints = { \
.name = _name, \
.min_uV = (_minmv)*1000, \
.max_uV = (_maxmv)*1000, \
.valid_modes_mask = (REGULATOR_MODE_NORMAL | \
REGULATOR_MODE_STANDBY), \
.valid_ops_mask = (REGULATOR_CHANGE_MODE | \
REGULATOR_CHANGE_STATUS | \
REGULATOR_CHANGE_VOLTAGE), \
.always_on = _on, \
}, \
}
HARMONY_REGULATOR_INIT(sm0, "vdd_sm0", "vdd_sys", 725, 1500, 1);
HARMONY_REGULATOR_INIT(sm1, "vdd_sm1", "vdd_sys", 725, 1500, 1);
HARMONY_REGULATOR_INIT(sm2, "vdd_sm2", "vdd_sys", 3000, 4550, 1);
HARMONY_REGULATOR_INIT(ldo1, "vdd_ldo1", "vdd_sm2", 725, 1500, 1);
HARMONY_REGULATOR_INIT(ldo2, "vdd_ldo2", "vdd_sm2", 725, 1500, 0);
HARMONY_REGULATOR_INIT(ldo3, "vdd_ldo3", "vdd_sm2", 1250, 3300, 1);
HARMONY_REGULATOR_INIT(ldo4, "vdd_ldo4", "vdd_sm2", 1700, 2475, 1);
HARMONY_REGULATOR_INIT(ldo5, "vdd_ldo5", NULL, 1250, 3300, 1);
HARMONY_REGULATOR_INIT(ldo6, "vdd_ldo6", "vdd_sm2", 1250, 3300, 0);
HARMONY_REGULATOR_INIT(ldo7, "vdd_ldo7", "vdd_sm2", 1250, 3300, 0);
HARMONY_REGULATOR_INIT(ldo8, "vdd_ldo8", "vdd_sm2", 1250, 3300, 0);
HARMONY_REGULATOR_INIT(ldo9, "vdd_ldo9", "vdd_sm2", 1250, 3300, 1);
#define TPS_REG(_id, _data) \
{ \
.id = TPS6586X_ID_##_id, \
.name = "tps6586x-regulator", \
.platform_data = _data, \
}
static struct tps6586x_subdev_info tps_devs[] = {
TPS_REG(SM_0, &sm0_data),
TPS_REG(SM_1, &sm1_data),
TPS_REG(SM_2, &sm2_data),
TPS_REG(LDO_0, &ldo0_data),
TPS_REG(LDO_1, &ldo1_data),
TPS_REG(LDO_2, &ldo2_data),
TPS_REG(LDO_3, &ldo3_data),
TPS_REG(LDO_4, &ldo4_data),
TPS_REG(LDO_5, &ldo5_data),
TPS_REG(LDO_6, &ldo6_data),
TPS_REG(LDO_7, &ldo7_data),
TPS_REG(LDO_8, &ldo8_data),
TPS_REG(LDO_9, &ldo9_data),
};
static struct tps6586x_platform_data tps_platform = {
.irq_base = TEGRA_NR_IRQS,
.num_subdevs = ARRAY_SIZE(tps_devs),
.subdevs = tps_devs,
.gpio_base = HARMONY_GPIO_TPS6586X(0),
};
static struct i2c_board_info __initdata harmony_regulators[] = {
{
I2C_BOARD_INFO("tps6586x", 0x34),
.irq = INT_EXTERNAL_PMU,
.platform_data = &tps_platform,
},
};
int __init harmony_regulator_init(void)
{
regulator_register_always_on(0, "vdd_sys",
NULL, 0, 5000000);
if (machine_is_harmony()) {
i2c_register_board_info(3, harmony_regulators, 1);
} else { /* Harmony, booted using device tree */
struct device_node *np;
struct i2c_adapter *adapter;
np = of_find_node_by_path("/i2c@7000d000");
if (np == NULL) {
pr_err("Could not find device_node for DVC I2C\n");
return -ENODEV;
}
adapter = of_find_i2c_adapter_by_node(np);
if (!adapter) {
pr_err("Could not find i2c_adapter for DVC I2C\n");
return -ENODEV;
}
i2c_new_device(adapter, harmony_regulators);
}
return 0;
}

197
arch/arm/mach-tegra/board-harmony.c
View File

@ -1,197 +0,0 @@
/*
* arch/arm/mach-tegra/board-harmony.c
*
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2011 NVIDIA, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/of_serial.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/pda_power.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <sound/wm8903.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/hardware/gic.h>
#include <asm/setup.h>
#include <mach/tegra_wm8903_pdata.h>
#include <mach/iomap.h>
#include <mach/irqs.h>
#include <mach/sdhci.h>
#include "board.h"
#include "board-harmony.h"
#include "clock.h"
#include "devices.h"
#include "gpio-names.h"
static struct plat_serial8250_port debug_uart_platform_data[] = {
{
.membase = IO_ADDRESS(TEGRA_UARTD_BASE),
.mapbase = TEGRA_UARTD_BASE,
.irq = INT_UARTD,
.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
.type = PORT_TEGRA,
.handle_break = tegra_serial_handle_break,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 216000000,
}, {
.flags = 0
}
};
static struct platform_device debug_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = debug_uart_platform_data,
},
};
static struct tegra_wm8903_platform_data harmony_audio_pdata = {
.gpio_spkr_en = TEGRA_GPIO_SPKR_EN,
.gpio_hp_det = TEGRA_GPIO_HP_DET,
.gpio_hp_mute = -1,
.gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN,
.gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN,
};
static struct platform_device harmony_audio_device = {
.name = "tegra-snd-wm8903",
.id = 0,
.dev = {
.platform_data = &harmony_audio_pdata,
},
};
static struct wm8903_platform_data harmony_wm8903_pdata = {
.irq_active_low = 0,
.micdet_cfg = 0,
.micdet_delay = 100,
.gpio_base = HARMONY_GPIO_WM8903(0),
.gpio_cfg = {
0,
0,
WM8903_GPIO_CONFIG_ZERO,
0,
0,
},
};
static struct i2c_board_info __initdata wm8903_board_info = {
I2C_BOARD_INFO("wm8903", 0x1a),
.platform_data = &harmony_wm8903_pdata,
};
static void __init harmony_i2c_init(void)
{
platform_device_register(&tegra_i2c_device1);
platform_device_register(&tegra_i2c_device2);
platform_device_register(&tegra_i2c_device3);
platform_device_register(&tegra_i2c_device4);
wm8903_board_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
i2c_register_board_info(0, &wm8903_board_info, 1);
}
static struct platform_device *harmony_devices[] __initdata = {
&debug_uart,
&tegra_sdhci_device1,
&tegra_sdhci_device2,
&tegra_sdhci_device4,
&tegra_ehci3_device,
&tegra_i2s_device1,
&tegra_das_device,
&harmony_audio_device,
};
static void __init tegra_harmony_fixup(struct tag *tags, char **cmdline,
struct meminfo *mi)
{
mi->nr_banks = 2;
mi->bank[0].start = PHYS_OFFSET;
mi->bank[0].size = 448 * SZ_1M;
mi->bank[1].start = SZ_512M;
mi->bank[1].size = SZ_512M;
}
static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
/* name parent rate enabled */
{ "uartd", "pll_p", 216000000, true },
{ "pll_a", "pll_p_out1", 56448000, true },
{ "pll_a_out0", "pll_a", 11289600, true },
{ "cdev1", NULL, 0, true },
{ "i2s1", "pll_a_out0", 11289600, false},
{ "usb3", "clk_m", 12000000, true },
{ NULL, NULL, 0, 0},
};
static struct tegra_sdhci_platform_data sdhci_pdata1 = {
.cd_gpio = -1,
.wp_gpio = -1,
.power_gpio = -1,
};
static struct tegra_sdhci_platform_data sdhci_pdata2 = {
.cd_gpio = TEGRA_GPIO_SD2_CD,
.wp_gpio = TEGRA_GPIO_SD2_WP,
.power_gpio = TEGRA_GPIO_SD2_POWER,
};
static struct tegra_sdhci_platform_data sdhci_pdata4 = {
.cd_gpio = TEGRA_GPIO_SD4_CD,
.wp_gpio = TEGRA_GPIO_SD4_WP,
.power_gpio = TEGRA_GPIO_SD4_POWER,
.is_8bit = 1,
};
static void __init tegra_harmony_init(void)
{
tegra_clk_init_from_table(harmony_clk_init_table);
harmony_pinmux_init();
tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2;
tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
harmony_i2c_init();
harmony_regulator_init();
}
MACHINE_START(HARMONY, "harmony")
.atag_offset = 0x100,
.fixup = tegra_harmony_fixup,
.map_io = tegra_map_common_io,
.init_early = tegra20_init_early,
.init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,
.init_machine = tegra_harmony_init,
.init_late = tegra_init_late,
.restart = tegra_assert_system_reset,
MACHINE_END

41
arch/arm/mach-tegra/board-harmony.h
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@ -1,41 +0,0 @@
/*
* arch/arm/mach-tegra/board-harmony.h
*
* Copyright (C) 2010 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _MACH_TEGRA_BOARD_HARMONY_H
#define _MACH_TEGRA_BOARD_HARMONY_H
#include <mach/gpio-tegra.h>
#define HARMONY_GPIO_TPS6586X(_x_) (TEGRA_NR_GPIOS + (_x_))
#define HARMONY_GPIO_WM8903(_x_) (HARMONY_GPIO_TPS6586X(4) + (_x_))
#define TEGRA_GPIO_SD2_CD TEGRA_GPIO_PI5
#define TEGRA_GPIO_SD2_WP TEGRA_GPIO_PH1
#define TEGRA_GPIO_SD2_POWER TEGRA_GPIO_PT3
#define TEGRA_GPIO_SD4_CD TEGRA_GPIO_PH2
#define TEGRA_GPIO_SD4_WP TEGRA_GPIO_PH3
#define TEGRA_GPIO_SD4_POWER TEGRA_GPIO_PI6
#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PX3
#define TEGRA_GPIO_SPKR_EN HARMONY_GPIO_WM8903(2)
#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PW2
#define TEGRA_GPIO_INT_MIC_EN TEGRA_GPIO_PX0
#define TEGRA_GPIO_EXT_MIC_EN TEGRA_GPIO_PX1
#define TEGRA_GPIO_EN_VDD_1V05_GPIO HARMONY_GPIO_TPS6586X(2)
void harmony_pinmux_init(void);
int harmony_regulator_init(void);
#endif

156
arch/arm/mach-tegra/board-paz00-pinmux.c
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@ -1,156 +0,0 @@
/*
* arch/arm/mach-tegra/board-paz00-pinmux.c
*
* Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include "board-paz00.h"
#include "board-pinmux.h"
static struct pinctrl_map paz00_map[] = {
TEGRA_MAP_MUXCONF("ata", "gmi", none, driven),
TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
TEGRA_MAP_MUXCONF("atc", "gmi", none, driven),
TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, driven),
TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
TEGRA_MAP_MUXCONF("csus", "pllc_out1", down, tristate),
TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
TEGRA_MAP_MUXCONF("dap2", "gmi", none, driven),
TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
TEGRA_MAP_MUXCONF("dta", "rsvd1", up, tristate),
TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, tristate),
TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
TEGRA_MAP_MUXCONF("dtd", "rsvd1", up, tristate),
TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
TEGRA_MAP_MUXCONF("gmc", "gmi", none, driven),
TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
TEGRA_MAP_MUXCONF("hdint", "hdmi", na, driven),
TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
TEGRA_MAP_MUXCONF("irrx", "uarta", up, driven),
TEGRA_MAP_MUXCONF("irtx", "uarta", up, driven),
TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
TEGRA_MAP_MUXCONF("kbcb", "sdio2", up, driven),
TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
TEGRA_MAP_MUXCONF("kbcd", "sdio2", up, driven),
TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ldc", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lhp0", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lhp1", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lhp2", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lm0", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lpp", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lpw0", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lpw2", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lvp1", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
TEGRA_MAP_MUXCONF("owc", "owr", up, tristate),
TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
TEGRA_MAP_MUXCONF("sdc", "twc", up, tristate),
TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
TEGRA_MAP_MUXCONF("slxa", "pcie", none, tristate),
TEGRA_MAP_MUXCONF("slxc", "spi4", none, tristate),
TEGRA_MAP_MUXCONF("slxd", "spi4", none, tristate),
TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
TEGRA_MAP_MUXCONF("spia", "gmi", down, tristate),
TEGRA_MAP_MUXCONF("spib", "gmi", down, tristate),
TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
TEGRA_MAP_MUXCONF("spid", "gmi", down, tristate),
TEGRA_MAP_MUXCONF("spie", "gmi", up, tristate),
TEGRA_MAP_MUXCONF("spif", "rsvd4", down, tristate),
TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, driven),
TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
TEGRA_MAP_MUXCONF("uac", "rsvd4", none, driven),
TEGRA_MAP_MUXCONF("uad", "spdif", up, tristate),
TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
TEGRA_MAP_CONF("ck32", none, na),
TEGRA_MAP_CONF("ddrc", none, na),
TEGRA_MAP_CONF("pmca", none, na),
TEGRA_MAP_CONF("pmcb", none, na),
TEGRA_MAP_CONF("pmcc", none, na),
TEGRA_MAP_CONF("pmcd", none, na),
TEGRA_MAP_CONF("pmce", none, na),
TEGRA_MAP_CONF("xm2c", none, na),
TEGRA_MAP_CONF("xm2d", none, na),
TEGRA_MAP_CONF("ls", up, na),
TEGRA_MAP_CONF("lc", up, na),
TEGRA_MAP_CONF("ld17_0", down, na),
TEGRA_MAP_CONF("ld19_18", down, na),
TEGRA_MAP_CONF("ld21_20", down, na),
TEGRA_MAP_CONF("ld23_22", down, na),
};
static struct tegra_board_pinmux_conf conf = {
.maps = paz00_map,
.map_count = ARRAY_SIZE(paz00_map),
};
void paz00_pinmux_init(void)
{
tegra_board_pinmux_init(&conf, NULL);
}

192
arch/arm/mach-tegra/board-paz00.c
View File

@ -17,72 +17,10 @@
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/of_serial.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/gpio_keys.h>
#include <linux/pda_power.h>
#include <linux/io.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/rfkill-gpio.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/setup.h>
#include <mach/iomap.h>
#include <mach/irqs.h>
#include <mach/sdhci.h>
#include "board.h"
#include "board-paz00.h"
#include "clock.h"
#include "devices.h"
#include "gpio-names.h"
static struct plat_serial8250_port debug_uart_platform_data[] = {
{
/* serial port on JP1 */
.membase = IO_ADDRESS(TEGRA_UARTA_BASE),
.mapbase = TEGRA_UARTA_BASE,
.irq = INT_UARTA,
.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
.type = PORT_TEGRA,
.handle_break = tegra_serial_handle_break,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 216000000,
}, {
/* serial port on mini-pcie */
.membase = IO_ADDRESS(TEGRA_UARTC_BASE),
.mapbase = TEGRA_UARTC_BASE,
.irq = INT_UARTC,
.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
.type = PORT_TEGRA,
.handle_break = tegra_serial_handle_break,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 216000000,
}, {
.flags = 0
}
};
static struct platform_device debug_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = debug_uart_platform_data,
},
};
static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
.name = "wifi_rfkill",
@ -99,137 +37,7 @@ static struct platform_device wifi_rfkill_device = {
},
};
static struct gpio_led gpio_leds[] = {
{
.name = "wifi-led",
.default_trigger = "rfkill0",
.gpio = TEGRA_WIFI_LED,
},
};
static struct gpio_led_platform_data gpio_led_info = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct platform_device leds_gpio = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &gpio_led_info,
},
};
static struct gpio_keys_button paz00_gpio_keys_buttons[] = {
{
.code = KEY_POWER,
.gpio = TEGRA_GPIO_POWERKEY,
.active_low = 1,
.desc = "Power",
.type = EV_KEY,
.wakeup = 1,
},
};
static struct gpio_keys_platform_data paz00_gpio_keys = {
.buttons = paz00_gpio_keys_buttons,
.nbuttons = ARRAY_SIZE(paz00_gpio_keys_buttons),
};
static struct platform_device gpio_keys_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &paz00_gpio_keys,
},
};
static struct platform_device *paz00_devices[] __initdata = {
&debug_uart,
&tegra_sdhci_device4,
&tegra_sdhci_device1,
&leds_gpio,
&gpio_keys_device,
};
static void paz00_i2c_init(void)
{
platform_device_register(&tegra_i2c_device1);
platform_device_register(&tegra_i2c_device2);
platform_device_register(&tegra_i2c_device4);
}
static void paz00_usb_init(void)
{
tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_ULPI_RST;
platform_device_register(&tegra_ehci2_device);
platform_device_register(&tegra_ehci3_device);
}
static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
struct meminfo *mi)
{
mi->nr_banks = 1;
mi->bank[0].start = PHYS_OFFSET;
mi->bank[0].size = 448 * SZ_1M;
}
static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
/* name parent rate enabled */
{ "uarta", "pll_p", 216000000, true },
{ "uartc", "pll_p", 216000000, true },
{ "usbd", "clk_m", 12000000, false },
{ "usb2", "clk_m", 12000000, false },
{ "usb3", "clk_m", 12000000, false },
{ NULL, NULL, 0, 0},
};
static struct tegra_sdhci_platform_data sdhci_pdata1 = {
.cd_gpio = TEGRA_GPIO_SD1_CD,
.wp_gpio = TEGRA_GPIO_SD1_WP,
.power_gpio = TEGRA_GPIO_SD1_POWER,
};
static struct tegra_sdhci_platform_data sdhci_pdata4 = {
.cd_gpio = -1,
.wp_gpio = -1,
.power_gpio = -1,
.is_8bit = 1,
};
void __init tegra_paz00_wifikill_init(void)
{
platform_device_register(&wifi_rfkill_device);
}
static void __init tegra_paz00_init(void)
{
tegra_clk_init_from_table(paz00_clk_init_table);
paz00_pinmux_init();
tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
tegra_paz00_wifikill_init();
paz00_i2c_init();
paz00_usb_init();
}
MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
.atag_offset = 0x100,
.fixup = tegra_paz00_fixup,
.map_io = tegra_map_common_io,
.init_early = tegra20_init_early,
.init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,
.init_machine = tegra_paz00_init,
.init_late = tegra_init_late,
.restart = tegra_assert_system_reset,
MACHINE_END

17
arch/arm/mach-tegra/board-paz00.h
View File

@ -17,24 +17,9 @@
#ifndef _MACH_TEGRA_BOARD_PAZ00_H
#define _MACH_TEGRA_BOARD_PAZ00_H
#include <mach/gpio-tegra.h>
#include "gpio-names.h"
/* SDCARD */
#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5
#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1
#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PV1
/* ULPI */
#define TEGRA_ULPI_RST TEGRA_GPIO_PV0
/* WIFI */
#define TEGRA_WIFI_PWRN TEGRA_GPIO_PK5
#define TEGRA_WIFI_RST TEGRA_GPIO_PD1
#define TEGRA_WIFI_LED TEGRA_GPIO_PD0
/* WakeUp */
#define TEGRA_GPIO_POWERKEY TEGRA_GPIO_PJ7
void paz00_pinmux_init(void);
#endif

87
arch/arm/mach-tegra/board-pinmux.c
View File

@ -1,87 +0,0 @@
/*
* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/notifier.h>
#include <linux/string.h>
#include "board-pinmux.h"
#include "devices.h"
unsigned long tegra_pincfg_pullnone_driven[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
};
unsigned long tegra_pincfg_pullnone_tristate[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
};
unsigned long tegra_pincfg_pullnone_na[1] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
};
unsigned long tegra_pincfg_pullup_driven[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
};
unsigned long tegra_pincfg_pullup_tristate[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
};
unsigned long tegra_pincfg_pullup_na[1] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
};
unsigned long tegra_pincfg_pulldown_driven[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
};
unsigned long tegra_pincfg_pulldown_tristate[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
};
unsigned long tegra_pincfg_pulldown_na[1] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
};
unsigned long tegra_pincfg_pullna_driven[1] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
};
unsigned long tegra_pincfg_pullna_tristate[1] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
};
static struct platform_device *devices[] = {
&tegra_gpio_device,
&tegra_pinmux_device,
};
void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
struct tegra_board_pinmux_conf *conf_b)
{
if (conf_a)
pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
if (conf_b)
pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
platform_add_devices(devices, ARRAY_SIZE(devices));
}

54
arch/arm/mach-tegra/board-pinmux.h
View File

@ -1,54 +0,0 @@
/*
* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_BOARD_PINMUX_H
#define __MACH_TEGRA_BOARD_PINMUX_H
#include <linux/pinctrl/machine.h>
#include <mach/pinconf-tegra.h>
#define PINMUX_DEV "tegra20-pinctrl"
#define TEGRA_MAP_MUX(_group_, _function_) \
PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
TEGRA_MAP_MUX(_group_, _function_), \
TEGRA_MAP_CONF(_group_, _pull_, _drive_)
extern unsigned long tegra_pincfg_pullnone_driven[2];
extern unsigned long tegra_pincfg_pullnone_tristate[2];
extern unsigned long tegra_pincfg_pullnone_na[1];
extern unsigned long tegra_pincfg_pullup_driven[2];
extern unsigned long tegra_pincfg_pullup_tristate[2];
extern unsigned long tegra_pincfg_pullup_na[1];
extern unsigned long tegra_pincfg_pulldown_driven[2];
extern unsigned long tegra_pincfg_pulldown_tristate[2];
extern unsigned long tegra_pincfg_pulldown_na[1];
extern unsigned long tegra_pincfg_pullna_driven[1];
extern unsigned long tegra_pincfg_pullna_tristate[1];
struct tegra_board_pinmux_conf {
struct pinctrl_map *maps;
int map_count;
};
void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
struct tegra_board_pinmux_conf *conf_b);
#endif

155
arch/arm/mach-tegra/board-trimslice-pinmux.c
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@ -1,155 +0,0 @@
/*
* arch/arm/mach-tegra/board-trimslice-pinmux.c
*
* Copyright (C) 2011 CompuLab, Ltd.
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include "board-trimslice.h"
#include "board-pinmux.h"
static struct pinctrl_map trimslice_map[] = {
TEGRA_MAP_MUXCONF("ata", "ide", none, tristate),
TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
TEGRA_MAP_MUXCONF("atc", "nand", none, tristate),
TEGRA_MAP_MUXCONF("atd", "gmi", none, tristate),
TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
TEGRA_MAP_MUXCONF("dta", "vi", none, tristate),
TEGRA_MAP_MUXCONF("dtb", "vi", none, tristate),
TEGRA_MAP_MUXCONF("dtc", "vi", none, tristate),
TEGRA_MAP_MUXCONF("dtd", "vi", none, tristate),
TEGRA_MAP_MUXCONF("dte", "vi", none, tristate),
TEGRA_MAP_MUXCONF("dtf", "i2c3", up, driven),
TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
TEGRA_MAP_MUXCONF("gmb", "nand", none, tristate),
TEGRA_MAP_MUXCONF("gmc", "sflash", none, driven),
TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
TEGRA_MAP_MUXCONF("gme", "gmi", none, tristate),
TEGRA_MAP_MUXCONF("gpu", "uarta", none, driven),
TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, tristate),
TEGRA_MAP_MUXCONF("irrx", "uartb", up, tristate),
TEGRA_MAP_MUXCONF("irtx", "uartb", up, tristate),
TEGRA_MAP_MUXCONF("kbca", "kbc", up, tristate),
TEGRA_MAP_MUXCONF("kbcb", "kbc", up, tristate),
TEGRA_MAP_MUXCONF("kbcc", "kbc", up, tristate),
TEGRA_MAP_MUXCONF("kbcd", "kbc", up, tristate),
TEGRA_MAP_MUXCONF("kbce", "kbc", up, tristate),
TEGRA_MAP_MUXCONF("kbcf", "kbc", up, tristate),
TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
TEGRA_MAP_MUXCONF("owc", "rsvd2", up, tristate),
TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, tristate),
TEGRA_MAP_MUXCONF("pta", "gmi", none, tristate),
TEGRA_MAP_MUXCONF("rm", "i2c1", up, driven),
TEGRA_MAP_MUXCONF("sdb", "pwm", na, driven),
TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
TEGRA_MAP_MUXCONF("sdd", "pwm", up, driven),
TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
TEGRA_MAP_MUXCONF("slxc", "sdio3", none, tristate),
TEGRA_MAP_MUXCONF("slxd", "sdio3", none, tristate),
TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
TEGRA_MAP_MUXCONF("spdi", "spdif", none, tristate),
TEGRA_MAP_MUXCONF("spdo", "spdif", none, tristate),
TEGRA_MAP_MUXCONF("spia", "spi2", down, tristate),
TEGRA_MAP_MUXCONF("spib", "spi2", down, tristate),
TEGRA_MAP_MUXCONF("spic", "spi2", up, tristate),
TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
TEGRA_MAP_CONF("ck32", none, na),
TEGRA_MAP_CONF("ddrc", none, na),
TEGRA_MAP_CONF("pmca", none, na),
TEGRA_MAP_CONF("pmcb", none, na),
TEGRA_MAP_CONF("pmcc", none, na),
TEGRA_MAP_CONF("pmcd", none, na),
TEGRA_MAP_CONF("pmce", none, na),
TEGRA_MAP_CONF("xm2c", none, na),
TEGRA_MAP_CONF("xm2d", none, na),
TEGRA_MAP_CONF("ls", up, na),
TEGRA_MAP_CONF("lc", up, na),
TEGRA_MAP_CONF("ld17_0", down, na),
TEGRA_MAP_CONF("ld19_18", down, na),
TEGRA_MAP_CONF("ld21_20", down, na),
TEGRA_MAP_CONF("ld23_22", down, na),
};
static struct tegra_board_pinmux_conf conf = {
.maps = trimslice_map,
.map_count = ARRAY_SIZE(trimslice_map),
};
void trimslice_pinmux_init(void)
{
tegra_board_pinmux_init(&conf, NULL);
}

183
arch/arm/mach-tegra/board-trimslice.c
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@ -1,183 +0,0 @@
/*
* arch/arm/mach-tegra/board-trimslice.c
*
* Copyright (C) 2011 CompuLab, Ltd.
* Author: Mike Rapoport <mike@compulab.co.il>
*
* Based on board-harmony.c
* Copyright (C) 2010 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/of_serial.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/platform_data/tegra_usb.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/setup.h>
#include <mach/iomap.h>
#include <mach/sdhci.h>
#include "board.h"
#include "clock.h"
#include "devices.h"
#include "gpio-names.h"
#include "board-trimslice.h"
static struct plat_serial8250_port debug_uart_platform_data[] = {
{
.membase = IO_ADDRESS(TEGRA_UARTA_BASE),
.mapbase = TEGRA_UARTA_BASE,
.irq = INT_UARTA,
.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
.type = PORT_TEGRA,
.handle_break = tegra_serial_handle_break,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 216000000,
}, {
.flags = 0
}
};
static struct platform_device debug_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = debug_uart_platform_data,
},
};
static struct tegra_sdhci_platform_data sdhci_pdata1 = {
.cd_gpio = -1,
.wp_gpio = -1,
.power_gpio = -1,
};
static struct tegra_sdhci_platform_data sdhci_pdata4 = {
.cd_gpio = TRIMSLICE_GPIO_SD4_CD,
.wp_gpio = TRIMSLICE_GPIO_SD4_WP,
.power_gpio = -1,
};
static struct platform_device trimslice_audio_device = {
.name = "tegra-snd-trimslice",
.id = 0,
};
static struct platform_device *trimslice_devices[] __initdata = {
&debug_uart,
&tegra_sdhci_device1,
&tegra_sdhci_device4,
&tegra_i2s_device1,
&tegra_das_device,
&trimslice_audio_device,
};
static struct i2c_board_info trimslice_i2c3_board_info[] = {
{
I2C_BOARD_INFO("tlv320aic23", 0x1a),
},
{
I2C_BOARD_INFO("em3027", 0x56),
},
};
static void trimslice_i2c_init(void)
{
platform_device_register(&tegra_i2c_device1);
platform_device_register(&tegra_i2c_device2);
platform_device_register(&tegra_i2c_device3);
i2c_register_board_info(2, trimslice_i2c3_board_info,
ARRAY_SIZE(trimslice_i2c3_board_info));
}
static void trimslice_usb_init(void)
{
struct tegra_ehci_platform_data *pdata;
pdata = tegra_ehci1_device.dev.platform_data;
pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_GPIO_PV0;
platform_device_register(&tegra_ehci3_device);
platform_device_register(&tegra_ehci2_device);
platform_device_register(&tegra_ehci1_device);
}
static void __init tegra_trimslice_fixup(struct tag *tags, char **cmdline,
struct meminfo *mi)
{
mi->nr_banks = 2;
mi->bank[0].start = PHYS_OFFSET;
mi->bank[0].size = 448 * SZ_1M;
mi->bank[1].start = SZ_512M;
mi->bank[1].size = SZ_512M;
}
static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
/* name parent rate enabled */
{ "uarta", "pll_p", 216000000, true },
{ "pll_a", "pll_p_out1", 56448000, true },
{ "pll_a_out0", "pll_a", 11289600, true },
{ "cdev1", NULL, 0, true },
{ "i2s1", "pll_a_out0", 11289600, false},
{ NULL, NULL, 0, 0},
};
static int __init tegra_trimslice_pci_init(void)
{
if (!machine_is_trimslice())
return 0;
return tegra_pcie_init(true, true);
}
subsys_initcall(tegra_trimslice_pci_init);
static void __init tegra_trimslice_init(void)
{
tegra_clk_init_from_table(trimslice_clk_init_table);
trimslice_pinmux_init();
tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices));
trimslice_i2c_init();
trimslice_usb_init();
}
MACHINE_START(TRIMSLICE, "trimslice")
.atag_offset = 0x100,
.fixup = tegra_trimslice_fixup,
.map_io = tegra_map_common_io,
.init_early = tegra20_init_early,
.init_irq = tegra_init_irq,
.handle_irq = gic_handle_irq,
.timer = &tegra_timer,
.init_machine = tegra_trimslice_init,
.init_late = tegra_init_late,
.restart = tegra_assert_system_reset,
MACHINE_END

30
arch/arm/mach-tegra/board-trimslice.h
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@ -1,30 +0,0 @@
/*
* arch/arm/mach-tegra/board-trimslice.h
*
* Copyright (C) 2011 CompuLab, Ltd.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _MACH_TEGRA_BOARD_TRIMSLICE_H
#define _MACH_TEGRA_BOARD_TRIMSLICE_H
#include <mach/gpio-tegra.h>
#define TRIMSLICE_GPIO_SD4_CD TEGRA_GPIO_PP1 /* mmc4 cd */
#define TRIMSLICE_GPIO_SD4_WP TEGRA_GPIO_PP2 /* mmc4 wp */
#define TRIMSLICE_GPIO_USB1_MODE TEGRA_GPIO_PV2 /* USB1 mode */
#define TRIMSLICE_GPIO_USB2_RST TEGRA_GPIO_PV0 /* USB2 PHY reset */
void trimslice_pinmux_init(void);
#endif

572
arch/arm/mach-tegra/clock.c
View File

@ -1,6 +1,7 @@
/*
*
* Copyright (C) 2010 Google, Inc.
* Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Colin Cross <ccross@google.com>
@ -19,8 +20,6 @@
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
@ -36,40 +35,30 @@
/*
* Locking:
*
* Each struct clk has a spinlock.
*
* To avoid AB-BA locking problems, locks must always be traversed from child
* clock to parent clock. For example, when enabling a clock, the clock's lock
* is taken, and then clk_enable is called on the parent, which take's the
* parent clock's lock. There is one exceptions to this ordering: When dumping
* the clock tree through debugfs. In this case, clk_lock_all is called,
* which attemps to iterate through the entire list of clocks and take every
* clock lock. If any call to spin_trylock fails, all locked clocks are
* unlocked, and the process is retried. When all the locks are held,
* the only clock operation that can be called is clk_get_rate_all_locked.
*
* Within a single clock, no clock operation can call another clock operation
* on itself, except for clk_get_rate_locked and clk_set_rate_locked. Any
* clock operation can call any other clock operation on any of it's possible
* parents.
*
* An additional mutex, clock_list_lock, is used to protect the list of all
* clocks.
*
* The clock operations must lock internally to protect against
* read-modify-write on registers that are shared by multiple clocks
*/
static DEFINE_MUTEX(clock_list_lock);
static LIST_HEAD(clocks);
void tegra_clk_add(struct clk *clk)
{
struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
mutex_lock(&clock_list_lock);
list_add(&c->node, &clocks);
mutex_unlock(&clock_list_lock);
}
struct clk *tegra_get_clock_by_name(const char *name)
{
struct clk *c;
struct clk_tegra *c;
struct clk *ret = NULL;
mutex_lock(&clock_list_lock);
list_for_each_entry(c, &clocks, node) {
if (strcmp(c->name, name) == 0) {
ret = c;
if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
ret = c->hw.clk;
break;
}
}
@ -77,280 +66,36 @@ struct clk *tegra_get_clock_by_name(const char *name)
return ret;
}
/* Must be called with c->spinlock held */
static unsigned long clk_predict_rate_from_parent(struct clk *c, struct clk *p)
{
u64 rate;
rate = clk_get_rate(p);
if (c->mul != 0 && c->div != 0) {
rate *= c->mul;
rate += c->div - 1; /* round up */
do_div(rate, c->div);
}
return rate;
}
/* Must be called with c->spinlock held */
unsigned long clk_get_rate_locked(struct clk *c)
{
unsigned long rate;
if (c->parent)
rate = clk_predict_rate_from_parent(c, c->parent);
else
rate = c->rate;
return rate;
}
unsigned long clk_get_rate(struct clk *c)
{
unsigned long flags;
unsigned long rate;
spin_lock_irqsave(&c->spinlock, flags);
rate = clk_get_rate_locked(c);
spin_unlock_irqrestore(&c->spinlock, flags);
return rate;
}
EXPORT_SYMBOL(clk_get_rate);
int clk_reparent(struct clk *c, struct clk *parent)
{
c->parent = parent;
return 0;
}
void clk_init(struct clk *c)
{
spin_lock_init(&c->spinlock);
if (c->ops && c->ops->init)
c->ops->init(c);
if (!c->ops || !c->ops->enable) {
c->refcnt++;
c->set = true;
if (c->parent)
c->state = c->parent->state;
else
c->state = ON;
}
mutex_lock(&clock_list_lock);
list_add(&c->node, &clocks);
mutex_unlock(&clock_list_lock);
}
int clk_enable(struct clk *c)
{
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&c->spinlock, flags);
if (c->refcnt == 0) {
if (c->parent) {
ret = clk_enable(c->parent);
if (ret)
goto out;
}
if (c->ops && c->ops->enable) {
ret = c->ops->enable(c);
if (ret) {
if (c->parent)
clk_disable(c->parent);
goto out;
}
c->state = ON;
c->set = true;
}
}
c->refcnt++;
out:
spin_unlock_irqrestore(&c->spinlock, flags);
return ret;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *c)
{
unsigned long flags;
spin_lock_irqsave(&c->spinlock, flags);
if (c->refcnt == 0) {
WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
spin_unlock_irqrestore(&c->spinlock, flags);
return;
}
if (c->refcnt == 1) {
if (c->ops && c->ops->disable)
c->ops->disable(c);
if (c->parent)
clk_disable(c->parent);
c->state = OFF;
}
c->refcnt--;
spin_unlock_irqrestore(&c->spinlock, flags);
}
EXPORT_SYMBOL(clk_disable);
int clk_set_parent(struct clk *c, struct clk *parent)
{
int ret;
unsigned long flags;
unsigned long new_rate;
unsigned long old_rate;
spin_lock_irqsave(&c->spinlock, flags);
if (!c->ops || !c->ops->set_parent) {
ret = -ENOSYS;
goto out;
}
new_rate = clk_predict_rate_from_parent(c, parent);
old_rate = clk_get_rate_locked(c);
ret = c->ops->set_parent(c, parent);
if (ret)
goto out;
out:
spin_unlock_irqrestore(&c->spinlock, flags);
return ret;
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *c)
{
return c->parent;
}
EXPORT_SYMBOL(clk_get_parent);
int clk_set_rate_locked(struct clk *c, unsigned long rate)
{
long new_rate;
if (!c->ops || !c->ops->set_rate)
return -ENOSYS;
if (rate > c->max_rate)
rate = c->max_rate;
if (c->ops && c->ops->round_rate) {
new_rate = c->ops->round_rate(c, rate);
if (new_rate < 0)
return new_rate;
rate = new_rate;
}
return c->ops->set_rate(c, rate);
}
int clk_set_rate(struct clk *c, unsigned long rate)
{
int ret;
unsigned long flags;
spin_lock_irqsave(&c->spinlock, flags);
ret = clk_set_rate_locked(c, rate);
spin_unlock_irqrestore(&c->spinlock, flags);
return ret;
}
EXPORT_SYMBOL(clk_set_rate);
/* Must be called with clocks lock and all indvidual clock locks held */
unsigned long clk_get_rate_all_locked(struct clk *c)
{
u64 rate;
int mul = 1;
int div = 1;
struct clk *p = c;
while (p) {
c = p;
if (c->mul != 0 && c->div != 0) {
mul *= c->mul;
div *= c->div;
}
p = c->parent;
}
rate = c->rate;
rate *= mul;
do_div(rate, div);
return rate;
}
long clk_round_rate(struct clk *c, unsigned long rate)
{
unsigned long flags;
long ret;
spin_lock_irqsave(&c->spinlock, flags);
if (!c->ops || !c->ops->round_rate) {
ret = -ENOSYS;
goto out;
}
if (rate > c->max_rate)
rate = c->max_rate;
ret = c->ops->round_rate(c, rate);
out:
spin_unlock_irqrestore(&c->spinlock, flags);
return ret;
}
EXPORT_SYMBOL(clk_round_rate);
static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
{
struct clk *c;
struct clk *p;
struct clk *parent;
int ret = 0;
c = tegra_get_clock_by_name(table->name);
if (!c) {
pr_warning("Unable to initialize clock %s\n",
pr_warn("Unable to initialize clock %s\n",
table->name);
return -ENODEV;
}
parent = clk_get_parent(c);
if (table->parent) {
p = tegra_get_clock_by_name(table->parent);
if (!p) {
pr_warning("Unable to find parent %s of clock %s\n",
pr_warn("Unable to find parent %s of clock %s\n",
table->parent, table->name);
return -ENODEV;
}
if (c->parent != p) {
if (parent != p) {
ret = clk_set_parent(c, p);
if (ret) {
pr_warning("Unable to set parent %s of clock %s: %d\n",
pr_warn("Unable to set parent %s of clock %s: %d\n",
table->parent, table->name, ret);
return -EINVAL;
}
@ -360,16 +105,16 @@ static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
if (table->rate && table->rate != clk_get_rate(c)) {
ret = clk_set_rate(c, table->rate);
if (ret) {
pr_warning("Unable to set clock %s to rate %lu: %d\n",
pr_warn("Unable to set clock %s to rate %lu: %d\n",
table->name, table->rate, ret);
return -EINVAL;
}
}
if (table->enabled) {
ret = clk_enable(c);
ret = clk_prepare_enable(c);
if (ret) {
pr_warning("Unable to enable clock %s: %d\n",
pr_warn("Unable to enable clock %s: %d\n",
table->name, ret);
return -EINVAL;
}
@ -383,19 +128,20 @@ void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
for (; table->name; table++)
tegra_clk_init_one_from_table(table);
}
EXPORT_SYMBOL(tegra_clk_init_from_table);
void tegra_periph_reset_deassert(struct clk *c)
{
BUG_ON(!c->ops->reset);
c->ops->reset(c, false);
struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
BUG_ON(!clk->reset);
clk->reset(__clk_get_hw(c), false);
}
EXPORT_SYMBOL(tegra_periph_reset_deassert);
void tegra_periph_reset_assert(struct clk *c)
{
BUG_ON(!c->ops->reset);
c->ops->reset(c, true);
struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
BUG_ON(!clk->reset);
clk->reset(__clk_get_hw(c), true);
}
EXPORT_SYMBOL(tegra_periph_reset_assert);
@ -405,268 +151,14 @@ EXPORT_SYMBOL(tegra_periph_reset_assert);
int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
{
int ret = 0;
unsigned long flags;
struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
spin_lock_irqsave(&c->spinlock, flags);
if (!c->ops || !c->ops->clk_cfg_ex) {
if (!clk->clk_cfg_ex) {
ret = -ENOSYS;
goto out;
}
ret = c->ops->clk_cfg_ex(c, p, setting);
ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
out:
spin_unlock_irqrestore(&c->spinlock, flags);
return ret;
}
#ifdef CONFIG_DEBUG_FS
static int __clk_lock_all_spinlocks(void)
{
struct clk *c;
list_for_each_entry(c, &clocks, node)
if (!spin_trylock(&c->spinlock))
goto unlock_spinlocks;
return 0;
unlock_spinlocks:
list_for_each_entry_continue_reverse(c, &clocks, node)
spin_unlock(&c->spinlock);
return -EAGAIN;
}
static void __clk_unlock_all_spinlocks(void)
{
struct clk *c;
list_for_each_entry_reverse(c, &clocks, node)
spin_unlock(&c->spinlock);
}
/*
* This function retries until it can take all locks, and may take
* an arbitrarily long time to complete.
* Must be called with irqs enabled, returns with irqs disabled
* Must be called with clock_list_lock held
*/
static void clk_lock_all(void)
{
int ret;
retry:
local_irq_disable();
ret = __clk_lock_all_spinlocks();
if (ret)
goto failed_spinlocks;
/* All locks taken successfully, return */
return;
failed_spinlocks:
local_irq_enable();
yield();
goto retry;
}
/*
* Unlocks all clocks after a clk_lock_all
* Must be called with irqs disabled, returns with irqs enabled
* Must be called with clock_list_lock held
*/
static void clk_unlock_all(void)
{
__clk_unlock_all_spinlocks();
local_irq_enable();
}
static struct dentry *clk_debugfs_root;
static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
{
struct clk *child;
const char *state = "uninit";
char div[8] = {0};
if (c->state == ON)
state = "on";
else if (c->state == OFF)
state = "off";
if (c->mul != 0 && c->div != 0) {
if (c->mul > c->div) {
int mul = c->mul / c->div;
int mul2 = (c->mul * 10 / c->div) % 10;
int mul3 = (c->mul * 10) % c->div;
if (mul2 == 0 && mul3 == 0)
snprintf(div, sizeof(div), "x%d", mul);
else if (mul3 == 0)
snprintf(div, sizeof(div), "x%d.%d", mul, mul2);
else
snprintf(div, sizeof(div), "x%d.%d..", mul, mul2);
} else {
snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
(c->div % c->mul) ? ".5" : "");
}
}
seq_printf(s, "%*s%c%c%-*s %-6s %-3d %-8s %-10lu\n",
level * 3 + 1, "",
c->rate > c->max_rate ? '!' : ' ',
!c->set ? '*' : ' ',
30 - level * 3, c->name,
state, c->refcnt, div, clk_get_rate_all_locked(c));
list_for_each_entry(child, &clocks, node) {
if (child->parent != c)
continue;
clock_tree_show_one(s, child, level + 1);
}
}
static int clock_tree_show(struct seq_file *s, void *data)
{
struct clk *c;
seq_printf(s, " clock state ref div rate\n");
seq_printf(s, "--------------------------------------------------------------\n");
mutex_lock(&clock_list_lock);
clk_lock_all();
list_for_each_entry(c, &clocks, node)
if (c->parent == NULL)
clock_tree_show_one(s, c, 0);
clk_unlock_all();
mutex_unlock(&clock_list_lock);
return 0;
}
static int clock_tree_open(struct inode *inode, struct file *file)
{
return single_open(file, clock_tree_show, inode->i_private);
}
static const struct file_operations clock_tree_fops = {
.open = clock_tree_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int possible_parents_show(struct seq_file *s, void *data)
{
struct clk *c = s->private;
int i;
for (i = 0; c->inputs[i].input; i++) {
char *first = (i == 0) ? "" : " ";
seq_printf(s, "%s%s", first, c->inputs[i].input->name);
}
seq_printf(s, "\n");
return 0;
}
static int possible_parents_open(struct inode *inode, struct file *file)
{
return single_open(file, possible_parents_show, inode->i_private);
}
static const struct file_operations possible_parents_fops = {
.open = possible_parents_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int clk_debugfs_register_one(struct clk *c)
{
struct dentry *d;
d = debugfs_create_dir(c->name, clk_debugfs_root);
if (!d)
return -ENOMEM;
c->dent = d;
d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
if (!d)
goto err_out;
d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
if (!d)
goto err_out;
d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
if (!d)
goto err_out;
if (c->inputs) {
d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
c, &possible_parents_fops);
if (!d)
goto err_out;
}
return 0;
err_out:
debugfs_remove_recursive(c->dent);
return -ENOMEM;
}
static int clk_debugfs_register(struct clk *c)
{
int err;
struct clk *pa = c->parent;
if (pa && !pa->dent) {
err = clk_debugfs_register(pa);
if (err)
return err;
}
if (!c->dent) {
err = clk_debugfs_register_one(c);
if (err)
return err;
}
return 0;
}
int __init tegra_clk_debugfs_init(void)
{
struct clk *c;
struct dentry *d;
int err = -ENOMEM;
d = debugfs_create_dir("clock", NULL);
if (!d)
return -ENOMEM;
clk_debugfs_root = d;
d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
&clock_tree_fops);
if (!d)
goto err_out;
list_for_each_entry(c, &clocks, node) {
err = clk_debugfs_register(c);
if (err)
goto err_out;
}
return 0;
err_out:
debugfs_remove_recursive(clk_debugfs_root);
return err;
}
#endif

40
arch/arm/mach-tegra/clock.h
View File

@ -2,6 +2,7 @@
* arch/arm/mach-tegra/include/mach/clock.h
*
* Copyright (C) 2010 Google, Inc.
* Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Colin Cross <ccross@google.com>
@ -20,9 +21,9 @@
#ifndef __MACH_TEGRA_CLOCK_H
#define __MACH_TEGRA_CLOCK_H
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <mach/clk.h>
@ -52,7 +53,8 @@
#define ENABLE_ON_INIT (1 << 28)
#define PERIPH_ON_APB (1 << 29)
struct clk;
struct clk_tegra;
#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
struct clk_mux_sel {
struct clk *input;
@ -68,47 +70,29 @@ struct clk_pll_freq_table {
u8 cpcon;
};
struct clk_ops {
void (*init)(struct clk *);
int (*enable)(struct clk *);
void (*disable)(struct clk *);
int (*set_parent)(struct clk *, struct clk *);
int (*set_rate)(struct clk *, unsigned long);
long (*round_rate)(struct clk *, unsigned long);
void (*reset)(struct clk *, bool);
int (*clk_cfg_ex)(struct clk *,
enum tegra_clk_ex_param, u32);
};
enum clk_state {
UNINITIALIZED = 0,
ON,
OFF,
};
struct clk {
struct clk_tegra {
/* node for master clocks list */
struct list_head node; /* node for list of all clocks */
struct list_head node; /* node for list of all clocks */
struct clk_lookup lookup;
struct clk_hw hw;
#ifdef CONFIG_DEBUG_FS
struct dentry *dent;
#endif
bool set;
struct clk_ops *ops;
unsigned long rate;
unsigned long fixed_rate;
unsigned long max_rate;
unsigned long min_rate;
u32 flags;
const char *name;
u32 refcnt;
enum clk_state state;
struct clk *parent;
u32 div;
u32 mul;
const struct clk_mux_sel *inputs;
u32 reg;
u32 reg_shift;
@ -144,7 +128,8 @@ struct clk {
} shared_bus_user;
} u;
spinlock_t spinlock;
void (*reset)(struct clk_hw *, bool);
int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
};
struct clk_duplicate {
@ -159,13 +144,10 @@ struct tegra_clk_init_table {
bool enabled;
};
void tegra_clk_add(struct clk *c);
void tegra2_init_clocks(void);
void tegra30_init_clocks(void);
void clk_init(struct clk *clk);
struct clk *tegra_get_clock_by_name(const char *name);
int clk_reparent(struct clk *c, struct clk *parent);
void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
unsigned long clk_get_rate_locked(struct clk *c);
int clk_set_rate_locked(struct clk *c, unsigned long rate);
#endif

1
arch/arm/mach-tegra/common.c
View File

@ -152,6 +152,5 @@ void __init tegra30_init_early(void)
void __init tegra_init_late(void)
{
tegra_clk_debugfs_init();
tegra_powergate_debugfs_init();
}

48
arch/arm/mach-tegra/cpu-tegra.c
View File

@ -49,6 +49,8 @@ static struct cpufreq_frequency_table freq_table[] = {
#define NUM_CPUS 2
static struct clk *cpu_clk;
static struct clk *pll_x_clk;
static struct clk *pll_p_clk;
static struct clk *emc_clk;
static unsigned long target_cpu_speed[NUM_CPUS];
@ -71,6 +73,42 @@ static unsigned int tegra_getspeed(unsigned int cpu)
return rate;
}
static int tegra_cpu_clk_set_rate(unsigned long rate)
{
int ret;
/*
* Take an extra reference to the main pll so it doesn't turn
* off when we move the cpu off of it
*/
clk_prepare_enable(pll_x_clk);
ret = clk_set_parent(cpu_clk, pll_p_clk);
if (ret) {
pr_err("Failed to switch cpu to clock pll_p\n");
goto out;
}
if (rate == clk_get_rate(pll_p_clk))
goto out;
ret = clk_set_rate(pll_x_clk, rate);
if (ret) {
pr_err("Failed to change pll_x to %lu\n", rate);
goto out;
}
ret = clk_set_parent(cpu_clk, pll_x_clk);
if (ret) {
pr_err("Failed to switch cpu to clock pll_x\n");
goto out;
}
out:
clk_disable_unprepare(pll_x_clk);
return ret;
}
static int tegra_update_cpu_speed(unsigned long rate)
{
int ret = 0;
@ -101,7 +139,7 @@ static int tegra_update_cpu_speed(unsigned long rate)
freqs.old, freqs.new);
#endif
ret = clk_set_rate(cpu_clk, freqs.new * 1000);
ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
if (ret) {
pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
freqs.new);
@ -183,6 +221,14 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
if (IS_ERR(cpu_clk))
return PTR_ERR(cpu_clk);
pll_x_clk = clk_get_sys(NULL, "pll_x");
if (IS_ERR(pll_x_clk))
return PTR_ERR(pll_x_clk);
pll_p_clk = clk_get_sys(NULL, "pll_p");
if (IS_ERR(pll_p_clk))
return PTR_ERR(pll_p_clk);
emc_clk = clk_get_sys("cpu", "emc");
if (IS_ERR(emc_clk)) {
clk_put(cpu_clk);

702
arch/arm/mach-tegra/devices.c
View File

@ -1,702 +0,0 @@
/*
* Copyright (C) 2010,2011 Google, Inc.
*
* Author:
* Colin Cross <ccross@android.com>
* Erik Gilling <ccross@android.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/resource.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/fsl_devices.h>
#include <linux/serial_8250.h>
#include <linux/i2c-tegra.h>
#include <asm/pmu.h>
#include <mach/irqs.h>
#include <mach/iomap.h>
#include <mach/dma.h>
#include <linux/usb/tegra_usb_phy.h>
#include "gpio-names.h"
#include "devices.h"
static struct resource gpio_resource[] = {
[0] = {
.start = TEGRA_GPIO_BASE,
.end = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_GPIO1,
.end = INT_GPIO1,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = INT_GPIO2,
.end = INT_GPIO2,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = INT_GPIO3,
.end = INT_GPIO3,
.flags = IORESOURCE_IRQ,
},
[4] = {
.start = INT_GPIO4,
.end = INT_GPIO4,
.flags = IORESOURCE_IRQ,
},
[5] = {
.start = INT_GPIO5,
.end = INT_GPIO5,
.flags = IORESOURCE_IRQ,
},
[6] = {
.start = INT_GPIO6,
.end = INT_GPIO6,
.flags = IORESOURCE_IRQ,
},
[7] = {
.start = INT_GPIO7,
.end = INT_GPIO7,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device tegra_gpio_device = {
.name = "tegra-gpio",
.id = -1,
.resource = gpio_resource,
.num_resources = ARRAY_SIZE(gpio_resource),
};
static struct resource pinmux_resource[] = {
[0] = {
/* Tri-state registers */
.start = TEGRA_APB_MISC_BASE + 0x14,
.end = TEGRA_APB_MISC_BASE + 0x20 + 3,
.flags = IORESOURCE_MEM,
},
[1] = {
/* Mux registers */
.start = TEGRA_APB_MISC_BASE + 0x80,
.end = TEGRA_APB_MISC_BASE + 0x9c + 3,
.flags = IORESOURCE_MEM,
},
[2] = {
/* Pull-up/down registers */
.start = TEGRA_APB_MISC_BASE + 0xa0,
.end = TEGRA_APB_MISC_BASE + 0xb0 + 3,
.flags = IORESOURCE_MEM,
},
[3] = {
/* Pad control registers */
.start = TEGRA_APB_MISC_BASE + 0x868,
.end = TEGRA_APB_MISC_BASE + 0x90c + 3,
.flags = IORESOURCE_MEM,
},
};
struct platform_device tegra_pinmux_device = {
.name = "tegra20-pinctrl",
.id = -1,
.resource = pinmux_resource,
.num_resources = ARRAY_SIZE(pinmux_resource),
};
static struct resource i2c_resource1[] = {
[0] = {
.start = INT_I2C,
.end = INT_I2C,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_I2C_BASE,
.end = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
static struct resource i2c_resource2[] = {
[0] = {
.start = INT_I2C2,
.end = INT_I2C2,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_I2C2_BASE,
.end = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
static struct resource i2c_resource3[] = {
[0] = {
.start = INT_I2C3,
.end = INT_I2C3,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_I2C3_BASE,
.end = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
static struct resource i2c_resource4[] = {
[0] = {
.start = INT_DVC,
.end = INT_DVC,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_DVC_BASE,
.end = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
.bus_clk_rate = 400000,
};
static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
.bus_clk_rate = 400000,
};
static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
.bus_clk_rate = 400000,
};
static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
.bus_clk_rate = 400000,
};
struct platform_device tegra_i2c_device1 = {
.name = "tegra-i2c",
.id = 0,
.resource = i2c_resource1,
.num_resources = ARRAY_SIZE(i2c_resource1),
.dev = {
.platform_data = &tegra_i2c1_platform_data,
},
};
struct platform_device tegra_i2c_device2 = {
.name = "tegra-i2c",
.id = 1,
.resource = i2c_resource2,
.num_resources = ARRAY_SIZE(i2c_resource2),
.dev = {
.platform_data = &tegra_i2c2_platform_data,
},
};
struct platform_device tegra_i2c_device3 = {
.name = "tegra-i2c",
.id = 2,
.resource = i2c_resource3,
.num_resources = ARRAY_SIZE(i2c_resource3),
.dev = {
.platform_data = &tegra_i2c3_platform_data,
},
};
struct platform_device tegra_i2c_device4 = {
.name = "tegra-i2c",
.id = 3,
.resource = i2c_resource4,
.num_resources = ARRAY_SIZE(i2c_resource4),
.dev = {
.platform_data = &tegra_dvc_platform_data,
},
};
static struct resource spi_resource1[] = {
[0] = {
.start = INT_S_LINK1,
.end = INT_S_LINK1,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_SPI1_BASE,
.end = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
static struct resource spi_resource2[] = {
[0] = {
.start = INT_SPI_2,
.end = INT_SPI_2,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_SPI2_BASE,
.end = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
static struct resource spi_resource3[] = {
[0] = {
.start = INT_SPI_3,
.end = INT_SPI_3,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_SPI3_BASE,
.end = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
static struct resource spi_resource4[] = {
[0] = {
.start = INT_SPI_4,
.end = INT_SPI_4,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_SPI4_BASE,
.end = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device tegra_spi_device1 = {
.name = "spi_tegra",
.id = 0,
.resource = spi_resource1,
.num_resources = ARRAY_SIZE(spi_resource1),
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
struct platform_device tegra_spi_device2 = {
.name = "spi_tegra",
.id = 1,
.resource = spi_resource2,
.num_resources = ARRAY_SIZE(spi_resource2),
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
struct platform_device tegra_spi_device3 = {
.name = "spi_tegra",
.id = 2,
.resource = spi_resource3,
.num_resources = ARRAY_SIZE(spi_resource3),
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
struct platform_device tegra_spi_device4 = {
.name = "spi_tegra",
.id = 3,
.resource = spi_resource4,
.num_resources = ARRAY_SIZE(spi_resource4),
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
static struct resource sdhci_resource1[] = {
[0] = {
.start = INT_SDMMC1,
.end = INT_SDMMC1,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_SDMMC1_BASE,
.end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
static struct resource sdhci_resource2[] = {
[0] = {
.start = INT_SDMMC2,
.end = INT_SDMMC2,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_SDMMC2_BASE,
.end = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
static struct resource sdhci_resource3[] = {
[0] = {
.start = INT_SDMMC3,
.end = INT_SDMMC3,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_SDMMC3_BASE,
.end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
static struct resource sdhci_resource4[] = {
[0] = {
.start = INT_SDMMC4,
.end = INT_SDMMC4,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = TEGRA_SDMMC4_BASE,
.end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
.flags = IORESOURCE_MEM,
},
};
/* board files should fill in platform_data register the devices themselvs.
* See board-harmony.c for an example
*/
struct platform_device tegra_sdhci_device1 = {
.name = "sdhci-tegra",
.id = 0,
.resource = sdhci_resource1,
.num_resources = ARRAY_SIZE(sdhci_resource1),
};
struct platform_device tegra_sdhci_device2 = {
.name = "sdhci-tegra",
.id = 1,
.resource = sdhci_resource2,
.num_resources = ARRAY_SIZE(sdhci_resource2),
};
struct platform_device tegra_sdhci_device3 = {
.name = "sdhci-tegra",
.id = 2,
.resource = sdhci_resource3,
.num_resources = ARRAY_SIZE(sdhci_resource3),
};
struct platform_device tegra_sdhci_device4 = {
.name = "sdhci-tegra",
.id = 3,
.resource = sdhci_resource4,
.num_resources = ARRAY_SIZE(sdhci_resource4),
};
static struct resource tegra_usb1_resources[] = {
[0] = {
.start = TEGRA_USB_BASE,
.end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_USB,
.end = INT_USB,
.flags = IORESOURCE_IRQ,
},
};
static struct resource tegra_usb2_resources[] = {
[0] = {
.start = TEGRA_USB2_BASE,
.end = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_USB2,
.end = INT_USB2,
.flags = IORESOURCE_IRQ,
},
};
static struct resource tegra_usb3_resources[] = {
[0] = {
.start = TEGRA_USB3_BASE,
.end = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_USB3,
.end = INT_USB3,
.flags = IORESOURCE_IRQ,
},
};
struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
.reset_gpio = -1,
.clk = "cdev2",
};
struct tegra_ehci_platform_data tegra_ehci1_pdata = {
.operating_mode = TEGRA_USB_OTG,
.power_down_on_bus_suspend = 1,
.vbus_gpio = -1,
};
struct tegra_ehci_platform_data tegra_ehci2_pdata = {
.phy_config = &tegra_ehci2_ulpi_phy_config,
.operating_mode = TEGRA_USB_HOST,
.power_down_on_bus_suspend = 1,
.vbus_gpio = -1,
};
struct tegra_ehci_platform_data tegra_ehci3_pdata = {
.operating_mode = TEGRA_USB_HOST,
.power_down_on_bus_suspend = 1,
.vbus_gpio = -1,
};
static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
struct platform_device tegra_ehci1_device = {
.name = "tegra-ehci",
.id = 0,
.dev = {
.dma_mask = &tegra_ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &tegra_ehci1_pdata,
},
.resource = tegra_usb1_resources,
.num_resources = ARRAY_SIZE(tegra_usb1_resources),
};
struct platform_device tegra_ehci2_device = {
.name = "tegra-ehci",
.id = 1,
.dev = {
.dma_mask = &tegra_ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &tegra_ehci2_pdata,
},
.resource = tegra_usb2_resources,
.num_resources = ARRAY_SIZE(tegra_usb2_resources),
};
struct platform_device tegra_ehci3_device = {
.name = "tegra-ehci",
.id = 2,
.dev = {
.dma_mask = &tegra_ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &tegra_ehci3_pdata,
},
.resource = tegra_usb3_resources,
.num_resources = ARRAY_SIZE(tegra_usb3_resources),
};
static struct resource tegra_pmu_resources[] = {
[0] = {
.start = INT_CPU0_PMU_INTR,
.end = INT_CPU0_PMU_INTR,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = INT_CPU1_PMU_INTR,
.end = INT_CPU1_PMU_INTR,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device tegra_pmu_device = {
.name = "arm-pmu",
.id = ARM_PMU_DEVICE_CPU,
.num_resources = ARRAY_SIZE(tegra_pmu_resources),
.resource = tegra_pmu_resources,
};
static struct resource tegra_uarta_resources[] = {
[0] = {
.start = TEGRA_UARTA_BASE,
.end = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_UARTA,
.end = INT_UARTA,
.flags = IORESOURCE_IRQ,
},
};
static struct resource tegra_uartb_resources[] = {
[0] = {
.start = TEGRA_UARTB_BASE,
.end = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_UARTB,
.end = INT_UARTB,
.flags = IORESOURCE_IRQ,
},
};
static struct resource tegra_uartc_resources[] = {
[0] = {
.start = TEGRA_UARTC_BASE,
.end = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_UARTC,
.end = INT_UARTC,
.flags = IORESOURCE_IRQ,
},
};
static struct resource tegra_uartd_resources[] = {
[0] = {
.start = TEGRA_UARTD_BASE,
.end = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_UARTD,
.end = INT_UARTD,
.flags = IORESOURCE_IRQ,
},
};
static struct resource tegra_uarte_resources[] = {
[0] = {
.start = TEGRA_UARTE_BASE,
.end = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_UARTE,
.end = INT_UARTE,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device tegra_uarta_device = {
.name = "tegra_uart",
.id = 0,
.num_resources = ARRAY_SIZE(tegra_uarta_resources),
.resource = tegra_uarta_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
struct platform_device tegra_uartb_device = {
.name = "tegra_uart",
.id = 1,
.num_resources = ARRAY_SIZE(tegra_uartb_resources),
.resource = tegra_uartb_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
struct platform_device tegra_uartc_device = {
.name = "tegra_uart",
.id = 2,
.num_resources = ARRAY_SIZE(tegra_uartc_resources),
.resource = tegra_uartc_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
struct platform_device tegra_uartd_device = {
.name = "tegra_uart",
.id = 3,
.num_resources = ARRAY_SIZE(tegra_uartd_resources),
.resource = tegra_uartd_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
struct platform_device tegra_uarte_device = {
.name = "tegra_uart",
.id = 4,
.num_resources = ARRAY_SIZE(tegra_uarte_resources),
.resource = tegra_uarte_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource i2s_resource1[] = {
[0] = {
.start = INT_I2S1,
.end = INT_I2S1,
.flags = IORESOURCE_IRQ
},
[1] = {
.start = TEGRA_DMA_REQ_SEL_I2S_1,
.end = TEGRA_DMA_REQ_SEL_I2S_1,
.flags = IORESOURCE_DMA
},
[2] = {
.start = TEGRA_I2S1_BASE,
.end = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
.flags = IORESOURCE_MEM
}
};
static struct resource i2s_resource2[] = {
[0] = {
.start = INT_I2S2,
.end = INT_I2S2,
.flags = IORESOURCE_IRQ
},
[1] = {
.start = TEGRA_DMA_REQ_SEL_I2S2_1,
.end = TEGRA_DMA_REQ_SEL_I2S2_1,
.flags = IORESOURCE_DMA
},
[2] = {
.start = TEGRA_I2S2_BASE,
.end = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
.flags = IORESOURCE_MEM
}
};
struct platform_device tegra_i2s_device1 = {
.name = "tegra20-i2s",
.id = 0,
.resource = i2s_resource1,
.num_resources = ARRAY_SIZE(i2s_resource1),
};
struct platform_device tegra_i2s_device2 = {
.name = "tegra20-i2s",
.id = 1,
.resource = i2s_resource2,
.num_resources = ARRAY_SIZE(i2s_resource2),
};
static struct resource tegra_das_resources[] = {
[0] = {
.start = TEGRA_APB_MISC_DAS_BASE,
.end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device tegra_das_device = {
.name = "tegra20-das",
.id = -1,
.num_resources = ARRAY_SIZE(tegra_das_resources),
.resource = tegra_das_resources,
};

60
arch/arm/mach-tegra/devices.h
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@ -1,60 +0,0 @@
/*
* Copyright (C) 2010,2011 Google, Inc.
*
* Author:
* Colin Cross <ccross@android.com>
* Erik Gilling <ccross@android.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_DEVICES_H
#define __MACH_TEGRA_DEVICES_H
#include <linux/platform_device.h>
#include <linux/platform_data/tegra_usb.h>
#include <linux/usb/tegra_usb_phy.h>
extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config;
extern struct tegra_ehci_platform_data tegra_ehci1_pdata;
extern struct tegra_ehci_platform_data tegra_ehci2_pdata;
extern struct tegra_ehci_platform_data tegra_ehci3_pdata;
extern struct platform_device tegra_gpio_device;
extern struct platform_device tegra_pinmux_device;
extern struct platform_device tegra_sdhci_device1;
extern struct platform_device tegra_sdhci_device2;
extern struct platform_device tegra_sdhci_device3;
extern struct platform_device tegra_sdhci_device4;
extern struct platform_device tegra_i2c_device1;
extern struct platform_device tegra_i2c_device2;
extern struct platform_device tegra_i2c_device3;
extern struct platform_device tegra_i2c_device4;
extern struct platform_device tegra_spi_device1;
extern struct platform_device tegra_spi_device2;
extern struct platform_device tegra_spi_device3;
extern struct platform_device tegra_spi_device4;
extern struct platform_device tegra_ehci1_device;
extern struct platform_device tegra_ehci2_device;
extern struct platform_device tegra_ehci3_device;
extern struct platform_device tegra_uarta_device;
extern struct platform_device tegra_uartb_device;
extern struct platform_device tegra_uartc_device;
extern struct platform_device tegra_uartd_device;
extern struct platform_device tegra_uarte_device;
extern struct platform_device tegra_pmu_device;
extern struct platform_device tegra_i2s_device1;
extern struct platform_device tegra_i2s_device2;
extern struct platform_device tegra_das_device;
#endif

1
arch/arm/mach-tegra/dma.c
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@ -31,7 +31,6 @@
#include <mach/dma.h>
#include <mach/irqs.h>
#include <mach/iomap.h>
#include <mach/suspend.h>
#include "apbio.h"

4
arch/arm/mach-tegra/fuse.c
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@ -93,9 +93,9 @@ void tegra_init_fuse(void)
{
u32 id;
u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
reg |= 1 << 28;
writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
reg = tegra_fuse_readl(FUSE_SKU_INFO);
tegra_sku_id = reg & 0xFF;

3
arch/arm/mach-tegra/include/mach/clk.h
View File

@ -34,7 +34,10 @@ enum tegra_clk_ex_param {
void tegra_periph_reset_deassert(struct clk *c);
void tegra_periph_reset_assert(struct clk *c);
#ifndef CONFIG_COMMON_CLK
unsigned long clk_get_rate_all_locked(struct clk *c);
#endif
void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);

28
arch/arm/mach-tegra/include/mach/gpio-tegra.h
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@ -1,28 +0,0 @@
/*
* arch/arm/mach-tegra/include/mach/gpio.h
*
* Copyright (C) 2010 Google, Inc.
*
* Author:
* Erik Gilling <konkers@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_GPIO_TEGRA_H
#define __MACH_TEGRA_GPIO_TEGRA_H
#include <linux/types.h>
#include <mach/irqs.h>
#define TEGRA_NR_GPIOS INT_GPIO_NR
#endif

63
arch/arm/mach-tegra/include/mach/pinconf-tegra.h
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@ -1,63 +0,0 @@
/*
* pinctrl configuration definitions for the NVIDIA Tegra pinmux
*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __PINCONF_TEGRA_H__
#define __PINCONF_TEGRA_H__
enum tegra_pinconf_param {
/* argument: tegra_pinconf_pull */
TEGRA_PINCONF_PARAM_PULL,
/* argument: tegra_pinconf_tristate */
TEGRA_PINCONF_PARAM_TRISTATE,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_ENABLE_INPUT,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_OPEN_DRAIN,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_LOCK,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_IORESET,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_SCHMITT,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
/* argument: Integer, range is HW-dependant */
TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
/* argument: Integer, range is HW-dependant */
TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
/* argument: Integer, range is HW-dependant */
TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
/* argument: Integer, range is HW-dependant */
TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
};
enum tegra_pinconf_pull {
TEGRA_PINCONFIG_PULL_NONE,
TEGRA_PINCONFIG_PULL_DOWN,
TEGRA_PINCONFIG_PULL_UP,
};
enum tegra_pinconf_tristate {
TEGRA_PINCONFIG_DRIVEN,
TEGRA_PINCONFIG_TRISTATE,
};
#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
#endif

38
arch/arm/mach-tegra/include/mach/suspend.h
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@ -1,38 +0,0 @@
/*
* arch/arm/mach-tegra/include/mach/suspend.h
*
* Copyright (C) 2010 Google, Inc.
*
* Author:
* Colin Cross <ccross@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _MACH_TEGRA_SUSPEND_H_
#define _MACH_TEGRA_SUSPEND_H_
void tegra_pinmux_suspend(void);
void tegra_irq_suspend(void);
void tegra_gpio_suspend(void);
void tegra_clk_suspend(void);
void tegra_dma_suspend(void);
void tegra_timer_suspend(void);
void tegra_pinmux_resume(void);
void tegra_irq_resume(void);
void tegra_gpio_resume(void);
void tegra_clk_resume(void);
void tegra_dma_resume(void);
void tegra_timer_resume(void);
#endif /* _MACH_TEGRA_SUSPEND_H_ */

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arch/arm/mach-tegra/tegra20_clocks.c Normal file
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42
arch/arm/mach-tegra/tegra20_clocks.h Normal file
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@ -0,0 +1,42 @@
/*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __MACH_TEGRA20_CLOCK_H
#define __MACH_TEGRA20_CLOCK_H
extern struct clk_ops tegra_clk_32k_ops;
extern struct clk_ops tegra_pll_ops;
extern struct clk_ops tegra_clk_m_ops;
extern struct clk_ops tegra_pll_div_ops;
extern struct clk_ops tegra_pllx_ops;
extern struct clk_ops tegra_plle_ops;
extern struct clk_ops tegra_clk_double_ops;
extern struct clk_ops tegra_cdev_clk_ops;
extern struct clk_ops tegra_audio_sync_clk_ops;
extern struct clk_ops tegra_super_ops;
extern struct clk_ops tegra_cpu_ops;
extern struct clk_ops tegra_twd_ops;
extern struct clk_ops tegra_cop_ops;
extern struct clk_ops tegra_bus_ops;
extern struct clk_ops tegra_blink_clk_ops;
extern struct clk_ops tegra_emc_clk_ops;
extern struct clk_ops tegra_periph_clk_ops;
extern struct clk_ops tegra_clk_shared_bus_ops;
void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
#endif

1141
arch/arm/mach-tegra/tegra20_clocks_data.c Normal file
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2484
arch/arm/mach-tegra/tegra2_clocks.c
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2559
arch/arm/mach-tegra/tegra30_clocks.c
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53
arch/arm/mach-tegra/tegra30_clocks.h Normal file
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@ -0,0 +1,53 @@
/*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __MACH_TEGRA30_CLOCK_H
#define __MACH_TEGRA30_CLOCK_H
extern struct clk_ops tegra30_clk_32k_ops;
extern struct clk_ops tegra30_clk_m_ops;
extern struct clk_ops tegra_clk_m_div_ops;
extern struct clk_ops tegra_pll_ref_ops;
extern struct clk_ops tegra30_pll_ops;
extern struct clk_ops tegra30_pll_div_ops;
extern struct clk_ops tegra_plld_ops;
extern struct clk_ops tegra30_plle_ops;
extern struct clk_ops tegra_cml_clk_ops;
extern struct clk_ops tegra_pciex_clk_ops;
extern struct clk_ops tegra_sync_source_ops;
extern struct clk_ops tegra30_audio_sync_clk_ops;
extern struct clk_ops tegra30_clk_double_ops;
extern struct clk_ops tegra_clk_out_ops;
extern struct clk_ops tegra30_super_ops;
extern struct clk_ops tegra30_blink_clk_ops;
extern struct clk_ops tegra30_twd_ops;
extern struct clk_ops tegra30_periph_clk_ops;
extern struct clk_ops tegra30_dsib_clk_ops;
extern struct clk_ops tegra_nand_clk_ops;
extern struct clk_ops tegra_vi_clk_ops;
extern struct clk_ops tegra_dtv_clk_ops;
extern struct clk_ops tegra_clk_shared_bus_ops;
int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
enum tegra_clk_ex_param p, u32 setting);
void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
enum tegra_clk_ex_param p, u32 setting);
int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
enum tegra_clk_ex_param p, u32 setting);
int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
enum tegra_clk_ex_param p, u32 setting);
#endif

1369
arch/arm/mach-tegra/tegra30_clocks_data.c Normal file
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File diff suppressed because it is too large Load Diff

1
arch/arm/mach-tegra/timer.c
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@ -33,7 +33,6 @@
#include <mach/iomap.h>
#include <mach/irqs.h>
#include <mach/suspend.h>
#include "board.h"
#include "clock.h"

3
drivers/gpio/gpio-tegra.c
View File

@ -30,9 +30,6 @@
#include <asm/mach/irq.h>
#include <mach/iomap.h>
#include <mach/suspend.h>
#define GPIO_BANK(x) ((x) >> 5)
#define GPIO_PORT(x) (((x) >> 3) & 0x3)
#define GPIO_BIT(x) ((x) & 0x7)

13
drivers/mfd/tps6586x.c
View File

@ -25,6 +25,7 @@
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/of_regulator.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tps6586x.h>
@ -346,6 +347,7 @@ failed:
#ifdef CONFIG_OF
static struct of_regulator_match tps6586x_matches[] = {
{ .name = "sys", .driver_data = (void *)TPS6586X_ID_SYS },
{ .name = "sm0", .driver_data = (void *)TPS6586X_ID_SM_0 },
{ .name = "sm1", .driver_data = (void *)TPS6586X_ID_SM_1 },
{ .name = "sm2", .driver_data = (void *)TPS6586X_ID_SM_2 },
@ -369,6 +371,7 @@ static struct tps6586x_platform_data *tps6586x_parse_dt(struct i2c_client *clien
struct tps6586x_platform_data *pdata;
struct tps6586x_subdev_info *devs;
struct device_node *regs;
const char *sys_rail_name = NULL;
unsigned int count;
unsigned int i, j;
int err;
@ -391,12 +394,22 @@ static struct tps6586x_platform_data *tps6586x_parse_dt(struct i2c_client *clien
return NULL;
for (i = 0, j = 0; i < num && j < count; i++) {
struct regulator_init_data *reg_idata;
if (!tps6586x_matches[i].init_data)
continue;
reg_idata = tps6586x_matches[i].init_data;
devs[j].name = "tps6586x-regulator";
devs[j].platform_data = tps6586x_matches[i].init_data;
devs[j].id = (int)tps6586x_matches[i].driver_data;
if (devs[j].id == TPS6586X_ID_SYS)
sys_rail_name = reg_idata->constraints.name;
if ((devs[j].id == TPS6586X_ID_LDO_5) ||
(devs[j].id == TPS6586X_ID_LDO_RTC))
reg_idata->supply_regulator = sys_rail_name;
devs[j].of_node = tps6586x_matches[i].of_node;
j++;
}

1
drivers/mmc/host/sdhci-tegra.c
View File

@ -27,7 +27,6 @@
#include <asm/gpio.h>
#include <mach/gpio-tegra.h>
#include <mach/sdhci.h>
#include "sdhci-pltfm.h"

2
drivers/pinctrl/pinctrl-tegra.c
View File

@ -30,8 +30,6 @@
#include <linux/pinctrl/pinconf.h>
#include <linux/slab.h>
#include <mach/pinconf-tegra.h>
#include "core.h"
#include "pinctrl-tegra.h"

44
drivers/pinctrl/pinctrl-tegra.h
View File

@ -16,6 +16,50 @@
#ifndef __PINMUX_TEGRA_H__
#define __PINMUX_TEGRA_H__
enum tegra_pinconf_param {
/* argument: tegra_pinconf_pull */
TEGRA_PINCONF_PARAM_PULL,
/* argument: tegra_pinconf_tristate */
TEGRA_PINCONF_PARAM_TRISTATE,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_ENABLE_INPUT,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_OPEN_DRAIN,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_LOCK,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_IORESET,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_SCHMITT,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
/* argument: Integer, range is HW-dependant */
TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
/* argument: Integer, range is HW-dependant */
TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
/* argument: Integer, range is HW-dependant */
TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
/* argument: Integer, range is HW-dependant */
TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
};
enum tegra_pinconf_pull {
TEGRA_PINCONFIG_PULL_NONE,
TEGRA_PINCONFIG_PULL_DOWN,
TEGRA_PINCONFIG_PULL_UP,
};
enum tegra_pinconf_tristate {
TEGRA_PINCONFIG_DRIVEN,
TEGRA_PINCONFIG_TRISTATE,
};
#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
/**
* struct tegra_function - Tegra pinctrl mux function
* @name: The name of the function, exported to pinctrl core.

20
drivers/regulator/tps6586x-regulator.c
View File

@ -162,6 +162,9 @@ static struct regulator_ops tps6586x_regulator_ops = {
.disable = tps6586x_regulator_disable,
};
static struct regulator_ops tps6586x_sys_regulator_ops = {
};
static const unsigned int tps6586x_ldo0_voltages[] = {
1200000, 1500000, 1800000, 2500000, 2700000, 2850000, 3100000, 3300000,
};
@ -230,15 +233,28 @@ static const unsigned int tps6586x_dvm_voltages[] = {
TPS6586X_REGULATOR_DVM_GOREG(goreg, gobit) \
}
#define TPS6586X_SYS_REGULATOR() \
{ \
.desc = { \
.supply_name = "sys", \
.name = "REG-SYS", \
.ops = &tps6586x_sys_regulator_ops, \
.type = REGULATOR_VOLTAGE, \
.id = TPS6586X_ID_SYS, \
.owner = THIS_MODULE, \
}, \
}
static struct tps6586x_regulator tps6586x_regulator[] = {
TPS6586X_SYS_REGULATOR(),
TPS6586X_LDO(LDO_0, "vinldo01", ldo0, SUPPLYV1, 5, 3, ENC, 0, END, 0),
TPS6586X_LDO(LDO_3, "vinldo23", ldo, SUPPLYV4, 0, 3, ENC, 2, END, 2),
TPS6586X_LDO(LDO_5, NULL, ldo, SUPPLYV6, 0, 3, ENE, 6, ENE, 6),
TPS6586X_LDO(LDO_5, "REG-SYS", ldo, SUPPLYV6, 0, 3, ENE, 6, ENE, 6),
TPS6586X_LDO(LDO_6, "vinldo678", ldo, SUPPLYV3, 0, 3, ENC, 4, END, 4),
TPS6586X_LDO(LDO_7, "vinldo678", ldo, SUPPLYV3, 3, 3, ENC, 5, END, 5),
TPS6586X_LDO(LDO_8, "vinldo678", ldo, SUPPLYV2, 5, 3, ENC, 6, END, 6),
TPS6586X_LDO(LDO_9, "vinldo9", ldo, SUPPLYV6, 3, 3, ENE, 7, ENE, 7),
TPS6586X_LDO(LDO_RTC, NULL, ldo, SUPPLYV4, 3, 3, V4, 7, V4, 7),
TPS6586X_LDO(LDO_RTC, "REG-SYS", ldo, SUPPLYV4, 3, 3, V4, 7, V4, 7),
TPS6586X_LDO(LDO_1, "vinldo01", dvm, SUPPLYV1, 0, 5, ENC, 1, END, 1),
TPS6586X_LDO(SM_2, "vin-sm2", sm2, SUPPLYV2, 0, 5, ENC, 7, END, 7),

1
drivers/usb/phy/tegra_usb_phy.c
View File

@ -28,7 +28,6 @@
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <asm/mach-types.h>
#include <mach/gpio-tegra.h>
#include <linux/usb/tegra_usb_phy.h>
#include <mach/iomap.h>

1
include/linux/mfd/tps6586x.h
View File

@ -14,6 +14,7 @@
#define TPS6586X_SLEW_RATE_MASK 0x07
enum {
TPS6586X_ID_SYS,
TPS6586X_ID_SM_0,
TPS6586X_ID_SM_1,
TPS6586X_ID_SM_2,