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pinctrl: renesas: r8a7790: Use shorthands for reserved fields
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 445 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/842d8060422a9b67dfac4af6d9325d0d99cf50dc.1649865241.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven
parent
5ca9a715f5
commit
9bfb06a378
@ -5122,10 +5122,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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GP_5_0_FN, FN_IP14_21_19 ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
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GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
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GROUP(-1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
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GROUP(
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/* IP0_31 [1] */
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0, 0,
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/* IP0_31 [1] RESERVED */
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/* IP0_30_27 [4] */
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FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
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FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
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@ -5159,10 +5158,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, 0, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
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GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
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GROUP(-2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
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GROUP(
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/* IP1_31_30 [2] */
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0, 0, 0, 0,
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/* IP1_31_30 [2] RESERVED */
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/* IP1_29_28 [2] */
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FN_A1, FN_PWM4, 0, 0,
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/* IP1_27_26 [2] */
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@ -5197,10 +5195,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, 0, 0, 0, 0, 0, 0, 0, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
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GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
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GROUP(-3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
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GROUP(
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/* IP2_31_29 [3] */
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0, 0, 0, 0, 0, 0, 0, 0,
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/* IP2_31_29 [3] RESERVED */
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/* IP2_28_26 [3] */
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FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
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FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
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@ -5261,10 +5258,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, 0, 0, 0, 0, 0, 0, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
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GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
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GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
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GROUP(
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/* IP4_31_30 [2] */
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0, 0, 0, 0,
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/* IP4_31_30 [2] RESERVED */
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/* IP4_29_27 [3] */
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FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
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FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
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@ -5295,10 +5291,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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))
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},
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{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
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GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
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GROUP(-2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
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GROUP(
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/* IP5_31_30 [2] */
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0, 0, 0, 0,
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/* IP5_31_30 [2] RESERVED */
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/* IP5_29_27 [3] */
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FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
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FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
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@ -5368,10 +5363,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
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GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
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GROUP(-1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
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GROUP(
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/* IP7_31 [1] */
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0, 0,
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/* IP7_31 [1] RESERVED */
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/* IP7_30_29 [2] */
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FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
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/* IP7_28_27 [2] */
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@ -5404,11 +5398,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
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GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
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GROUP(-1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2),
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GROUP(
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/* IP8_31 [1] */
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0, 0,
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/* IP8_31 [1] RESERVED */
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/* IP8_30_29 [2] */
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FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
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/* IP8_28 [1] */
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@ -5482,10 +5475,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
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GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
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GROUP(-2, 4, 3, 4, 4, 4, 4, 3, 4),
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GROUP(
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/* IP10_31_30 [2] */
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0, 0, 0, 0,
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/* IP10_31_30 [2] RESERVED */
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/* IP10_29_26 [4] */
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FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
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FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
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@ -5558,10 +5550,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
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GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
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GROUP(-1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
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GROUP(
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/* IP12_31 [1] */
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0, 0,
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/* IP12_31 [1] RESERVED */
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/* IP12_30_28 [3] */
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FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
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FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
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@ -5598,10 +5589,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
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GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
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GROUP(-1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
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GROUP(
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/* IP13_31 [1] */
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0, 0,
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/* IP13_31 [1] RESERVED */
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/* IP13_30_29 [2] */
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FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
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/* IP13_28_26 [3] */
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@ -5635,10 +5625,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
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GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
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GROUP(-1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
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GROUP(
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/* IP14_30 [1] */
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0, 0,
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/* IP14_30 [1] RESERVED */
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/* IP14_30_28 [3] */
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FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
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FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
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@ -5674,10 +5663,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_REMOCON, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
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GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
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GROUP(-2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
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GROUP(
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/* IP15_31_30 [2] */
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0, 0, 0, 0,
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/* IP15_31_30 [2] RESERVED */
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/* IP15_29_28 [2] */
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FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
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/* IP15_27_26 [2] */
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@ -5710,26 +5698,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
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GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
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GROUP(-24, 1, 1, 3, 3),
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GROUP(
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/* IP16_31_28 [4] */
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* IP16_27_24 [4] */
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* IP16_23_20 [4] */
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* IP16_19_16 [4] */
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* IP16_15_12 [4] */
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* IP16_11_8 [4] */
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* IP16_31_8 [24] RESERVED */
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/* IP16_7 [1] */
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FN_USB1_OVC, FN_TCLK1_B,
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/* IP16_6 [1] */
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@ -5743,7 +5714,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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},
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{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
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GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
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1, 1, 1, 2, 1, 1, 2, 1, 1),
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1, 1, 1, 2, -1, 1, 2, 1, 1),
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GROUP(
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/* SEL_SCIF1 [3] */
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FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
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@ -5782,7 +5753,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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/* SEL_TSIF1 [2] */
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FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
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/* RESERVED [1] */
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0, 0,
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/* SEL_LBS [1] */
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FN_SEL_LBS_0, FN_SEL_LBS_1,
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/* SEL_TSIF0 [2] */
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@ -5793,11 +5763,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
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},
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{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
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GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
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3, 3, 2, 3, 2, 2),
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GROUP(-3, 1, 1, 1, 2, 1, 2, 1, -2, 1, 1, 1,
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3, 3, 2, -3, 2, 2),
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GROUP(
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/* RESERVED [3] */
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0, 0, 0, 0, 0, 0, 0, 0,
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/* SEL_TMU1 [1] */
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FN_SEL_TMU1_0, FN_SEL_TMU1_1,
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/* SEL_HSCIF1 [1] */
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@ -5813,7 +5782,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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/* SEL_CAN1 [1] */
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FN_SEL_CAN1_0, FN_SEL_CAN1_1,
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/* RESERVED [2] */
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0, 0, 0, 0,
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/* SEL_SCIF2 [1] */
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FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
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/* SEL_ADI [1] */
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@ -5829,36 +5797,22 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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/* SEL_GPS [2] */
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FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
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/* RESERVED [3] */
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0, 0, 0, 0, 0, 0, 0, 0,
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/* SEL_SIM [2] */
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FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
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/* SEL_SSI8 [2] */
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FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
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},
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{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
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GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
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GROUP(1, 1, -12, 2, -6, 3, 2, 3, 2),
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GROUP(
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/* SEL_IICDVFS [1] */
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FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
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/* SEL_IIC0 [1] */
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FN_SEL_IIC0_0, FN_SEL_IIC0_1,
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/* RESERVED [2] */
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0, 0, 0, 0,
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/* RESERVED [4] */
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* RESERVED [4] */
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* RESERVED [2] */
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0, 0, 0, 0,
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/* RESERVED [12] */
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/* SEL_IEB [2] */
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FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
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/* RESERVED [4] */
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* RESERVED [2] */
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0, 0, 0, 0,
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/* RESERVED [6] */
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/* SEL_IIC2 [3] */
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FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
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FN_SEL_IIC2_4, 0, 0, 0,
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