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clk: renesas: Updates for v4.10 (take three)
- CSI2 and VIN clocks for R-Car M3-W, - Clock drivers for new RZ/G1M and RZ/G1E SoCs, - Minor bug fix for R-Car H3. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYLCQPAAoJEEgEtLw/Ve77198P/ReauPCFhaRbvPi6y0BL3zBU 5qLwn8CjQMeylXDkI/XBKS/baHR7rWlT6RVoae6n0IVge/p8/BsgdH7lKlZyhntQ Y5h25zpDCXRWjvY2jqEmWQIkvSyAs34r7/EDCnvT3Q/1DbCgwd/jBhszPfTLpOWj hi2/Pzsv4muMKzsSIPm1al+0xBxRxlwfgKLW3NcV/3Xd94cI+Zl11vMHXgaUKtOc ip6Y5F5elnBxH9pMaUCEmeMB682XUSWVbT5l8zVHG+5w0qLecjdXQ7vcPjbbm71B 7EO6y5wAAuerJjniLjx6zkWnK3LkrXtw5wsNAPYpK5XPIt7nZPkM3X7lr1ijVghQ 2CZSGdN7qphpcp566RLtEgG403Xz+Ar2VM6OdpaSxxEBb0AQb+jPD8lrubuh0zH0 q8n52rkxFguAVao0C+L/2ItoUCZufBq1AIFyC9i2v0WeH8/BdZh5jWFXj5hLAFaB M40z0k5JK2BnU9PvupavZFVUf9iM5K1wF52lDVliXUK4g0g4FDzr64T+LR1CMVL9 fEAb2N08SKUlJu4faRpdlFwkSqq2dFFWb3+Z6515mUD3wQvPVn/+uQcPFcb4jDmc aePN1XNFGR0cUKgTQvTt/bVngrtGAeCpnk4qVMUpSvdEmR0UthvNjnYywzvJw2qO YE+Cqz8+TIoPpPN8LoT8 =ynxf -----END PGP SIGNATURE----- Merge tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull more clk driver updates from Geert Uytterhoeven: - CSI2 and VIN clocks for R-Car M3-W, - Clock drivers for new RZ/G1M and RZ/G1E SoCs, - Minor bug fix for R-Car H3. * tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Add R8A7745 support clk: renesas: cpg-mssr: Add R8A7743 support clk: renesas: cpg-mssr: Add common R-Car Gen2 support clk: renesas: r8a7795: Fix HDMI parent clock clk: renesas: r8a7796: Add VIN clocks clk: renesas: r8a7796: Add CSI2 clocks
This commit is contained in:
Stephen Boyd
commit
9baabf4341
@ -13,6 +13,8 @@ They provide the following functionalities:
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Required Properties:
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- compatible: Must be one of:
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- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
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- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
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- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
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- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
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@ -22,8 +24,9 @@ Required Properties:
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- clocks: References to external parent clocks, one entry for each entry in
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clock-names
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- clock-names: List of external parent clock names. Valid names are:
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- "extal" (r8a7795, r8a7796)
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- "extal" (r8a7743, r8a7745, r8a7795, r8a7796)
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- "extalr" (r8a7795, r8a7796)
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- "usb_extal" (r8a7743, r8a7745)
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- #clock-cells: Must be 2
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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@ -1,5 +1,7 @@
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config CLK_RENESAS_CPG_MSSR
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bool
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default y if ARCH_R8A7743
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default y if ARCH_R8A7745
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default y if ARCH_R8A7795
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default y if ARCH_R8A7796
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@ -2,6 +2,8 @@ obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
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obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
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obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7743) += r8a7743-cpg-mssr.o rcar-gen2-cpg.o
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obj-$(CONFIG_ARCH_R8A7745) += r8a7745-cpg-mssr.o rcar-gen2-cpg.o
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obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
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obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
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270
drivers/clk/renesas/r8a7743-cpg-mssr.c
Normal file
270
drivers/clk/renesas/r8a7743-cpg-mssr.c
Normal file
@ -0,0 +1,270 @@
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/*
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* r8a7743 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2016 Cogent Embedded Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation; of the License.
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*/
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/soc/renesas/rcar-rst.h>
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#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen2-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A7743_CLK_OSC,
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_USB_EXTAL,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL3,
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CLK_PLL1_DIV2,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("usb_extal", CLK_USB_EXTAL),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
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DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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/* Core Clock Outputs */
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DEF_BASE("z", R8A7743_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
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DEF_BASE("lb", R8A7743_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
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DEF_BASE("sdh", R8A7743_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
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DEF_BASE("sd0", R8A7743_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
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DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
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DEF_BASE("rcan", R8A7743_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
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DEF_FIXED("zg", R8A7743_CLK_ZG, CLK_PLL1, 3, 1),
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DEF_FIXED("zx", R8A7743_CLK_ZX, CLK_PLL1, 3, 1),
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DEF_FIXED("zs", R8A7743_CLK_ZS, CLK_PLL1, 6, 1),
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DEF_FIXED("hp", R8A7743_CLK_HP, CLK_PLL1, 12, 1),
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DEF_FIXED("b", R8A7743_CLK_B, CLK_PLL1, 12, 1),
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DEF_FIXED("p", R8A7743_CLK_P, CLK_PLL1, 24, 1),
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DEF_FIXED("cl", R8A7743_CLK_CL, CLK_PLL1, 48, 1),
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DEF_FIXED("m2", R8A7743_CLK_M2, CLK_PLL1, 8, 1),
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DEF_FIXED("zb3", R8A7743_CLK_ZB3, CLK_PLL3, 4, 1),
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DEF_FIXED("zb3d2", R8A7743_CLK_ZB3D2, CLK_PLL3, 8, 1),
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DEF_FIXED("ddr", R8A7743_CLK_DDR, CLK_PLL3, 8, 1),
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DEF_FIXED("mp", R8A7743_CLK_MP, CLK_PLL1_DIV2, 15, 1),
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DEF_FIXED("cp", R8A7743_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("r", R8A7743_CLK_R, CLK_PLL1, 49152, 1),
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DEF_FIXED("osc", R8A7743_CLK_OSC, CLK_PLL1, 12288, 1),
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DEF_DIV6P1("sd2", R8A7743_CLK_SD2, CLK_PLL1_DIV2, 0x078),
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DEF_DIV6P1("sd3", R8A7743_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
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DEF_DIV6P1("mmc0", R8A7743_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
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};
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static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {
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DEF_MOD("msiof0", 0, R8A7743_CLK_MP),
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DEF_MOD("vcp0", 101, R8A7743_CLK_ZS),
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DEF_MOD("vpc0", 103, R8A7743_CLK_ZS),
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DEF_MOD("tmu1", 111, R8A7743_CLK_P),
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DEF_MOD("3dg", 112, R8A7743_CLK_ZG),
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DEF_MOD("2d-dmac", 115, R8A7743_CLK_ZS),
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DEF_MOD("fdp1-1", 118, R8A7743_CLK_ZS),
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DEF_MOD("fdp1-0", 119, R8A7743_CLK_ZS),
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DEF_MOD("tmu3", 121, R8A7743_CLK_P),
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DEF_MOD("tmu2", 122, R8A7743_CLK_P),
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DEF_MOD("cmt0", 124, R8A7743_CLK_R),
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DEF_MOD("tmu0", 125, R8A7743_CLK_CP),
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DEF_MOD("vsp1du1", 127, R8A7743_CLK_ZS),
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DEF_MOD("vsp1du0", 128, R8A7743_CLK_ZS),
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DEF_MOD("vsp1-sy", 131, R8A7743_CLK_ZS),
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DEF_MOD("scifa2", 202, R8A7743_CLK_MP),
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DEF_MOD("scifa1", 203, R8A7743_CLK_MP),
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DEF_MOD("scifa0", 204, R8A7743_CLK_MP),
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DEF_MOD("msiof2", 205, R8A7743_CLK_MP),
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DEF_MOD("scifb0", 206, R8A7743_CLK_MP),
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DEF_MOD("scifb1", 207, R8A7743_CLK_MP),
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DEF_MOD("msiof1", 208, R8A7743_CLK_MP),
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DEF_MOD("scifb2", 216, R8A7743_CLK_MP),
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DEF_MOD("sys-dmac1", 218, R8A7743_CLK_ZS),
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DEF_MOD("sys-dmac0", 219, R8A7743_CLK_ZS),
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DEF_MOD("tpu0", 304, R8A7743_CLK_CP),
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DEF_MOD("sdhi3", 311, R8A7743_CLK_SD3),
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DEF_MOD("sdhi2", 312, R8A7743_CLK_SD2),
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DEF_MOD("sdhi0", 314, R8A7743_CLK_SD0),
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DEF_MOD("mmcif0", 315, R8A7743_CLK_MMC0),
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DEF_MOD("iic0", 318, R8A7743_CLK_HP),
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DEF_MOD("pciec", 319, R8A7743_CLK_MP),
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DEF_MOD("iic1", 323, R8A7743_CLK_HP),
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DEF_MOD("usb3.0", 328, R8A7743_CLK_MP),
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DEF_MOD("cmt1", 329, R8A7743_CLK_R),
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DEF_MOD("usbhs-dmac0", 330, R8A7743_CLK_HP),
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DEF_MOD("usbhs-dmac1", 331, R8A7743_CLK_HP),
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DEF_MOD("irqc", 407, R8A7743_CLK_CP),
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DEF_MOD("intc-sys", 408, R8A7743_CLK_ZS),
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DEF_MOD("audio-dmac1", 501, R8A7743_CLK_HP),
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DEF_MOD("audio-dmac0", 502, R8A7743_CLK_HP),
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DEF_MOD("thermal", 522, CLK_EXTAL),
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DEF_MOD("pwm", 523, R8A7743_CLK_P),
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DEF_MOD("usb-ehci", 703, R8A7743_CLK_MP),
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DEF_MOD("usbhs", 704, R8A7743_CLK_HP),
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DEF_MOD("hscif2", 713, R8A7743_CLK_ZS),
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DEF_MOD("scif5", 714, R8A7743_CLK_P),
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DEF_MOD("scif4", 715, R8A7743_CLK_P),
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DEF_MOD("hscif1", 716, R8A7743_CLK_ZS),
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DEF_MOD("hscif0", 717, R8A7743_CLK_ZS),
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DEF_MOD("scif3", 718, R8A7743_CLK_P),
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DEF_MOD("scif2", 719, R8A7743_CLK_P),
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DEF_MOD("scif1", 720, R8A7743_CLK_P),
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DEF_MOD("scif0", 721, R8A7743_CLK_P),
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DEF_MOD("du1", 723, R8A7743_CLK_ZX),
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DEF_MOD("du0", 724, R8A7743_CLK_ZX),
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DEF_MOD("lvds0", 726, R8A7743_CLK_ZX),
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DEF_MOD("ipmmu-sgx", 800, R8A7743_CLK_ZX),
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DEF_MOD("vin2", 809, R8A7743_CLK_ZG),
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DEF_MOD("vin1", 810, R8A7743_CLK_ZG),
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DEF_MOD("vin0", 811, R8A7743_CLK_ZG),
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DEF_MOD("etheravb", 812, R8A7743_CLK_HP),
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DEF_MOD("ether", 813, R8A7743_CLK_P),
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DEF_MOD("sata1", 814, R8A7743_CLK_ZS),
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DEF_MOD("sata0", 815, R8A7743_CLK_ZS),
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DEF_MOD("gpio7", 904, R8A7743_CLK_CP),
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DEF_MOD("gpio6", 905, R8A7743_CLK_CP),
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DEF_MOD("gpio5", 907, R8A7743_CLK_CP),
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DEF_MOD("gpio4", 908, R8A7743_CLK_CP),
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DEF_MOD("gpio3", 909, R8A7743_CLK_CP),
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DEF_MOD("gpio2", 910, R8A7743_CLK_CP),
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DEF_MOD("gpio1", 911, R8A7743_CLK_CP),
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DEF_MOD("gpio0", 912, R8A7743_CLK_CP),
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DEF_MOD("can1", 915, R8A7743_CLK_P),
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DEF_MOD("can0", 916, R8A7743_CLK_P),
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DEF_MOD("qspi_mod", 917, R8A7743_CLK_QSPI),
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DEF_MOD("i2c5", 925, R8A7743_CLK_HP),
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DEF_MOD("iicdvfs", 926, R8A7743_CLK_CP),
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DEF_MOD("i2c4", 927, R8A7743_CLK_HP),
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DEF_MOD("i2c3", 928, R8A7743_CLK_HP),
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DEF_MOD("i2c2", 929, R8A7743_CLK_HP),
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DEF_MOD("i2c1", 930, R8A7743_CLK_HP),
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DEF_MOD("i2c0", 931, R8A7743_CLK_HP),
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DEF_MOD("ssi-all", 1005, R8A7743_CLK_P),
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DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
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DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
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DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
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DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
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DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
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DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
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DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
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DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
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DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
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DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
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DEF_MOD("scu-all", 1017, R8A7743_CLK_P),
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DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
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DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
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DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
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DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
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DEF_MOD("scifa3", 1106, R8A7743_CLK_MP),
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DEF_MOD("scifa4", 1107, R8A7743_CLK_MP),
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DEF_MOD("scifa5", 1108, R8A7743_CLK_MP),
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};
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static const unsigned int r8a7743_crit_mod_clks[] __initconst = {
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MOD_CLK_ID(408), /* INTC-SYS (GIC) */
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};
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/*
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* CPG Clock Data
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*/
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/*
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* MD EXTAL PLL0 PLL1 PLL3
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* 14 13 19 (MHz) *1 *1
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*---------------------------------------------------
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* 0 0 0 15 x172/2 x208/2 x106
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* 0 0 1 15 x172/2 x208/2 x88
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* 0 1 0 20 x130/2 x156/2 x80
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* 0 1 1 20 x130/2 x156/2 x66
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* 1 0 0 26 / 2 x200/2 x240/2 x122
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* 1 0 1 26 / 2 x200/2 x240/2 x102
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* 1 1 0 30 / 2 x172/2 x208/2 x106
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* 1 1 1 30 / 2 x172/2 x208/2 x88
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*
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* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
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(((md) & BIT(13)) >> 12) | \
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(((md) & BIT(19)) >> 19))
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static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
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/* EXTAL div PLL1 mult PLL3 mult */
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{ 1, 208, 106, },
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{ 1, 208, 88, },
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{ 1, 156, 80, },
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{ 1, 156, 66, },
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{ 2, 240, 122, },
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{ 2, 240, 102, },
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{ 2, 208, 106, },
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{ 2, 208, 88, },
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};
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static int __init r8a7743_cpg_mssr_init(struct device *dev)
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{
|
||||
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
|
||||
return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a7743_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a7743_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a7743_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a7743_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a7743_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a7743_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a7743_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a7743_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen2_cpg_clk_register,
|
||||
};
|
||||
259
drivers/clk/renesas/r8a7745-cpg-mssr.c
Normal file
259
drivers/clk/renesas/r8a7745-cpg-mssr.c
Normal file
@ -0,0 +1,259 @@
|
||||
/*
|
||||
* r8a7745 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation; of the License.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7745-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7745_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_USB_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("lb", R8A7745_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7745_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7745_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
|
||||
|
||||
DEF_FIXED("z2", R8A7745_CLK_Z2, CLK_PLL0, 1, 1),
|
||||
DEF_FIXED("zg", R8A7745_CLK_ZG, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("zx", R8A7745_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("hp", R8A7745_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("b", R8A7745_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("p", R8A7745_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7745_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A7745_CLK_CP, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7745_CLK_M2, CLK_PLL1, 8, 1),
|
||||
DEF_FIXED("zb3", R8A7745_CLK_ZB3, CLK_PLL3, 4, 1),
|
||||
DEF_FIXED("zb3d2", R8A7745_CLK_ZB3D2, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("ddr", R8A7745_CLK_DDR, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("mp", R8A7745_CLK_MP, CLK_PLL1_DIV2, 15, 1),
|
||||
DEF_FIXED("cpex", R8A7745_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("r", R8A7745_CLK_R, CLK_PLL1, 49152, 1),
|
||||
DEF_FIXED("osc", R8A7745_CLK_OSC, CLK_PLL1, 12288, 1),
|
||||
|
||||
DEF_DIV6P1("sd2", R8A7745_CLK_SD2, CLK_PLL1_DIV2, 0x078),
|
||||
DEF_DIV6P1("sd3", R8A7745_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
|
||||
DEF_DIV6P1("mmc0", R8A7745_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
|
||||
DEF_MOD("msiof0", 0, R8A7745_CLK_MP),
|
||||
DEF_MOD("vcp0", 101, R8A7745_CLK_ZS),
|
||||
DEF_MOD("vpc0", 103, R8A7745_CLK_ZS),
|
||||
DEF_MOD("tmu1", 111, R8A7745_CLK_P),
|
||||
DEF_MOD("3dg", 112, R8A7745_CLK_ZG),
|
||||
DEF_MOD("2d-dmac", 115, R8A7745_CLK_ZS),
|
||||
DEF_MOD("fdp1-0", 119, R8A7745_CLK_ZS),
|
||||
DEF_MOD("tmu3", 121, R8A7745_CLK_P),
|
||||
DEF_MOD("tmu2", 122, R8A7745_CLK_P),
|
||||
DEF_MOD("cmt0", 124, R8A7745_CLK_R),
|
||||
DEF_MOD("tmu0", 125, R8A7745_CLK_CP),
|
||||
DEF_MOD("vsp1du0", 128, R8A7745_CLK_ZS),
|
||||
DEF_MOD("vsp1-sy", 131, R8A7745_CLK_ZS),
|
||||
DEF_MOD("scifa2", 202, R8A7745_CLK_MP),
|
||||
DEF_MOD("scifa1", 203, R8A7745_CLK_MP),
|
||||
DEF_MOD("scifa0", 204, R8A7745_CLK_MP),
|
||||
DEF_MOD("msiof2", 205, R8A7745_CLK_MP),
|
||||
DEF_MOD("scifb0", 206, R8A7745_CLK_MP),
|
||||
DEF_MOD("scifb1", 207, R8A7745_CLK_MP),
|
||||
DEF_MOD("msiof1", 208, R8A7745_CLK_MP),
|
||||
DEF_MOD("scifb2", 216, R8A7745_CLK_MP),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7745_CLK_ZS),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7745_CLK_ZS),
|
||||
DEF_MOD("tpu0", 304, R8A7745_CLK_CP),
|
||||
DEF_MOD("sdhi3", 311, R8A7745_CLK_SD3),
|
||||
DEF_MOD("sdhi2", 312, R8A7745_CLK_SD2),
|
||||
DEF_MOD("sdhi0", 314, R8A7745_CLK_SD0),
|
||||
DEF_MOD("mmcif0", 315, R8A7745_CLK_MMC0),
|
||||
DEF_MOD("iic0", 318, R8A7745_CLK_HP),
|
||||
DEF_MOD("iic1", 323, R8A7745_CLK_HP),
|
||||
DEF_MOD("cmt1", 329, R8A7745_CLK_R),
|
||||
DEF_MOD("usbhs-dmac0", 330, R8A7745_CLK_HP),
|
||||
DEF_MOD("usbhs-dmac1", 331, R8A7745_CLK_HP),
|
||||
DEF_MOD("irqc", 407, R8A7745_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7745_CLK_ZS),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7745_CLK_HP),
|
||||
DEF_MOD("pwm", 523, R8A7745_CLK_P),
|
||||
DEF_MOD("usb-ehci", 703, R8A7745_CLK_MP),
|
||||
DEF_MOD("usbhs", 704, R8A7745_CLK_HP),
|
||||
DEF_MOD("hscif2", 713, R8A7745_CLK_ZS),
|
||||
DEF_MOD("scif5", 714, R8A7745_CLK_P),
|
||||
DEF_MOD("scif4", 715, R8A7745_CLK_P),
|
||||
DEF_MOD("hscif1", 716, R8A7745_CLK_ZS),
|
||||
DEF_MOD("hscif0", 717, R8A7745_CLK_ZS),
|
||||
DEF_MOD("scif3", 718, R8A7745_CLK_P),
|
||||
DEF_MOD("scif2", 719, R8A7745_CLK_P),
|
||||
DEF_MOD("scif1", 720, R8A7745_CLK_P),
|
||||
DEF_MOD("scif0", 721, R8A7745_CLK_P),
|
||||
DEF_MOD("du0", 724, R8A7745_CLK_ZX),
|
||||
DEF_MOD("ipmmu-sgx", 800, R8A7745_CLK_ZX),
|
||||
DEF_MOD("vin1", 810, R8A7745_CLK_ZG),
|
||||
DEF_MOD("vin0", 811, R8A7745_CLK_ZG),
|
||||
DEF_MOD("etheravb", 812, R8A7745_CLK_HP),
|
||||
DEF_MOD("ether", 813, R8A7745_CLK_P),
|
||||
DEF_MOD("gpio6", 905, R8A7745_CLK_CP),
|
||||
DEF_MOD("gpio5", 907, R8A7745_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A7745_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A7745_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A7745_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A7745_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A7745_CLK_CP),
|
||||
DEF_MOD("can1", 915, R8A7745_CLK_P),
|
||||
DEF_MOD("can0", 916, R8A7745_CLK_P),
|
||||
DEF_MOD("qspi_mod", 917, R8A7745_CLK_QSPI),
|
||||
DEF_MOD("i2c5", 925, R8A7745_CLK_HP),
|
||||
DEF_MOD("i2c4", 927, R8A7745_CLK_HP),
|
||||
DEF_MOD("i2c3", 928, R8A7745_CLK_HP),
|
||||
DEF_MOD("i2c2", 929, R8A7745_CLK_HP),
|
||||
DEF_MOD("i2c1", 930, R8A7745_CLK_HP),
|
||||
DEF_MOD("i2c0", 931, R8A7745_CLK_HP),
|
||||
DEF_MOD("ssi-all", 1005, R8A7745_CLK_P),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7745_CLK_P),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scifa3", 1106, R8A7745_CLK_MP),
|
||||
DEF_MOD("scifa4", 1107, R8A7745_CLK_MP),
|
||||
DEF_MOD("scifa5", 1108, R8A7745_CLK_MP),
|
||||
};
|
||||
|
||||
static const unsigned int r8a7745_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *2
|
||||
*---------------------------------------------------
|
||||
* 0 0 0 15 x200/3 x208/2 x106
|
||||
* 0 0 1 15 x200/3 x208/2 x88
|
||||
* 0 1 0 20 x150/3 x156/2 x80
|
||||
* 0 1 1 20 x150/3 x156/2 x66
|
||||
* 1 0 0 26 / 2 x230/3 x240/2 x122
|
||||
* 1 0 1 26 / 2 x230/3 x240/2 x102
|
||||
* 1 1 0 30 / 2 x200/3 x208/2 x106
|
||||
* 1 1 1 30 / 2 x200/3 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
|
||||
* *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
|
||||
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
|
||||
/* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
|
||||
{ 1, 208, 106, 200 },
|
||||
{ 1, 208, 88, 200 },
|
||||
{ 1, 156, 80, 150 },
|
||||
{ 1, 156, 66, 150 },
|
||||
{ 2, 240, 122, 230 },
|
||||
{ 2, 240, 102, 230 },
|
||||
{ 2, 208, 106, 200 },
|
||||
{ 2, 208, 88, 200 },
|
||||
};
|
||||
|
||||
static int __init r8a7745_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
|
||||
return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a7745_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a7745_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a7745_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a7745_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a7745_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a7745_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a7745_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a7745_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen2_cpg_clk_register,
|
||||
};
|
||||
@ -98,7 +98,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
|
||||
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
|
||||
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
|
||||
|
||||
@ -103,6 +103,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
|
||||
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
@ -156,10 +158,20 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
|
||||
DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
|
||||
DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4),
|
||||
|
||||
371
drivers/clk/renesas/rcar-gen2-cpg.c
Normal file
371
drivers/clk/renesas/rcar-gen2-cpg.c
Normal file
@ -0,0 +1,371 @@
|
||||
/*
|
||||
* R-Car Gen2 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
#define CPG_FRQCRB 0x0004
|
||||
#define CPG_FRQCRB_KICK BIT(31)
|
||||
#define CPG_SDCKCR 0x0074
|
||||
#define CPG_PLL0CR 0x00d8
|
||||
#define CPG_PLL0CR_STC_SHIFT 24
|
||||
#define CPG_PLL0CR_STC_MASK (0x7f << CPG_PLL0CR_STC_SHIFT)
|
||||
#define CPG_FRQCRC 0x00e0
|
||||
#define CPG_FRQCRC_ZFC_SHIFT 8
|
||||
#define CPG_FRQCRC_ZFC_MASK (0x1f << CPG_FRQCRC_ZFC_SHIFT)
|
||||
#define CPG_ADSPCKCR 0x025c
|
||||
#define CPG_RCANCKCR 0x0270
|
||||
|
||||
static spinlock_t cpg_lock;
|
||||
|
||||
/*
|
||||
* Z Clock
|
||||
*
|
||||
* Traits of this clock:
|
||||
* prepare - clk_prepare only ensures that parents are prepared
|
||||
* enable - clk_enable only ensures that parents are enabled
|
||||
* rate - rate is adjustable. clk->rate = parent->rate * mult / 32
|
||||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
struct cpg_z_clk {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
void __iomem *kick_reg;
|
||||
};
|
||||
|
||||
#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
|
||||
|
||||
static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int mult;
|
||||
unsigned int val;
|
||||
|
||||
val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
|
||||
mult = 32 - val;
|
||||
|
||||
return div_u64((u64)parent_rate * mult, 32);
|
||||
}
|
||||
|
||||
static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
unsigned long prate = *parent_rate;
|
||||
unsigned int mult;
|
||||
|
||||
if (!prate)
|
||||
prate = 1;
|
||||
|
||||
mult = div_u64((u64)rate * 32, prate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
|
||||
return *parent_rate / 32 * mult;
|
||||
}
|
||||
|
||||
static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int mult;
|
||||
u32 val, kick;
|
||||
unsigned int i;
|
||||
|
||||
mult = div_u64((u64)rate * 32, parent_rate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
|
||||
if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
|
||||
return -EBUSY;
|
||||
|
||||
val = readl(zclk->reg);
|
||||
val &= ~CPG_FRQCRC_ZFC_MASK;
|
||||
val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
|
||||
writel(val, zclk->reg);
|
||||
|
||||
/*
|
||||
* Set KICK bit in FRQCRB to update hardware setting and wait for
|
||||
* clock change completion.
|
||||
*/
|
||||
kick = readl(zclk->kick_reg);
|
||||
kick |= CPG_FRQCRB_KICK;
|
||||
writel(kick, zclk->kick_reg);
|
||||
|
||||
/*
|
||||
* Note: There is no HW information about the worst case latency.
|
||||
*
|
||||
* Using experimental measurements, it seems that no more than
|
||||
* ~10 iterations are needed, independently of the CPU rate.
|
||||
* Since this value might be dependent on external xtal rate, pll1
|
||||
* rate or even the other emulation clocks rate, use 1000 as a
|
||||
* "super" safe value.
|
||||
*/
|
||||
for (i = 1000; i; i--) {
|
||||
if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
|
||||
return 0;
|
||||
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static const struct clk_ops cpg_z_clk_ops = {
|
||||
.recalc_rate = cpg_z_clk_recalc_rate,
|
||||
.round_rate = cpg_z_clk_round_rate,
|
||||
.set_rate = cpg_z_clk_set_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init cpg_z_clk_register(const char *name,
|
||||
const char *parent_name,
|
||||
void __iomem *base)
|
||||
{
|
||||
struct clk_init_data init;
|
||||
struct cpg_z_clk *zclk;
|
||||
struct clk *clk;
|
||||
|
||||
zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
|
||||
if (!zclk)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &cpg_z_clk_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
zclk->reg = base + CPG_FRQCRC;
|
||||
zclk->kick_reg = base + CPG_FRQCRB;
|
||||
zclk->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &zclk->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(zclk);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static struct clk * __init cpg_rcan_clk_register(const char *name,
|
||||
const char *parent_name,
|
||||
void __iomem *base)
|
||||
{
|
||||
struct clk_fixed_factor *fixed;
|
||||
struct clk_gate *gate;
|
||||
struct clk *clk;
|
||||
|
||||
fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
|
||||
if (!fixed)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
fixed->mult = 1;
|
||||
fixed->div = 6;
|
||||
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate) {
|
||||
kfree(fixed);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
gate->reg = base + CPG_RCANCKCR;
|
||||
gate->bit_idx = 8;
|
||||
gate->flags = CLK_GATE_SET_TO_DISABLE;
|
||||
gate->lock = &cpg_lock;
|
||||
|
||||
clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
|
||||
&fixed->hw, &clk_fixed_factor_ops,
|
||||
&gate->hw, &clk_gate_ops, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(gate);
|
||||
kfree(fixed);
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/* ADSP divisors */
|
||||
static const struct clk_div_table cpg_adsp_div_table[] = {
|
||||
{ 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
|
||||
{ 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
|
||||
{ 10, 36 }, { 11, 48 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk * __init cpg_adsp_clk_register(const char *name,
|
||||
const char *parent_name,
|
||||
void __iomem *base)
|
||||
{
|
||||
struct clk_divider *div;
|
||||
struct clk_gate *gate;
|
||||
struct clk *clk;
|
||||
|
||||
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
||||
if (!div)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
div->reg = base + CPG_ADSPCKCR;
|
||||
div->width = 4;
|
||||
div->table = cpg_adsp_div_table;
|
||||
div->lock = &cpg_lock;
|
||||
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate) {
|
||||
kfree(div);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
gate->reg = base + CPG_ADSPCKCR;
|
||||
gate->bit_idx = 8;
|
||||
gate->flags = CLK_GATE_SET_TO_DISABLE;
|
||||
gate->lock = &cpg_lock;
|
||||
|
||||
clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
|
||||
&div->hw, &clk_divider_ops,
|
||||
&gate->hw, &clk_gate_ops, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(gate);
|
||||
kfree(div);
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/* SDHI divisors */
|
||||
static const struct clk_div_table cpg_sdh_div_table[] = {
|
||||
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
|
||||
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
|
||||
{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table cpg_sd01_div_table[] = {
|
||||
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
|
||||
{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
|
||||
static unsigned int cpg_pll0_div __initdata;
|
||||
static u32 cpg_mode __initdata;
|
||||
|
||||
struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core,
|
||||
const struct cpg_mssr_info *info,
|
||||
struct clk **clks,
|
||||
void __iomem *base)
|
||||
{
|
||||
const struct clk_div_table *table = NULL;
|
||||
const struct clk *parent;
|
||||
const char *parent_name;
|
||||
unsigned int mult = 1;
|
||||
unsigned int div = 1;
|
||||
unsigned int shift;
|
||||
|
||||
parent = clks[core->parent];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
parent_name = __clk_get_name(parent);
|
||||
|
||||
switch (core->type) {
|
||||
/* R-Car Gen2 */
|
||||
case CLK_TYPE_GEN2_MAIN:
|
||||
div = cpg_pll_config->extal_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN2_PLL0:
|
||||
/*
|
||||
* PLL0 is a configurable multiplier clock except on R-Car
|
||||
* V2H/E2. Register the PLL0 clock as a fixed factor clock for
|
||||
* now as there's no generic multiplier clock implementation and
|
||||
* we currently have no need to change the multiplier value.
|
||||
*/
|
||||
mult = cpg_pll_config->pll0_mult;
|
||||
div = cpg_pll0_div;
|
||||
if (!mult) {
|
||||
u32 pll0cr = readl(base + CPG_PLL0CR);
|
||||
|
||||
mult = (((pll0cr & CPG_PLL0CR_STC_MASK) >>
|
||||
CPG_PLL0CR_STC_SHIFT) + 1) * 2;
|
||||
}
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN2_PLL1:
|
||||
mult = cpg_pll_config->pll1_mult / 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN2_PLL3:
|
||||
mult = cpg_pll_config->pll3_mult;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN2_Z:
|
||||
return cpg_z_clk_register(core->name, parent_name, base);
|
||||
|
||||
case CLK_TYPE_GEN2_LB:
|
||||
div = cpg_mode & BIT(18) ? 36 : 24;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN2_ADSP:
|
||||
return cpg_adsp_clk_register(core->name, parent_name, base);
|
||||
|
||||
case CLK_TYPE_GEN2_SDH:
|
||||
table = cpg_sdh_div_table;
|
||||
shift = 8;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN2_SD0:
|
||||
table = cpg_sd01_div_table;
|
||||
shift = 4;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN2_SD1:
|
||||
table = cpg_sd01_div_table;
|
||||
shift = 0;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN2_QSPI:
|
||||
div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ?
|
||||
8 : 10;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN2_RCAN:
|
||||
return cpg_rcan_clk_register(core->name, parent_name, base);
|
||||
|
||||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (!table)
|
||||
return clk_register_fixed_factor(NULL, core->name, parent_name,
|
||||
0, mult, div);
|
||||
else
|
||||
return clk_register_divider_table(NULL, core->name,
|
||||
parent_name, 0,
|
||||
base + CPG_SDCKCR, shift, 4,
|
||||
0, table, &cpg_lock);
|
||||
}
|
||||
|
||||
int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
|
||||
unsigned int pll0_div, u32 mode)
|
||||
{
|
||||
cpg_pll_config = config;
|
||||
cpg_pll0_div = pll0_div;
|
||||
cpg_mode = mode;
|
||||
|
||||
spin_lock_init(&cpg_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
43
drivers/clk/renesas/rcar-gen2-cpg.h
Normal file
43
drivers/clk/renesas/rcar-gen2-cpg.h
Normal file
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* R-Car Gen2 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
|
||||
#define __CLK_RENESAS_RCAR_GEN2_CPG_H__
|
||||
|
||||
enum rcar_gen2_clk_types {
|
||||
CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM,
|
||||
CLK_TYPE_GEN2_PLL0,
|
||||
CLK_TYPE_GEN2_PLL1,
|
||||
CLK_TYPE_GEN2_PLL3,
|
||||
CLK_TYPE_GEN2_Z,
|
||||
CLK_TYPE_GEN2_LB,
|
||||
CLK_TYPE_GEN2_ADSP,
|
||||
CLK_TYPE_GEN2_SDH,
|
||||
CLK_TYPE_GEN2_SD0,
|
||||
CLK_TYPE_GEN2_SD1,
|
||||
CLK_TYPE_GEN2_QSPI,
|
||||
CLK_TYPE_GEN2_RCAN,
|
||||
};
|
||||
|
||||
struct rcar_gen2_cpg_pll_config {
|
||||
unsigned int extal_div;
|
||||
unsigned int pll1_mult;
|
||||
unsigned int pll3_mult;
|
||||
unsigned int pll0_mult; /* leave as zero if PLL0CR exists */
|
||||
};
|
||||
|
||||
struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core,
|
||||
const struct cpg_mssr_info *info,
|
||||
struct clk **clks, void __iomem *base);
|
||||
int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
|
||||
unsigned int pll0_div, u32 mode);
|
||||
|
||||
#endif
|
||||
@ -502,6 +502,18 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
|
||||
}
|
||||
|
||||
static const struct of_device_id cpg_mssr_match[] = {
|
||||
#ifdef CONFIG_ARCH_R8A7743
|
||||
{
|
||||
.compatible = "renesas,r8a7743-cpg-mssr",
|
||||
.data = &r8a7743_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A7745
|
||||
{
|
||||
.compatible = "renesas,r8a7745-cpg-mssr",
|
||||
.data = &r8a7745_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A7795
|
||||
{
|
||||
.compatible = "renesas,r8a7795-cpg-mssr",
|
||||
|
||||
@ -130,6 +130,8 @@ struct cpg_mssr_info {
|
||||
struct clk **clks, void __iomem *base);
|
||||
};
|
||||
|
||||
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user