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drm/i915/dg2: Drop 38.4 MHz MPLLB tables
Our early understanding of DG2 was incorrect; since the 5th display isn't actually a Type-C output, 38.4 MHz input clocks are never used on this platform and we can drop the corresponding MPLLB tables. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220218010328.183423-2-lucas.demarchi@intel.com
This commit is contained in:
Matt Roper
Lucas De Marchi
parent
d1af7b6f91
commit
9b693453a4
@ -250,197 +250,6 @@ static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
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NULL,
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NULL,
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};
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};
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/*
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* Basic DP link rates with 38.4 MHz reference clock.
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*/
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static const struct intel_mpllb_state dg2_dp_rbr_38_4 = {
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.clock = 162000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
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.mpllb_fracn2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152),
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};
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static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = {
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.clock = 270000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
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.mpllb_fracn2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
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};
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static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = {
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.clock = 540000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
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.mpllb_fracn2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
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};
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static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
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.clock = 810000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
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.mpllb_fracn2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440),
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};
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static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = {
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.clock = 1000000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 488),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 3),
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.mpllb_fracn2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 27306),
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/*
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* SSC will be enabled, DP UHBR has a minimum SSC requirement.
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*/
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.mpllb_sscen =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 76800),
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.mpllb_sscstep =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 129024),
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};
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static const struct intel_mpllb_state dg2_dp_uhbr13_38_4 = {
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.clock = 1350000,
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.ref_control =
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REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
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.mpllb_cp =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 56) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
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.mpllb_div =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
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.mpllb_div2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 670),
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.mpllb_fracn1 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
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.mpllb_fracn2 =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36864),
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/*
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* SSC will be enabled, DP UHBR has a minimum SSC requirement.
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*/
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.mpllb_sscen =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 103680),
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.mpllb_sscstep =
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REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 174182),
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};
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static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = {
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&dg2_dp_rbr_38_4,
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&dg2_dp_hbr1_38_4,
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&dg2_dp_hbr2_38_4,
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&dg2_dp_hbr3_38_4,
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&dg2_dp_uhbr10_38_4,
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&dg2_dp_uhbr13_38_4,
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NULL,
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};
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/*
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/*
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* eDP link rates with 100 MHz reference clock.
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* eDP link rates with 100 MHz reference clock.
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*/
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*/
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@ -749,22 +558,7 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
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return dg2_edp_tables;
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return dg2_edp_tables;
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} else if (intel_crtc_has_dp_encoder(crtc_state)) {
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} else if (intel_crtc_has_dp_encoder(crtc_state)) {
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/*
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return dg2_dp_100_tables;
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* FIXME: Initially we're just enabling the "combo" outputs on
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* port A-D. The MPLLB for those ports takes an input from the
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* "Display Filter PLL" which always has an output frequency
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* of 100 MHz, hence the use of the _100 tables below.
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*
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* Once we enable port TC1 it will either use the same 100 MHz
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* "Display Filter PLL" (when strapped to support a native
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* display connection) or different 38.4 MHz "Filter PLL" when
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* strapped to support a USB connection, so we'll need to check
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* that to determine which table to use.
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*/
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if (0)
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return dg2_dp_38_4_tables;
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else
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return dg2_dp_100_tables;
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} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
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} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
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return dg2_hdmi_tables;
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return dg2_hdmi_tables;
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}
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}
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