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drm/i915: ironlake_write_eld code cleanup
Use _PIPE macro to get correct register definition for IBX/CPT, discard old variable "i" way. Signed-off-by: Wang Xingchao <xingchao.wang@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> [danvet: Added the DIP_PORT_SEL #define from a preceeding patch in the series that needs more work.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -4247,7 +4247,15 @@
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#define G4X_HDMIW_HDMIEDID 0x6210C
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#define IBX_HDMIW_HDMIEDID_A 0xE2050
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#define IBX_HDMIW_HDMIEDID_B 0xE2150
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#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
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IBX_HDMIW_HDMIEDID_A, \
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IBX_HDMIW_HDMIEDID_B)
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#define IBX_AUD_CNTL_ST_A 0xE20B4
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#define IBX_AUD_CNTL_ST_B 0xE21B4
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#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
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IBX_AUD_CNTL_ST_A, \
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IBX_AUD_CNTL_ST_B)
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#define IBX_ELD_BUFFER_SIZE (0x1f << 10)
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#define IBX_ELD_ADDRESS (0x1f << 5)
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#define IBX_ELD_ACK (1 << 4)
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@ -4256,7 +4264,15 @@
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#define IBX_CP_READYB (1 << 1)
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#define CPT_HDMIW_HDMIEDID_A 0xE5050
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#define CPT_HDMIW_HDMIEDID_B 0xE5150
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#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
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CPT_HDMIW_HDMIEDID_A, \
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CPT_HDMIW_HDMIEDID_B)
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#define CPT_AUD_CNTL_ST_A 0xE50B4
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#define CPT_AUD_CNTL_ST_B 0xE51B4
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#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
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CPT_AUD_CNTL_ST_A, \
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CPT_AUD_CNTL_ST_B)
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#define CPT_AUD_CNTRL_ST2 0xE50C0
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/* These are the 4 32-bit write offset registers for each stream
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@ -4266,7 +4282,15 @@
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#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
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#define IBX_AUD_CONFIG_A 0xe2000
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#define IBX_AUD_CONFIG_B 0xe2100
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#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
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IBX_AUD_CONFIG_A, \
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IBX_AUD_CONFIG_B)
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#define CPT_AUD_CONFIG_A 0xe5000
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#define CPT_AUD_CONFIG_B 0xe5100
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#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
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CPT_AUD_CONFIG_A, \
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CPT_AUD_CONFIG_B)
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#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
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#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
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#define AUD_CONFIG_UPPER_N_SHIFT 20
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@ -4302,6 +4326,7 @@
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#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
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HSW_AUD_DIG_CNVT_1, \
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HSW_AUD_DIG_CNVT_2)
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#define DIP_PORT_SEL_MASK 0x3
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#define HSW_AUD_EDID_DATA_A 0x65050
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#define HSW_AUD_EDID_DATA_B 0x65150
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@ -5078,28 +5078,24 @@ static void ironlake_write_eld(struct drm_connector *connector,
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int aud_config;
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int aud_cntl_st;
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int aud_cntrl_st2;
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int pipe = to_intel_crtc(crtc)->pipe;
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if (HAS_PCH_IBX(connector->dev)) {
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hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
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aud_config = IBX_AUD_CONFIG_A;
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aud_cntl_st = IBX_AUD_CNTL_ST_A;
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hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
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aud_config = IBX_AUD_CFG(pipe);
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aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
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aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
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} else {
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hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
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aud_config = CPT_AUD_CONFIG_A;
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aud_cntl_st = CPT_AUD_CNTL_ST_A;
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hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
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aud_config = CPT_AUD_CFG(pipe);
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aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
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aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
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}
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i = to_intel_crtc(crtc)->pipe;
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hdmiw_hdmiedid += i * 0x100;
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aud_cntl_st += i * 0x100;
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aud_config += i * 0x100;
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DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
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DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
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i = I915_READ(aud_cntl_st);
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i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
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i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
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if (!i) {
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DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
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/* operate blindly on all ports */
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