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perf vendor events intel: Fix uncore topics for skylake

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Move events from 'uncore-other' topic classification to cache and
interconnect.

Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230413132949.3487664-19-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2023-04-13 06:29:46 -07:00 committed by Arnaldo Carvalho de Melo
parent f58468a815
commit 9a8b303688
3 changed files with 81 additions and 79 deletions
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28
tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
View File

@ -6,7 +6,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"UMask": "0x86",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
@ -15,7 +15,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
"UMask": "0x88",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
@ -24,7 +24,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
"UMask": "0x81",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
@ -33,7 +33,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"UMask": "0x8f",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
@ -42,7 +42,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"UMask": "0x16",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
@ -51,7 +51,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
"UMask": "0x18",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
@ -60,7 +60,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"UMask": "0x1f",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
@ -69,7 +69,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"UMask": "0x26",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
@ -78,7 +78,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
"UMask": "0x21",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
@ -87,7 +87,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"UMask": "0x2f",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
@ -95,7 +95,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
"UMask": "0x48",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
@ -103,7 +103,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
"UMask": "0x44",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
@ -111,7 +111,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
"UMask": "0x81",
"Unit": "CBO"
"Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
@ -119,6 +119,6 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
"UMask": "0x41",
"Unit": "CBO"
"Unit": "CBOX"
}
]

67
tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json Normal file
View File

@ -0,0 +1,67 @@
[
{
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"CounterMask": "1",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "ARB"
}
]

65
tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
View File

@ -1,69 +1,4 @@
[
{
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"CounterMask": "1",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "ARB"
},
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
"EventCode": "0xff",