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Short summary of fixes pull:

Browse Source 
bridge:
 - tc358768: Fix DSI command tx
 
 nouveau:
 - Fix GSP AUX error handling
 - dp: Handle retires for AUX CH transfers with GSP
 - fw: Sync DMA after setup
 
 panthor:
 - Fix partial BO mappings to GPU
 
 rockchip:
 - vop: Avoid null-ptr deref in plane-state check
 
 vmwgfx:
 - Avoid null-ptr deref in surface creation
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Merge tag 'drm-misc-fixes-2024-11-14' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes

Short summary of fixes pull:

bridge:
- tc358768: Fix DSI command tx

nouveau:
- Fix GSP AUX error handling
- dp: Handle retires for AUX CH transfers with GSP
- fw: Sync DMA after setup

panthor:
- Fix partial BO mappings to GPU

rockchip:
- vop: Avoid null-ptr deref in plane-state check

vmwgfx:
- Avoid null-ptr deref in surface creation

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20241114142256.GA86810@2a02-2454-fd5e-fd00-4ce-489-4b34-bd1a.dyn6.pyur.net
This commit is contained in:
Dave Airlie 2024-11-15 06:38:32 +10:00
commit 99d051c4b3
7 changed files with 72 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/gpu/drm/bridge/tc358768.c
View File

@ -125,6 +125,9 @@
#define TC358768_DSI_CONFW_MODE_CLR (6 << 29)
#define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24)
/* TC358768_DSICMD_TX (0x0600) register */
#define TC358768_DSI_CMDTX_DC_START BIT(0)
static const char * const tc358768_supplies[] = {
"vddc", "vddmipi", "vddio"
};
@ -229,6 +232,21 @@ static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
tc358768_write(priv, reg, tmp);
}
static void tc358768_dsicmd_tx(struct tc358768_priv *priv)
{
u32 val;
/* start transfer */
tc358768_write(priv, TC358768_DSICMD_TX, TC358768_DSI_CMDTX_DC_START);
if (priv->error)
return;
/* wait transfer completion */
priv->error = regmap_read_poll_timeout(priv->regmap, TC358768_DSICMD_TX, val,
(val & TC358768_DSI_CMDTX_DC_START) == 0,
100, 100000);
}
static int tc358768_sw_reset(struct tc358768_priv *priv)
{
/* Assert Reset */
@ -516,8 +534,7 @@ static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
}
}
/* start transfer */
tc358768_write(priv, TC358768_DSICMD_TX, 1);
tc358768_dsicmd_tx(priv);
ret = tc358768_clear_error(priv);
if (ret)

61
drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c
View File

@ -992,7 +992,7 @@ r535_dp_train_target(struct nvkm_outp *outp, u8 target, bool mst, u8 link_nr, u8
ctrl->data = data;
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
if (ret == -EAGAIN && ctrl->retryTimeMs) {
if ((ret == -EAGAIN || ret == -EBUSY) && ctrl->retryTimeMs) {
/*
* Device (likely an eDP panel) isn't ready yet, wait for the time specified
* by GSP before retrying again
@ -1060,33 +1060,44 @@ r535_dp_aux_xfer(struct nvkm_outp *outp, u8 type, u32 addr, u8 *data, u8 *psize)
NV0073_CTRL_DP_AUXCH_CTRL_PARAMS *ctrl;
u8 size = *psize;
int ret;
int retries;
ctrl = nvkm_gsp_rm_ctrl_get(&disp->rm.objcom, NV0073_CTRL_CMD_DP_AUXCH_CTRL, sizeof(*ctrl));
if (IS_ERR(ctrl))
return PTR_ERR(ctrl);
for (retries = 0; retries < 3; ++retries) {
ctrl = nvkm_gsp_rm_ctrl_get(&disp->rm.objcom, NV0073_CTRL_CMD_DP_AUXCH_CTRL, sizeof(*ctrl));
if (IS_ERR(ctrl))
return PTR_ERR(ctrl);
ctrl->subDeviceInstance = 0;
ctrl->displayId = BIT(outp->index);
ctrl->bAddrOnly = !size;
ctrl->cmd = type;
if (ctrl->bAddrOnly) {
ctrl->cmd = NVDEF_SET(ctrl->cmd, NV0073_CTRL, DP_AUXCH_CMD, REQ_TYPE, WRITE);
ctrl->cmd = NVDEF_SET(ctrl->cmd, NV0073_CTRL, DP_AUXCH_CMD, I2C_MOT, FALSE);
ctrl->subDeviceInstance = 0;
ctrl->displayId = BIT(outp->index);
ctrl->bAddrOnly = !size;
ctrl->cmd = type;
if (ctrl->bAddrOnly) {
ctrl->cmd = NVDEF_SET(ctrl->cmd, NV0073_CTRL, DP_AUXCH_CMD, REQ_TYPE, WRITE);
ctrl->cmd = NVDEF_SET(ctrl->cmd, NV0073_CTRL, DP_AUXCH_CMD, I2C_MOT, FALSE);
}
ctrl->addr = addr;
ctrl->size = !ctrl->bAddrOnly ? (size - 1) : 0;
memcpy(ctrl->data, data, size);
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
if ((ret == -EAGAIN || ret == -EBUSY) && ctrl->retryTimeMs) {
/*
* Device (likely an eDP panel) isn't ready yet, wait for the time specified
* by GSP before retrying again
*/
nvkm_debug(&disp->engine.subdev,
"Waiting %dms for GSP LT panel delay before retrying in AUX\n",
ctrl->retryTimeMs);
msleep(ctrl->retryTimeMs);
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
} else {
memcpy(data, ctrl->data, size);
*psize = ctrl->size;
ret = ctrl->replyType;
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
break;
}
}
ctrl->addr = addr;
ctrl->size = !ctrl->bAddrOnly ? (size - 1) : 0;
memcpy(ctrl->data, data, size);
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
if (ret) {
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
return ret;
}
memcpy(data, ctrl->data, size);
*psize = ctrl->size;
ret = ctrl->replyType;
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
return ret;
}

11
drivers/gpu/drm/nouveau/nvkm/falcon/fw.c
View File

@ -89,11 +89,6 @@ nvkm_falcon_fw_boot(struct nvkm_falcon_fw *fw, struct nvkm_subdev *user,
nvkm_falcon_fw_dtor_sigs(fw);
}
/* after last write to the img, sync dma mappings */
dma_sync_single_for_device(fw->fw.device->dev,
fw->fw.phys,
sg_dma_len(&fw->fw.mem.sgl),
DMA_TO_DEVICE);
FLCNFW_DBG(fw, "resetting");
fw->func->reset(fw);
@ -105,6 +100,12 @@ nvkm_falcon_fw_boot(struct nvkm_falcon_fw *fw, struct nvkm_subdev *user,
goto done;
}
/* after last write to the img, sync dma mappings */
dma_sync_single_for_device(fw->fw.device->dev,
fw->fw.phys,
sg_dma_len(&fw->fw.mem.sgl),
DMA_TO_DEVICE);
ret = fw->func->load(fw);
if (ret)
goto done;

6
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
View File

@ -78,7 +78,7 @@ r535_rpc_status_to_errno(uint32_t rpc_status)
switch (rpc_status) {
case 0x55: /* NV_ERR_NOT_READY */
case 0x66: /* NV_ERR_TIMEOUT_RETRY */
return -EAGAIN;
return -EBUSY;
case 0x51: /* NV_ERR_NO_MEMORY */
return -ENOMEM;
default:
@ -601,7 +601,7 @@ r535_gsp_rpc_rm_alloc_push(struct nvkm_gsp_object *object, void *argv, u32 repc)
if (rpc->status) {
ret = ERR_PTR(r535_rpc_status_to_errno(rpc->status));
if (PTR_ERR(ret) != -EAGAIN)
if (PTR_ERR(ret) != -EAGAIN && PTR_ERR(ret) != -EBUSY)
nvkm_error(&gsp->subdev, "RM_ALLOC: 0x%x\n", rpc->status);
} else {
ret = repc ? rpc->params : NULL;
@ -660,7 +660,7 @@ r535_gsp_rpc_rm_ctrl_push(struct nvkm_gsp_object *object, void **argv, u32 repc)
if (rpc->status) {
ret = r535_rpc_status_to_errno(rpc->status);
if (ret != -EAGAIN)
if (ret != -EAGAIN && ret != -EBUSY)
nvkm_error(&gsp->subdev, "cli:0x%08x obj:0x%08x ctrl cmd:0x%08x failed: 0x%08x\n",
object->client->object.handle, object->handle, rpc->cmd, rpc->status);
}

2
drivers/gpu/drm/panthor/panthor_mmu.c
View File

@ -990,6 +990,8 @@ panthor_vm_map_pages(struct panthor_vm *vm, u64 iova, int prot,
if (!size)
break;
offset = 0;
}
return panthor_vm_flush_range(vm, start_iova, iova - start_iova);

8
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@ -1093,10 +1093,10 @@ static int vop_plane_atomic_async_check(struct drm_plane *plane,
if (!plane->state->fb)
return -EINVAL;
if (state)
crtc_state = drm_atomic_get_existing_crtc_state(state,
new_plane_state->crtc);
else /* Special case for asynchronous cursor updates. */
crtc_state = drm_atomic_get_existing_crtc_state(state, new_plane_state->crtc);
/* Special case for asynchronous cursor updates. */
if (!crtc_state)
crtc_state = plane->crtc->state;
return drm_atomic_helper_check_plane_state(plane->state, crtc_state,

2
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
View File

@ -1265,6 +1265,8 @@ static int vmw_framebuffer_surface_create_handle(struct drm_framebuffer *fb,
struct vmw_framebuffer_surface *vfbs = vmw_framebuffer_to_vfbs(fb);
struct vmw_bo *bo = vmw_user_object_buffer(&vfbs->uo);
if (WARN_ON(!bo))
return -EINVAL;
return drm_gem_handle_create(file_priv, &bo->tbo.base, handle);
}