mirror of
https://github.com/torvalds/linux.git
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (23 commits) sh: Make intc messages consistent via pr_fmt. sh: make sure static declaration on ms7724se sh: make sure static declaration on mach-migor sh: make sure static declaration on mach-ecovec24 sh: make sure static declaration on mach-ap325rxa clocksource: sh_cmt: compute mult and shift before registration clocksource: sh_tmu: compute mult and shift before registration sh: PIO disabling for x3proto and urquell. sh: mach-sdk7786: conditionally disable PIO support. sh: support for platforms without PIO. usb: r8a66597-hcd pio to mmio accessor conversion. usb: gadget: r8a66597-udc pio to mmio accessor conversion. usb: gadget: m66592-udc pio to mmio accessor conversion. sh: add romImage MMCIF boot for sh7724 and Ecovec V2 sh: add boot code to MMCIF driver header sh: prepare MMCIF driver header file sh: allow romImage data between head.S and the zero page sh: Add support MMCIF for ecovec sh: remove duplicated #include input: serio: disable i8042 for non-cayman sh platforms. ...
This commit is contained in:
Linus Torvalds
commit
999fd1ab34
@ -9,7 +9,7 @@ config SUPERH
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def_bool y
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select EMBEDDED
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select HAVE_CLK
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select HAVE_IDE
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select HAVE_IDE if HAS_IOPORT
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select HAVE_LMB
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select HAVE_OPROFILE
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select HAVE_GENERIC_DMA_COHERENT
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@ -174,6 +174,9 @@ config ARCH_HAS_DEFAULT_IDLE
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config ARCH_HAS_CPU_IDLE_WAIT
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def_bool y
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config NO_IOPORT
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bool
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config IO_TRAPPED
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bool
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@ -776,6 +779,17 @@ config ENTRY_OFFSET
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default "0x00010000" if PAGE_SIZE_64KB
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default "0x00000000"
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config ROMIMAGE_MMCIF
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bool "Include MMCIF loader in romImage (EXPERIMENTAL)"
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depends on CPU_SUBTYPE_SH7724 && EXPERIMENTAL
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help
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Say Y here to include experimental MMCIF loading code in
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romImage. With this enabled it is possible to write the romImage
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kernel image to an MMC card and boot the kernel straight from
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the reset vector. At reset the processor Mask ROM will load the
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first part of the romImage which in turn loads the rest the kernel
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image to RAM using the MMCIF hardware block.
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choice
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prompt "Kernel command line"
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optional
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@ -154,6 +154,7 @@ config SH_SDK7786
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bool "SDK7786"
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depends on CPU_SUBTYPE_SH7786
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select SYS_SUPPORTS_PCI
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select NO_IOPORT if !PCI
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help
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Select SDK7786 if configuring for a Renesas Technology Europe
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SH7786-65nm board.
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@ -190,6 +191,7 @@ config SH_URQUELL
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depends on CPU_SUBTYPE_SH7786
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select ARCH_REQUIRE_GPIOLIB
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select SYS_SUPPORTS_PCI
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select NO_IOPORT if !PCI
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config SH_MIGOR
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bool "Migo-R"
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@ -286,6 +288,7 @@ config SH_LBOX_RE2
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config SH_X3PROTO
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bool "SH-X3 Prototype board"
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depends on CPU_SUBTYPE_SHX3
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select NO_IOPORT if !PCI
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config SH_MAGIC_PANEL_R2
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bool "Magic Panel R2"
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@ -328,7 +328,7 @@ static struct soc_camera_platform_info camera_info = {
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.set_capture = camera_set_capture,
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};
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struct soc_camera_link camera_link = {
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static struct soc_camera_link camera_link = {
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.bus_id = 0,
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.add_device = ap325rxa_camera_add,
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.del_device = ap325rxa_camera_del,
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@ -12,6 +12,8 @@
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/sh_mobile_sdhi.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sh_mmcif.h>
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#include <linux/mtd/physmap.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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@ -26,7 +28,6 @@
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#include <linux/mmc/host.h>
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#include <linux/input.h>
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#include <linux/input/sh_keysc.h>
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#include <linux/mfd/sh_mobile_sdhi.h>
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#include <video/sh_mobile_lcdc.h>
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#include <sound/sh_fsi.h>
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#include <media/sh_mobile_ceu.h>
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@ -139,7 +140,7 @@ static struct resource sh_eth_resources[] = {
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},
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};
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struct sh_eth_plat_data sh_eth_plat = {
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static struct sh_eth_plat_data sh_eth_plat = {
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.phy = 0x1f, /* SMSC LAN8700 */
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.edmac_endian = EDMAC_LITTLE_ENDIAN,
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.ether_link_active_low = 1
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@ -159,7 +160,7 @@ static struct platform_device sh_eth_device = {
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};
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/* USB0 host */
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void usb0_port_power(int port, int power)
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static void usb0_port_power(int port, int power)
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{
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gpio_set_value(GPIO_PTB4, power);
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}
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@ -195,7 +196,7 @@ static struct platform_device usb0_host_device = {
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};
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/* USB1 host/function */
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void usb1_port_power(int port, int power)
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static void usb1_port_power(int port, int power)
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{
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gpio_set_value(GPIO_PTB5, power);
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}
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@ -421,7 +422,7 @@ static int ts_init(void)
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return 0;
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}
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struct tsc2007_platform_data tsc2007_info = {
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static struct tsc2007_platform_data tsc2007_info = {
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.model = 2007,
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.x_plate_ohms = 180,
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.get_pendown_state = ts_get_pendown_state,
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@ -436,7 +437,7 @@ static struct i2c_board_info ts_i2c_clients = {
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};
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#ifdef CONFIG_MFD_SH_MOBILE_SDHI
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/* SHDI0 */
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/* SDHI0 */
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static void sdhi0_set_pwr(struct platform_device *pdev, int state)
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{
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gpio_set_value(GPIO_PTB6, state);
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@ -474,7 +475,8 @@ static struct platform_device sdhi0_device = {
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},
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};
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/* SHDI1 */
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#if !defined(CONFIG_MMC_SH_MMCIF)
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/* SDHI1 */
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static void sdhi1_set_pwr(struct platform_device *pdev, int state)
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{
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gpio_set_value(GPIO_PTB7, state);
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@ -511,6 +513,7 @@ static struct platform_device sdhi1_device = {
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.hwblk_id = HWBLK_SDHI1,
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},
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};
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#endif /* CONFIG_MMC_SH_MMCIF */
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#else
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@ -720,7 +723,7 @@ static struct clk fsimckb_clk = {
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.rate = 0, /* unknown */
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};
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struct sh_fsi_platform_info fsi_info = {
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static struct sh_fsi_platform_info fsi_info = {
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.portb_flags = SH_FSI_BRS_INV |
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SH_FSI_OUT_SLAVE_MODE |
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SH_FSI_IN_SLAVE_MODE |
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@ -777,7 +780,7 @@ static struct platform_device irda_device = {
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#include <media/ak881x.h>
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#include <media/sh_vou.h>
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struct ak881x_pdata ak881x_pdata = {
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static struct ak881x_pdata ak881x_pdata = {
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.flags = AK881X_IF_MODE_SLAVE,
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};
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@ -786,7 +789,7 @@ static struct i2c_board_info ak8813 = {
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.platform_data = &ak881x_pdata,
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};
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struct sh_vou_pdata sh_vou_pdata = {
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static struct sh_vou_pdata sh_vou_pdata = {
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.bus_fmt = SH_VOU_BUS_8BIT,
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.flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
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.board_info = &ak8813,
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@ -819,6 +822,58 @@ static struct platform_device vou_device = {
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},
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};
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#if defined(CONFIG_MMC_SH_MMCIF)
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/* SH_MMCIF */
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static void mmcif_set_pwr(struct platform_device *pdev, int state)
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{
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gpio_set_value(GPIO_PTB7, state);
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}
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static void mmcif_down_pwr(struct platform_device *pdev)
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{
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gpio_set_value(GPIO_PTB7, 0);
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}
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static struct resource sh_mmcif_resources[] = {
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[0] = {
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.name = "SH_MMCIF",
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.start = 0xA4CA0000,
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.end = 0xA4CA00FF,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* MMC2I */
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.start = 29,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* MMC3I */
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.start = 30,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct sh_mmcif_plat_data sh_mmcif_plat = {
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.set_pwr = mmcif_set_pwr,
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.down_pwr = mmcif_down_pwr,
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.sup_pclk = 0, /* SH7724: Max Pclk/2 */
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.caps = MMC_CAP_4_BIT_DATA |
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MMC_CAP_8_BIT_DATA |
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MMC_CAP_NEEDS_POLL,
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.ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
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};
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static struct platform_device sh_mmcif_device = {
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.name = "sh_mmcif",
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.id = 0,
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.dev = {
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.platform_data = &sh_mmcif_plat,
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},
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.num_resources = ARRAY_SIZE(sh_mmcif_resources),
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.resource = sh_mmcif_resources,
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};
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#endif
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static struct platform_device *ecovec_devices[] __initdata = {
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&heartbeat_device,
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&nor_flash_device,
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@ -831,7 +886,9 @@ static struct platform_device *ecovec_devices[] __initdata = {
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&keysc_device,
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#ifdef CONFIG_MFD_SH_MOBILE_SDHI
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&sdhi0_device,
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#if !defined(CONFIG_MMC_SH_MMCIF)
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&sdhi1_device,
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#endif
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#else
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&msiof0_device,
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#endif
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@ -841,6 +898,9 @@ static struct platform_device *ecovec_devices[] __initdata = {
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&fsi_device,
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&irda_device,
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&vou_device,
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#if defined(CONFIG_MMC_SH_MMCIF)
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&sh_mmcif_device,
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#endif
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};
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#ifdef CONFIG_I2C
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@ -1134,6 +1194,7 @@ static int __init arch_setup(void)
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gpio_request(GPIO_PTB6, NULL);
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gpio_direction_output(GPIO_PTB6, 0);
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#if !defined(CONFIG_MMC_SH_MMCIF)
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/* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
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gpio_request(GPIO_FN_SDHI1CD, NULL);
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gpio_request(GPIO_FN_SDHI1WP, NULL);
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@ -1148,6 +1209,7 @@ static int __init arch_setup(void)
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/* I/O buffer drive ability is high for SDHI1 */
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__raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
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#endif /* CONFIG_MMC_SH_MMCIF */
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#else
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/* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
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gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
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@ -1223,6 +1285,25 @@ static int __init arch_setup(void)
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gpio_request(GPIO_PTU5, NULL);
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gpio_direction_output(GPIO_PTU5, 0);
|
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|
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#if defined(CONFIG_MMC_SH_MMCIF)
|
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/* enable MMCIF (needs DS2.6,7 set to OFF,ON) */
|
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gpio_request(GPIO_FN_MMC_D7, NULL);
|
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gpio_request(GPIO_FN_MMC_D6, NULL);
|
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gpio_request(GPIO_FN_MMC_D5, NULL);
|
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gpio_request(GPIO_FN_MMC_D4, NULL);
|
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gpio_request(GPIO_FN_MMC_D3, NULL);
|
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gpio_request(GPIO_FN_MMC_D2, NULL);
|
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gpio_request(GPIO_FN_MMC_D1, NULL);
|
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gpio_request(GPIO_FN_MMC_D0, NULL);
|
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gpio_request(GPIO_FN_MMC_CLK, NULL);
|
||||
gpio_request(GPIO_FN_MMC_CMD, NULL);
|
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gpio_request(GPIO_PTB7, NULL);
|
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gpio_direction_output(GPIO_PTB7, 0);
|
||||
|
||||
/* I/O buffer drive ability is high for MMCIF */
|
||||
__raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
|
||||
#endif
|
||||
|
||||
/* enable I2C device */
|
||||
i2c_register_board_info(0, i2c0_devices,
|
||||
ARRAY_SIZE(i2c0_devices));
|
||||
|
||||
@ -181,7 +181,7 @@ static int migor_nand_flash_ready(struct mtd_info *mtd)
|
||||
return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
|
||||
}
|
||||
|
||||
struct platform_nand_data migor_nand_flash_data = {
|
||||
static struct platform_nand_data migor_nand_flash_data = {
|
||||
.chip = {
|
||||
.nr_chips = 1,
|
||||
.partitions = migor_nand_flash_partitions,
|
||||
|
||||
@ -283,7 +283,7 @@ static struct clk fsimcka_clk = {
|
||||
};
|
||||
|
||||
/* change J20, J21, J22 pin to 1-2 connection to use slave mode */
|
||||
struct sh_fsi_platform_info fsi_info = {
|
||||
static struct sh_fsi_platform_info fsi_info = {
|
||||
.porta_flags = SH_FSI_BRS_INV |
|
||||
SH_FSI_OUT_SLAVE_MODE |
|
||||
SH_FSI_IN_SLAVE_MODE |
|
||||
@ -371,7 +371,7 @@ static struct resource sh_eth_resources[] = {
|
||||
},
|
||||
};
|
||||
|
||||
struct sh_eth_plat_data sh_eth_plat = {
|
||||
static struct sh_eth_plat_data sh_eth_plat = {
|
||||
.phy = 0x1f, /* SMSC LAN8187 */
|
||||
.edmac_endian = EDMAC_LITTLE_ENDIAN,
|
||||
};
|
||||
@ -535,7 +535,7 @@ static struct platform_device irda_device = {
|
||||
#include <media/ak881x.h>
|
||||
#include <media/sh_vou.h>
|
||||
|
||||
struct ak881x_pdata ak881x_pdata = {
|
||||
static struct ak881x_pdata ak881x_pdata = {
|
||||
.flags = AK881X_IF_MODE_SLAVE,
|
||||
};
|
||||
|
||||
@ -545,7 +545,7 @@ static struct i2c_board_info ak8813 = {
|
||||
.platform_data = &ak881x_pdata,
|
||||
};
|
||||
|
||||
struct sh_vou_pdata sh_vou_pdata = {
|
||||
static struct sh_vou_pdata sh_vou_pdata = {
|
||||
.bus_fmt = SH_VOU_BUS_8BIT,
|
||||
.flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
|
||||
.board_info = &ak8813,
|
||||
|
||||
@ -1,16 +1,21 @@
|
||||
#
|
||||
# linux/arch/sh/boot/romimage/Makefile
|
||||
#
|
||||
# create an image suitable for burning to flash from zImage
|
||||
# create an romImage file suitable for burning to flash/mmc from zImage
|
||||
#
|
||||
|
||||
targets := vmlinux head.o zeropage.bin piggy.o
|
||||
load-y := 0
|
||||
|
||||
OBJECTS = $(obj)/head.o
|
||||
LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext 0 -e romstart \
|
||||
mmcif-load-$(CONFIG_CPU_SUBTYPE_SH7724) := 0xe5200000 # ILRAM
|
||||
mmcif-obj-$(CONFIG_CPU_SUBTYPE_SH7724) := $(obj)/mmcif-sh7724.o
|
||||
load-$(CONFIG_ROMIMAGE_MMCIF) := $(mmcif-load-y)
|
||||
obj-$(CONFIG_ROMIMAGE_MMCIF) := $(mmcif-obj-y)
|
||||
|
||||
LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext $(load-y) -e romstart \
|
||||
-T $(obj)/../../kernel/vmlinux.lds
|
||||
|
||||
$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o FORCE
|
||||
$(obj)/vmlinux: $(obj)/head.o $(obj-y) $(obj)/piggy.o FORCE
|
||||
$(call if_changed,ld)
|
||||
@:
|
||||
|
||||
|
||||
@ -12,8 +12,40 @@ romstart:
|
||||
/* include board specific setup code */
|
||||
#include <mach/romimage.h>
|
||||
|
||||
#ifdef CONFIG_ROMIMAGE_MMCIF
|
||||
/* load the romImage to above the empty zero page */
|
||||
mov.l empty_zero_page_dst, r4
|
||||
mov.l empty_zero_page_dst_adj, r5
|
||||
add r5, r4
|
||||
mov.l bytes_to_load, r5
|
||||
mov.l loader_function, r7
|
||||
jsr @r7
|
||||
mov r4, r15
|
||||
|
||||
mov.l empty_zero_page_dst, r4
|
||||
mov.l empty_zero_page_dst_adj, r5
|
||||
add r5, r4
|
||||
mov.l loaded_code_offs, r5
|
||||
add r5, r4
|
||||
jmp @r4
|
||||
nop
|
||||
|
||||
.balign 4
|
||||
empty_zero_page_dst_adj:
|
||||
.long PAGE_SIZE
|
||||
bytes_to_load:
|
||||
.long end_data - romstart
|
||||
loader_function:
|
||||
.long mmcif_loader
|
||||
loaded_code_offs:
|
||||
.long loaded_code - romstart
|
||||
loaded_code:
|
||||
#endif /* CONFIG_ROMIMAGE_MMCIF */
|
||||
|
||||
/* copy the empty_zero_page contents to where vmlinux expects it */
|
||||
mova empty_zero_page_src, r0
|
||||
mova extra_data_pos, r0
|
||||
mov.l extra_data_size, r1
|
||||
add r1, r0
|
||||
mov.l empty_zero_page_dst, r1
|
||||
mov #(PAGE_SHIFT - 4), r4
|
||||
mov #1, r3
|
||||
@ -37,7 +69,9 @@ romstart:
|
||||
mov #PAGE_SHIFT, r4
|
||||
mov #1, r1
|
||||
shld r4, r1
|
||||
mova empty_zero_page_src, r0
|
||||
mova extra_data_pos, r0
|
||||
add r1, r0
|
||||
mov.l extra_data_size, r1
|
||||
add r1, r0
|
||||
jmp @r0
|
||||
nop
|
||||
@ -45,4 +79,6 @@ romstart:
|
||||
.align 2
|
||||
empty_zero_page_dst:
|
||||
.long _text
|
||||
empty_zero_page_src:
|
||||
extra_data_pos:
|
||||
extra_data_size:
|
||||
.long zero_page_pos - extra_data_pos
|
||||
|
||||
72
arch/sh/boot/romimage/mmcif-sh7724.c
Normal file
72
arch/sh/boot/romimage/mmcif-sh7724.c
Normal file
@ -0,0 +1,72 @@
|
||||
/*
|
||||
* sh7724 MMCIF loader
|
||||
*
|
||||
* Copyright (C) 2010 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/mmc/sh_mmcif.h>
|
||||
#include <mach/romimage.h>
|
||||
|
||||
#define MMCIF_BASE (void __iomem *)0xa4ca0000
|
||||
|
||||
#define MSTPCR2 0xa4150038
|
||||
#define PTWCR 0xa4050146
|
||||
#define PTXCR 0xa4050148
|
||||
#define PSELA 0xa405014e
|
||||
#define PSELE 0xa4050156
|
||||
#define HIZCRC 0xa405015c
|
||||
#define DRVCRA 0xa405018a
|
||||
|
||||
enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT,
|
||||
MMCIF_PROGRESS_LOAD, MMCIF_PROGRESS_DONE };
|
||||
|
||||
/* SH7724 specific MMCIF loader
|
||||
*
|
||||
* loads the romImage from an MMC card starting from block 512
|
||||
* use the following line to write the romImage to an MMC card
|
||||
* # dd if=arch/sh/boot/romImage of=/dev/sdx bs=512 seek=512
|
||||
*/
|
||||
asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes)
|
||||
{
|
||||
mmcif_update_progress(MMCIF_PROGRESS_ENTER);
|
||||
|
||||
/* enable clock to the MMCIF hardware block */
|
||||
__raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2);
|
||||
|
||||
/* setup pins D7-D0 */
|
||||
__raw_writew(0x0000, PTWCR);
|
||||
|
||||
/* setup pins MMC_CLK, MMC_CMD */
|
||||
__raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR);
|
||||
|
||||
/* select D3-D0 pin function */
|
||||
__raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA);
|
||||
|
||||
/* select D7-D4 pin function */
|
||||
__raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE);
|
||||
|
||||
/* disable Hi-Z for the MMC pins */
|
||||
__raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC);
|
||||
|
||||
/* high drive capability for MMC pins */
|
||||
__raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA);
|
||||
|
||||
mmcif_update_progress(MMCIF_PROGRESS_INIT);
|
||||
|
||||
/* setup MMCIF hardware */
|
||||
sh_mmcif_boot_init(MMCIF_BASE);
|
||||
|
||||
mmcif_update_progress(MMCIF_PROGRESS_LOAD);
|
||||
|
||||
/* load kernel via MMCIF interface */
|
||||
sh_mmcif_boot_slurp(MMCIF_BASE, buf, no_bytes);
|
||||
|
||||
/* disable clock to the MMCIF hardware block */
|
||||
__raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2);
|
||||
|
||||
mmcif_update_progress(MMCIF_PROGRESS_DONE);
|
||||
}
|
||||
@ -1,6 +1,8 @@
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
zero_page_pos = .;
|
||||
*(.data)
|
||||
end_data = .;
|
||||
}
|
||||
}
|
||||
|
||||
@ -39,6 +39,8 @@
|
||||
#include <asm/io_generic.h>
|
||||
#include <asm/io_trapped.h>
|
||||
|
||||
#ifdef CONFIG_HAS_IOPORT
|
||||
|
||||
#define inb(p) sh_mv.mv_inb((p))
|
||||
#define inw(p) sh_mv.mv_inw((p))
|
||||
#define inl(p) sh_mv.mv_inl((p))
|
||||
@ -60,6 +62,8 @@
|
||||
#define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
|
||||
#define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
|
||||
|
||||
#endif
|
||||
|
||||
#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
|
||||
#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
|
||||
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
|
||||
@ -240,6 +244,8 @@ __BUILD_MEMORY_STRING(q, u64)
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
#ifdef CONFIG_HAS_IOPORT
|
||||
|
||||
/*
|
||||
* This function provides a method for the generic case where a
|
||||
* board-specific ioport_map simply needs to return the port + some
|
||||
@ -255,6 +261,8 @@ static inline void __set_io_port_base(unsigned long pbase)
|
||||
|
||||
#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
|
||||
|
||||
#endif
|
||||
|
||||
/* We really want to try and get these to memcpy etc */
|
||||
void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
|
||||
void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
|
||||
|
||||
@ -19,6 +19,10 @@ struct sh_machine_vector {
|
||||
const char *mv_name;
|
||||
int mv_nr_irqs;
|
||||
|
||||
int (*mv_irq_demux)(int irq);
|
||||
void (*mv_init_irq)(void);
|
||||
|
||||
#ifdef CONFIG_HAS_IOPORT
|
||||
u8 (*mv_inb)(unsigned long);
|
||||
u16 (*mv_inw)(unsigned long);
|
||||
u32 (*mv_inl)(unsigned long);
|
||||
@ -40,12 +44,9 @@ struct sh_machine_vector {
|
||||
void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
|
||||
void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
|
||||
|
||||
int (*mv_irq_demux)(int irq);
|
||||
|
||||
void (*mv_init_irq)(void);
|
||||
|
||||
void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
|
||||
void (*mv_ioport_unmap)(void __iomem *);
|
||||
#endif
|
||||
|
||||
int (*mv_clk_init)(void);
|
||||
int (*mv_mode_pins)(void);
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
* MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
|
||||
* MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
|
||||
* MD8: Test Mode
|
||||
* BOOT: FBR - Boot Mode (L: MMCIF, H: Area0)
|
||||
*/
|
||||
|
||||
/* Pin Function Controller:
|
||||
|
||||
@ -1 +1,11 @@
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/* do nothing here by default */
|
||||
|
||||
#else /* __ASSEMBLY__ */
|
||||
|
||||
extern inline void mmcif_update_progress(int nr)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
@ -1,3 +1,5 @@
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/* EcoVec board specific boot code:
|
||||
* converts the "partner-jet-script.txt" script into assembly
|
||||
* the assembly code is the first code to be executed in the romImage
|
||||
@ -18,3 +20,28 @@
|
||||
.align 2
|
||||
1 : .long 0xa8000000
|
||||
2 :
|
||||
|
||||
#else /* __ASSEMBLY__ */
|
||||
|
||||
/* Ecovec board specific information:
|
||||
*
|
||||
* Set the following to enable MMCIF boot from the MMC card in CN12:
|
||||
*
|
||||
* DS1.5 = OFF (SH BOOT pin set to L)
|
||||
* DS2.6 = OFF (Select MMCIF on CN12 instead of SDHI1)
|
||||
* DS2.7 = ON (Select MMCIF on CN12 instead of SDHI1)
|
||||
*
|
||||
*/
|
||||
#define HIZCRA 0xa4050158
|
||||
#define PGDR 0xa405012c
|
||||
|
||||
extern inline void mmcif_update_progress(int nr)
|
||||
{
|
||||
/* disable Hi-Z for LED pins */
|
||||
__raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA);
|
||||
|
||||
/* update progress on LED4, LED5, LED6 and LED7 */
|
||||
__raw_writeb(1 << (nr - 1), PGDR);
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
@ -1,3 +1,5 @@
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/* kfr2r09 board specific boot code:
|
||||
* converts the "partner-jet-script.txt" script into assembly
|
||||
* the assembly code is the first code to be executed in the romImage
|
||||
@ -18,3 +20,11 @@
|
||||
.align 2
|
||||
1: .long 0xa8000000
|
||||
2:
|
||||
|
||||
#else /* __ASSEMBLY__ */
|
||||
|
||||
extern inline void mmcif_update_progress(int nr)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
@ -12,7 +12,7 @@ endif
|
||||
CFLAGS_REMOVE_return_address.o = -pg
|
||||
|
||||
obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \
|
||||
idle.o io.o io_generic.o irq.o \
|
||||
idle.o io.o irq.o \
|
||||
irq_$(BITS).o machvec.o nmi_debug.o process.o \
|
||||
process_$(BITS).o ptrace_$(BITS).o \
|
||||
reboot.o return_address.o \
|
||||
@ -39,6 +39,7 @@ obj-$(CONFIG_DUMP_CODE) += disassemble.o
|
||||
obj-$(CONFIG_HIBERNATION) += swsusp.o
|
||||
obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o
|
||||
obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_callchain.o
|
||||
obj-$(CONFIG_HAS_IOPORT) += io_generic.o
|
||||
|
||||
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
|
||||
obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
|
||||
|
||||
@ -49,6 +49,8 @@ static DEFINE_SPINLOCK(dwarf_fde_lock);
|
||||
|
||||
static struct dwarf_cie *cached_cie;
|
||||
|
||||
static unsigned int dwarf_unwinder_ready;
|
||||
|
||||
/**
|
||||
* dwarf_frame_alloc_reg - allocate memory for a DWARF register
|
||||
* @frame: the DWARF frame whose list of registers we insert on
|
||||
@ -581,6 +583,13 @@ struct dwarf_frame *dwarf_unwind_stack(unsigned long pc,
|
||||
struct dwarf_reg *reg;
|
||||
unsigned long addr;
|
||||
|
||||
/*
|
||||
* If we've been called in to before initialization has
|
||||
* completed, bail out immediately.
|
||||
*/
|
||||
if (!dwarf_unwinder_ready)
|
||||
return NULL;
|
||||
|
||||
/*
|
||||
* If we're starting at the top of the stack we need get the
|
||||
* contents of a physical register to get the CFA in order to
|
||||
@ -1167,7 +1176,7 @@ void module_dwarf_cleanup(struct module *mod)
|
||||
*/
|
||||
static int __init dwarf_unwinder_init(void)
|
||||
{
|
||||
int err;
|
||||
int err = -ENOMEM;
|
||||
|
||||
dwarf_frame_cachep = kmem_cache_create("dwarf_frames",
|
||||
sizeof(struct dwarf_frame), 0,
|
||||
@ -1181,11 +1190,15 @@ static int __init dwarf_unwinder_init(void)
|
||||
mempool_alloc_slab,
|
||||
mempool_free_slab,
|
||||
dwarf_frame_cachep);
|
||||
if (!dwarf_frame_pool)
|
||||
goto out;
|
||||
|
||||
dwarf_reg_pool = mempool_create(DWARF_REG_MIN_REQ,
|
||||
mempool_alloc_slab,
|
||||
mempool_free_slab,
|
||||
dwarf_reg_cachep);
|
||||
if (!dwarf_reg_pool)
|
||||
goto out;
|
||||
|
||||
err = dwarf_parse_section(__start_eh_frame, __stop_eh_frame, NULL);
|
||||
if (err)
|
||||
@ -1195,11 +1208,13 @@ static int __init dwarf_unwinder_init(void)
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
dwarf_unwinder_ready = 1;
|
||||
|
||||
return 0;
|
||||
|
||||
out:
|
||||
printk(KERN_ERR "Failed to initialise DWARF unwinder: %d\n", err);
|
||||
dwarf_unwinder_cleanup();
|
||||
return -EINVAL;
|
||||
return err;
|
||||
}
|
||||
early_initcall(dwarf_unwinder_init);
|
||||
|
||||
@ -112,25 +112,3 @@ void memset_io(volatile void __iomem *dst, int c, unsigned long count)
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(memset_io);
|
||||
|
||||
#ifndef CONFIG_GENERIC_IOMAP
|
||||
|
||||
void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
||||
{
|
||||
void __iomem *ret;
|
||||
|
||||
ret = __ioport_map_trapped(port, nr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return __ioport_map(port, nr);
|
||||
}
|
||||
EXPORT_SYMBOL(ioport_map);
|
||||
|
||||
void ioport_unmap(void __iomem *addr)
|
||||
{
|
||||
sh_mv.mv_ioport_unmap(addr);
|
||||
}
|
||||
EXPORT_SYMBOL(ioport_unmap);
|
||||
|
||||
#endif /* CONFIG_GENERIC_IOMAP */
|
||||
|
||||
@ -158,3 +158,23 @@ void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
|
||||
void generic_ioport_unmap(void __iomem *addr)
|
||||
{
|
||||
}
|
||||
|
||||
#ifndef CONFIG_GENERIC_IOMAP
|
||||
void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
||||
{
|
||||
void __iomem *ret;
|
||||
|
||||
ret = __ioport_map_trapped(port, nr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return __ioport_map(port, nr);
|
||||
}
|
||||
EXPORT_SYMBOL(ioport_map);
|
||||
|
||||
void ioport_unmap(void __iomem *addr)
|
||||
{
|
||||
sh_mv.mv_ioport_unmap(addr);
|
||||
}
|
||||
EXPORT_SYMBOL(ioport_unmap);
|
||||
#endif /* CONFIG_GENERIC_IOMAP */
|
||||
|
||||
@ -91,10 +91,14 @@ int register_trapped_io(struct trapped_io *tiop)
|
||||
tiop->magic = IO_TRAPPED_MAGIC;
|
||||
INIT_LIST_HEAD(&tiop->list);
|
||||
spin_lock_irq(&trapped_lock);
|
||||
#ifdef CONFIG_HAS_IOPORT
|
||||
if (flags & IORESOURCE_IO)
|
||||
list_add(&tiop->list, &trapped_io);
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_IOMEM
|
||||
if (flags & IORESOURCE_MEM)
|
||||
list_add(&tiop->list, &trapped_mem);
|
||||
#endif
|
||||
spin_unlock_irq(&trapped_lock);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -118,6 +118,14 @@ void __init sh_mv_setup(void)
|
||||
sh_mv.mv_##elem = generic_##elem; \
|
||||
} while (0)
|
||||
|
||||
#ifdef CONFIG_HAS_IOPORT
|
||||
|
||||
#ifdef P2SEG
|
||||
__set_io_port_base(P2SEG);
|
||||
#else
|
||||
__set_io_port_base(0);
|
||||
#endif
|
||||
|
||||
mv_set(inb); mv_set(inw); mv_set(inl);
|
||||
mv_set(outb); mv_set(outw); mv_set(outl);
|
||||
|
||||
@ -129,16 +137,13 @@ void __init sh_mv_setup(void)
|
||||
|
||||
mv_set(ioport_map);
|
||||
mv_set(ioport_unmap);
|
||||
|
||||
#endif
|
||||
|
||||
mv_set(irq_demux);
|
||||
mv_set(mode_pins);
|
||||
mv_set(mem_init);
|
||||
|
||||
if (!sh_mv.mv_nr_irqs)
|
||||
sh_mv.mv_nr_irqs = NR_IRQS;
|
||||
|
||||
#ifdef P2SEG
|
||||
__set_io_port_base(P2SEG);
|
||||
#else
|
||||
__set_io_port_base(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -24,6 +24,8 @@ void *return_address(unsigned int depth)
|
||||
struct dwarf_frame *tmp;
|
||||
|
||||
tmp = dwarf_unwind_stack(ra, frame);
|
||||
if (!tmp)
|
||||
return NULL;
|
||||
|
||||
if (frame)
|
||||
dwarf_free_frame(frame);
|
||||
|
||||
@ -412,18 +412,10 @@ static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
|
||||
static int sh_cmt_clocksource_enable(struct clocksource *cs)
|
||||
{
|
||||
struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
|
||||
int ret;
|
||||
|
||||
p->total_cycles = 0;
|
||||
|
||||
ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* TODO: calculate good shift from rate and counter bit width */
|
||||
cs->shift = 0;
|
||||
cs->mult = clocksource_hz2mult(p->rate, cs->shift);
|
||||
return 0;
|
||||
return sh_cmt_start(p, FLAG_CLOCKSOURCE);
|
||||
}
|
||||
|
||||
static void sh_cmt_clocksource_disable(struct clocksource *cs)
|
||||
@ -450,8 +442,20 @@ static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
|
||||
cs->resume = sh_cmt_clocksource_resume;
|
||||
cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
|
||||
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
|
||||
|
||||
/* clk_get_rate() needs an enabled clock */
|
||||
clk_enable(p->clk);
|
||||
p->rate = clk_get_rate(p->clk) / (p->width == 16) ? 512 : 8;
|
||||
clk_disable(p->clk);
|
||||
|
||||
/* TODO: calculate good shift from rate and counter bit width */
|
||||
cs->shift = 10;
|
||||
cs->mult = clocksource_hz2mult(p->rate, cs->shift);
|
||||
|
||||
dev_info(&p->pdev->dev, "used as clock source\n");
|
||||
|
||||
clocksource_register(cs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -199,16 +199,8 @@ static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
|
||||
static int sh_tmu_clocksource_enable(struct clocksource *cs)
|
||||
{
|
||||
struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
|
||||
int ret;
|
||||
|
||||
ret = sh_tmu_enable(p);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* TODO: calculate good shift from rate and counter bit width */
|
||||
cs->shift = 10;
|
||||
cs->mult = clocksource_hz2mult(p->rate, cs->shift);
|
||||
return 0;
|
||||
return sh_tmu_enable(p);
|
||||
}
|
||||
|
||||
static void sh_tmu_clocksource_disable(struct clocksource *cs)
|
||||
@ -228,6 +220,16 @@ static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
|
||||
cs->disable = sh_tmu_clocksource_disable;
|
||||
cs->mask = CLOCKSOURCE_MASK(32);
|
||||
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
|
||||
|
||||
/* clk_get_rate() needs an enabled clock */
|
||||
clk_enable(p->clk);
|
||||
/* channel will be configured at parent clock / 4 */
|
||||
p->rate = clk_get_rate(p->clk) / 4;
|
||||
clk_disable(p->clk);
|
||||
/* TODO: calculate good shift from rate and counter bit width */
|
||||
cs->shift = 10;
|
||||
cs->mult = clocksource_hz2mult(p->rate, cs->shift);
|
||||
|
||||
dev_info(&p->pdev->dev, "used as clock source\n");
|
||||
clocksource_register(cs);
|
||||
return 0;
|
||||
|
||||
@ -21,7 +21,8 @@ if SERIO
|
||||
config SERIO_I8042
|
||||
tristate "i8042 PC Keyboard controller" if EMBEDDED || !X86
|
||||
default y
|
||||
depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && !M68K && !BLACKFIN
|
||||
depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && \
|
||||
(!SUPERH || SH_CAYMAN) && !M68K && !BLACKFIN
|
||||
help
|
||||
i8042 is the chip over which the standard AT keyboard and PS/2
|
||||
mouse are connected to the computer. If you use these devices,
|
||||
|
||||
@ -30,25 +30,6 @@
|
||||
#define DRIVER_NAME "sh_mmcif"
|
||||
#define DRIVER_VERSION "2010-04-28"
|
||||
|
||||
#define MMCIF_CE_CMD_SET 0x00000000
|
||||
#define MMCIF_CE_ARG 0x00000008
|
||||
#define MMCIF_CE_ARG_CMD12 0x0000000C
|
||||
#define MMCIF_CE_CMD_CTRL 0x00000010
|
||||
#define MMCIF_CE_BLOCK_SET 0x00000014
|
||||
#define MMCIF_CE_CLK_CTRL 0x00000018
|
||||
#define MMCIF_CE_BUF_ACC 0x0000001C
|
||||
#define MMCIF_CE_RESP3 0x00000020
|
||||
#define MMCIF_CE_RESP2 0x00000024
|
||||
#define MMCIF_CE_RESP1 0x00000028
|
||||
#define MMCIF_CE_RESP0 0x0000002C
|
||||
#define MMCIF_CE_RESP_CMD12 0x00000030
|
||||
#define MMCIF_CE_DATA 0x00000034
|
||||
#define MMCIF_CE_INT 0x00000040
|
||||
#define MMCIF_CE_INT_MASK 0x00000044
|
||||
#define MMCIF_CE_HOST_STS1 0x00000048
|
||||
#define MMCIF_CE_HOST_STS2 0x0000004C
|
||||
#define MMCIF_CE_VERSION 0x0000007C
|
||||
|
||||
/* CE_CMD_SET */
|
||||
#define CMD_MASK 0x3f000000
|
||||
#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
|
||||
@ -207,27 +188,17 @@ struct sh_mmcif_host {
|
||||
wait_queue_head_t intr_wait;
|
||||
};
|
||||
|
||||
static inline u32 sh_mmcif_readl(struct sh_mmcif_host *host, unsigned int reg)
|
||||
{
|
||||
return readl(host->addr + reg);
|
||||
}
|
||||
|
||||
static inline void sh_mmcif_writel(struct sh_mmcif_host *host,
|
||||
unsigned int reg, u32 val)
|
||||
{
|
||||
writel(val, host->addr + reg);
|
||||
}
|
||||
|
||||
static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
|
||||
unsigned int reg, u32 val)
|
||||
{
|
||||
writel(val | sh_mmcif_readl(host, reg), host->addr + reg);
|
||||
writel(val | readl(host->addr + reg), host->addr + reg);
|
||||
}
|
||||
|
||||
static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
|
||||
unsigned int reg, u32 val)
|
||||
{
|
||||
writel(~val & sh_mmcif_readl(host, reg), host->addr + reg);
|
||||
writel(~val & readl(host->addr + reg), host->addr + reg);
|
||||
}
|
||||
|
||||
|
||||
@ -253,10 +224,10 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = 0x010f0000 & sh_mmcif_readl(host, MMCIF_CE_CLK_CTRL);
|
||||
tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
|
||||
|
||||
sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_ON);
|
||||
sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_OFF);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
|
||||
sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
|
||||
SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
|
||||
/* byte swap on */
|
||||
@ -271,12 +242,10 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
|
||||
host->sd_error = 0;
|
||||
host->wait_int = 0;
|
||||
|
||||
state1 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS1);
|
||||
state2 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS2);
|
||||
pr_debug("%s: ERR HOST_STS1 = %08x\n", \
|
||||
DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS1));
|
||||
pr_debug("%s: ERR HOST_STS2 = %08x\n", \
|
||||
DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS2));
|
||||
state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
|
||||
state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
|
||||
pr_debug("%s: ERR HOST_STS1 = %08x\n", DRIVER_NAME, state1);
|
||||
pr_debug("%s: ERR HOST_STS2 = %08x\n", DRIVER_NAME, state2);
|
||||
|
||||
if (state1 & STS1_CMDSEQ) {
|
||||
sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
|
||||
@ -288,7 +257,7 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
|
||||
"command sequence timeout err\n");
|
||||
return -EIO;
|
||||
}
|
||||
if (!(sh_mmcif_readl(host, MMCIF_CE_HOST_STS1)
|
||||
if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
|
||||
& STS1_CMDSEQ))
|
||||
break;
|
||||
mdelay(1);
|
||||
@ -330,9 +299,9 @@ static int sh_mmcif_single_read(struct sh_mmcif_host *host,
|
||||
|
||||
host->wait_int = 0;
|
||||
blocksize = (BLOCK_SIZE_MASK &
|
||||
sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3;
|
||||
sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
|
||||
for (i = 0; i < blocksize / 4; i++)
|
||||
*p++ = sh_mmcif_readl(host, MMCIF_CE_DATA);
|
||||
*p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
|
||||
|
||||
/* buffer read end */
|
||||
sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
|
||||
@ -353,7 +322,8 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
|
||||
long time;
|
||||
u32 blocksize, i, j, sec, *p;
|
||||
|
||||
blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET);
|
||||
blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
|
||||
MMCIF_CE_BLOCK_SET);
|
||||
for (j = 0; j < data->sg_len; j++) {
|
||||
p = sg_virt(data->sg);
|
||||
host->wait_int = 0;
|
||||
@ -370,7 +340,8 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
|
||||
|
||||
host->wait_int = 0;
|
||||
for (i = 0; i < blocksize / 4; i++)
|
||||
*p++ = sh_mmcif_readl(host, MMCIF_CE_DATA);
|
||||
*p++ = sh_mmcif_readl(host->addr,
|
||||
MMCIF_CE_DATA);
|
||||
}
|
||||
if (j < data->sg_len - 1)
|
||||
data->sg++;
|
||||
@ -397,9 +368,9 @@ static int sh_mmcif_single_write(struct sh_mmcif_host *host,
|
||||
|
||||
host->wait_int = 0;
|
||||
blocksize = (BLOCK_SIZE_MASK &
|
||||
sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3;
|
||||
sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
|
||||
for (i = 0; i < blocksize / 4; i++)
|
||||
sh_mmcif_writel(host, MMCIF_CE_DATA, *p++);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
|
||||
|
||||
/* buffer write end */
|
||||
sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
|
||||
@ -421,7 +392,8 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
|
||||
long time;
|
||||
u32 i, sec, j, blocksize, *p;
|
||||
|
||||
blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET);
|
||||
blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
|
||||
MMCIF_CE_BLOCK_SET);
|
||||
|
||||
for (j = 0; j < data->sg_len; j++) {
|
||||
p = sg_virt(data->sg);
|
||||
@ -439,7 +411,8 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
|
||||
|
||||
host->wait_int = 0;
|
||||
for (i = 0; i < blocksize / 4; i++)
|
||||
sh_mmcif_writel(host, MMCIF_CE_DATA, *p++);
|
||||
sh_mmcif_writel(host->addr,
|
||||
MMCIF_CE_DATA, *p++);
|
||||
}
|
||||
if (j < data->sg_len - 1)
|
||||
data->sg++;
|
||||
@ -451,18 +424,18 @@ static void sh_mmcif_get_response(struct sh_mmcif_host *host,
|
||||
struct mmc_command *cmd)
|
||||
{
|
||||
if (cmd->flags & MMC_RSP_136) {
|
||||
cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP3);
|
||||
cmd->resp[1] = sh_mmcif_readl(host, MMCIF_CE_RESP2);
|
||||
cmd->resp[2] = sh_mmcif_readl(host, MMCIF_CE_RESP1);
|
||||
cmd->resp[3] = sh_mmcif_readl(host, MMCIF_CE_RESP0);
|
||||
cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
|
||||
cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
|
||||
cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
|
||||
cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
|
||||
} else
|
||||
cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP0);
|
||||
cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
|
||||
}
|
||||
|
||||
static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
|
||||
struct mmc_command *cmd)
|
||||
{
|
||||
cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP_CMD12);
|
||||
cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
|
||||
}
|
||||
|
||||
static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
|
||||
@ -596,18 +569,19 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
|
||||
MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
|
||||
|
||||
if (host->data) {
|
||||
sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, 0);
|
||||
sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, mrq->data->blksz);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
|
||||
mrq->data->blksz);
|
||||
}
|
||||
opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
|
||||
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT, 0xD80430C0);
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT_MASK, mask);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
|
||||
/* set arg */
|
||||
sh_mmcif_writel(host, MMCIF_CE_ARG, cmd->arg);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
|
||||
host->wait_int = 0;
|
||||
/* set cmd */
|
||||
sh_mmcif_writel(host, MMCIF_CE_CMD_SET, opc);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
|
||||
|
||||
time = wait_event_interruptible_timeout(host->intr_wait,
|
||||
host->wait_int == 1 || host->sd_error == 1, host->timeout);
|
||||
@ -752,43 +726,44 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
|
||||
u32 state = 0;
|
||||
int err = 0;
|
||||
|
||||
state = sh_mmcif_readl(host, MMCIF_CE_INT);
|
||||
state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
|
||||
|
||||
if (state & INT_RBSYE) {
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT, ~(INT_RBSYE | INT_CRSPE));
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT,
|
||||
~(INT_RBSYE | INT_CRSPE));
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
|
||||
} else if (state & INT_CRSPE) {
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_CRSPE);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
|
||||
} else if (state & INT_BUFREN) {
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFREN);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
|
||||
} else if (state & INT_BUFWEN) {
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFWEN);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
|
||||
} else if (state & INT_CMD12DRE) {
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT,
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT,
|
||||
~(INT_CMD12DRE | INT_CMD12RBE |
|
||||
INT_CMD12CRE | INT_BUFRE));
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
|
||||
} else if (state & INT_BUFRE) {
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFRE);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
|
||||
} else if (state & INT_DTRANE) {
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_DTRANE);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
|
||||
} else if (state & INT_CMD12RBE) {
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT,
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT,
|
||||
~(INT_CMD12RBE | INT_CMD12CRE));
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
|
||||
} else if (state & INT_ERR_STS) {
|
||||
/* err interrupts */
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT, ~state);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
|
||||
err = 1;
|
||||
} else {
|
||||
pr_debug("%s: Not support int\n", DRIVER_NAME);
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT, ~state);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
|
||||
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
|
||||
err = 1;
|
||||
}
|
||||
@ -894,12 +869,12 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
|
||||
goto clean_up2;
|
||||
}
|
||||
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
|
||||
sh_mmcif_detect(host->mmc);
|
||||
|
||||
pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION);
|
||||
pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME,
|
||||
sh_mmcif_readl(host, MMCIF_CE_VERSION) & 0x0000ffff);
|
||||
sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
|
||||
return ret;
|
||||
|
||||
clean_up2:
|
||||
@ -917,7 +892,7 @@ static int __devexit sh_mmcif_remove(struct platform_device *pdev)
|
||||
struct sh_mmcif_host *host = platform_get_drvdata(pdev);
|
||||
int irq[2];
|
||||
|
||||
sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL);
|
||||
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
|
||||
|
||||
irq[0] = platform_get_irq(pdev, 0);
|
||||
irq[1] = platform_get_irq(pdev, 1);
|
||||
|
||||
@ -16,6 +16,8 @@
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/module.h>
|
||||
@ -855,8 +857,8 @@ static void __init intc_register_irq(struct intc_desc *desc,
|
||||
primary = 1;
|
||||
|
||||
if (!data[0] && !data[1])
|
||||
pr_warning("intc: missing unique irq mask for "
|
||||
"irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
|
||||
pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
|
||||
irq, irq2evt(irq));
|
||||
|
||||
data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
|
||||
data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
|
||||
@ -952,7 +954,7 @@ int __init register_intc_controller(struct intc_desc *desc)
|
||||
struct intc_desc_int *d;
|
||||
struct resource *res;
|
||||
|
||||
pr_info("intc: Registered controller '%s' with %u IRQs\n",
|
||||
pr_info("Registered controller '%s' with %u IRQs\n",
|
||||
desc->name, hw->nr_vectors);
|
||||
|
||||
d = kzalloc(sizeof(*d), GFP_NOWAIT);
|
||||
@ -1148,7 +1150,7 @@ int register_intc_userimask(unsigned long addr)
|
||||
if (unlikely(!uimask))
|
||||
return -ENOMEM;
|
||||
|
||||
pr_info("intc: userimask support registered for levels 0 -> %d\n",
|
||||
pr_info("userimask support registered for levels 0 -> %d\n",
|
||||
default_prio_level - 1);
|
||||
|
||||
return 0;
|
||||
@ -1286,7 +1288,7 @@ static int __init register_intc_sysdevs(void)
|
||||
}
|
||||
|
||||
if (error)
|
||||
pr_err("intc: sysdev registration error\n");
|
||||
pr_err("sysdev registration error\n");
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
@ -537,35 +537,35 @@ struct m66592 {
|
||||
/*-------------------------------------------------------------------------*/
|
||||
static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
|
||||
{
|
||||
return inw((unsigned long)m66592->reg + offset);
|
||||
return ioread16(m66592->reg + offset);
|
||||
}
|
||||
|
||||
static inline void m66592_read_fifo(struct m66592 *m66592,
|
||||
unsigned long offset,
|
||||
void *buf, unsigned long len)
|
||||
{
|
||||
unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
|
||||
void __iomem *fifoaddr = m66592->reg + offset;
|
||||
|
||||
if (m66592->pdata->on_chip) {
|
||||
len = (len + 3) / 4;
|
||||
insl(fifoaddr, buf, len);
|
||||
ioread32_rep(fifoaddr, buf, len);
|
||||
} else {
|
||||
len = (len + 1) / 2;
|
||||
insw(fifoaddr, buf, len);
|
||||
ioread16_rep(fifoaddr, buf, len);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void m66592_write(struct m66592 *m66592, u16 val,
|
||||
unsigned long offset)
|
||||
{
|
||||
outw(val, (unsigned long)m66592->reg + offset);
|
||||
iowrite16(val, m66592->reg + offset);
|
||||
}
|
||||
|
||||
static inline void m66592_write_fifo(struct m66592 *m66592,
|
||||
unsigned long offset,
|
||||
void *buf, unsigned long len)
|
||||
{
|
||||
unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
|
||||
void __iomem *fifoaddr = m66592->reg + offset;
|
||||
|
||||
if (m66592->pdata->on_chip) {
|
||||
unsigned long count;
|
||||
@ -573,25 +573,25 @@ static inline void m66592_write_fifo(struct m66592 *m66592,
|
||||
int i;
|
||||
|
||||
count = len / 4;
|
||||
outsl(fifoaddr, buf, count);
|
||||
iowrite32_rep(fifoaddr, buf, count);
|
||||
|
||||
if (len & 0x00000003) {
|
||||
pb = buf + count * 4;
|
||||
for (i = 0; i < (len & 0x00000003); i++) {
|
||||
if (m66592_read(m66592, M66592_CFBCFG)) /* le */
|
||||
outb(pb[i], fifoaddr + (3 - i));
|
||||
iowrite8(pb[i], fifoaddr + (3 - i));
|
||||
else
|
||||
outb(pb[i], fifoaddr + i);
|
||||
iowrite8(pb[i], fifoaddr + i);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
unsigned long odd = len & 0x0001;
|
||||
|
||||
len = len / 2;
|
||||
outsw(fifoaddr, buf, len);
|
||||
iowrite16_rep(fifoaddr, buf, len);
|
||||
if (odd) {
|
||||
unsigned char *p = buf + len*2;
|
||||
outb(*p, fifoaddr);
|
||||
iowrite8(*p, fifoaddr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1500,7 +1500,7 @@ static int __exit r8a66597_remove(struct platform_device *pdev)
|
||||
struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
del_timer_sync(&r8a66597->timer);
|
||||
iounmap((void *)r8a66597->reg);
|
||||
iounmap(r8a66597->reg);
|
||||
free_irq(platform_get_irq(pdev, 0), r8a66597);
|
||||
r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
@ -1578,7 +1578,7 @@ static int __init r8a66597_probe(struct platform_device *pdev)
|
||||
init_timer(&r8a66597->timer);
|
||||
r8a66597->timer.function = r8a66597_timer;
|
||||
r8a66597->timer.data = (unsigned long)r8a66597;
|
||||
r8a66597->reg = (unsigned long)reg;
|
||||
r8a66597->reg = reg;
|
||||
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
if (r8a66597->pdata->on_chip) {
|
||||
|
||||
@ -91,7 +91,7 @@ struct r8a66597_ep {
|
||||
|
||||
struct r8a66597 {
|
||||
spinlock_t lock;
|
||||
unsigned long reg;
|
||||
void __iomem *reg;
|
||||
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
struct clk *clk;
|
||||
@ -127,7 +127,7 @@ struct r8a66597 {
|
||||
|
||||
static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
|
||||
{
|
||||
return inw(r8a66597->reg + offset);
|
||||
return ioread16(r8a66597->reg + offset);
|
||||
}
|
||||
|
||||
static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
||||
@ -135,7 +135,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
||||
unsigned char *buf,
|
||||
int len)
|
||||
{
|
||||
unsigned long fifoaddr = r8a66597->reg + offset;
|
||||
void __iomem *fifoaddr = r8a66597->reg + offset;
|
||||
unsigned int data;
|
||||
int i;
|
||||
|
||||
@ -144,7 +144,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
||||
|
||||
/* aligned buf case */
|
||||
if (len >= 4 && !((unsigned long)buf & 0x03)) {
|
||||
insl(fifoaddr, buf, len / 4);
|
||||
ioread32_rep(fifoaddr, buf, len / 4);
|
||||
buf += len & ~0x03;
|
||||
len &= 0x03;
|
||||
}
|
||||
@ -152,7 +152,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
||||
/* unaligned buf case */
|
||||
for (i = 0; i < len; i++) {
|
||||
if (!(i & 0x03))
|
||||
data = inl(fifoaddr);
|
||||
data = ioread32(fifoaddr);
|
||||
|
||||
buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
|
||||
}
|
||||
@ -161,7 +161,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
||||
|
||||
/* aligned buf case */
|
||||
if (len >= 2 && !((unsigned long)buf & 0x01)) {
|
||||
insw(fifoaddr, buf, len / 2);
|
||||
ioread16_rep(fifoaddr, buf, len / 2);
|
||||
buf += len & ~0x01;
|
||||
len &= 0x01;
|
||||
}
|
||||
@ -169,7 +169,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
||||
/* unaligned buf case */
|
||||
for (i = 0; i < len; i++) {
|
||||
if (!(i & 0x01))
|
||||
data = inw(fifoaddr);
|
||||
data = ioread16(fifoaddr);
|
||||
|
||||
buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
|
||||
}
|
||||
@ -179,7 +179,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
||||
static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
|
||||
unsigned long offset)
|
||||
{
|
||||
outw(val, r8a66597->reg + offset);
|
||||
iowrite16(val, r8a66597->reg + offset);
|
||||
}
|
||||
|
||||
static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
|
||||
@ -187,21 +187,21 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
|
||||
unsigned char *buf,
|
||||
int len)
|
||||
{
|
||||
unsigned long fifoaddr = r8a66597->reg + offset;
|
||||
void __iomem *fifoaddr = r8a66597->reg + offset;
|
||||
int adj = 0;
|
||||
int i;
|
||||
|
||||
if (r8a66597->pdata->on_chip) {
|
||||
/* 32-bit access only if buf is 32-bit aligned */
|
||||
if (len >= 4 && !((unsigned long)buf & 0x03)) {
|
||||
outsl(fifoaddr, buf, len / 4);
|
||||
iowrite32_rep(fifoaddr, buf, len / 4);
|
||||
buf += len & ~0x03;
|
||||
len &= 0x03;
|
||||
}
|
||||
} else {
|
||||
/* 16-bit access only if buf is 16-bit aligned */
|
||||
if (len >= 2 && !((unsigned long)buf & 0x01)) {
|
||||
outsw(fifoaddr, buf, len / 2);
|
||||
iowrite16_rep(fifoaddr, buf, len / 2);
|
||||
buf += len & ~0x01;
|
||||
len &= 0x01;
|
||||
}
|
||||
@ -216,7 +216,7 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
|
||||
}
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
outb(buf[i], fifoaddr + adj - (i & adj));
|
||||
iowrite8(buf[i], fifoaddr + adj - (i & adj));
|
||||
}
|
||||
|
||||
static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
|
||||
|
||||
@ -2404,7 +2404,7 @@ static int __init_or_module r8a66597_remove(struct platform_device *pdev)
|
||||
|
||||
del_timer_sync(&r8a66597->rh_timer);
|
||||
usb_remove_hcd(hcd);
|
||||
iounmap((void *)r8a66597->reg);
|
||||
iounmap(r8a66597->reg);
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
if (r8a66597->pdata->on_chip)
|
||||
clk_put(r8a66597->clk);
|
||||
@ -2496,7 +2496,7 @@ static int __devinit r8a66597_probe(struct platform_device *pdev)
|
||||
init_timer(&r8a66597->rh_timer);
|
||||
r8a66597->rh_timer.function = r8a66597_timer;
|
||||
r8a66597->rh_timer.data = (unsigned long)r8a66597;
|
||||
r8a66597->reg = (unsigned long)reg;
|
||||
r8a66597->reg = reg;
|
||||
|
||||
/* make sure no interrupts are pending */
|
||||
ret = r8a66597_clock_enable(r8a66597);
|
||||
|
||||
@ -112,7 +112,7 @@ struct r8a66597_root_hub {
|
||||
|
||||
struct r8a66597 {
|
||||
spinlock_t lock;
|
||||
unsigned long reg;
|
||||
void __iomem *reg;
|
||||
#ifdef CONFIG_HAVE_CLK
|
||||
struct clk *clk;
|
||||
#endif
|
||||
@ -170,67 +170,67 @@ static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
|
||||
|
||||
static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
|
||||
{
|
||||
return inw(r8a66597->reg + offset);
|
||||
return ioread16(r8a66597->reg + offset);
|
||||
}
|
||||
|
||||
static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
|
||||
unsigned long offset, u16 *buf,
|
||||
int len)
|
||||
{
|
||||
unsigned long fifoaddr = r8a66597->reg + offset;
|
||||
void __iomem *fifoaddr = r8a66597->reg + offset;
|
||||
unsigned long count;
|
||||
|
||||
if (r8a66597->pdata->on_chip) {
|
||||
count = len / 4;
|
||||
insl(fifoaddr, buf, count);
|
||||
ioread32_rep(fifoaddr, buf, count);
|
||||
|
||||
if (len & 0x00000003) {
|
||||
unsigned long tmp = inl(fifoaddr);
|
||||
unsigned long tmp = ioread32(fifoaddr);
|
||||
memcpy((unsigned char *)buf + count * 4, &tmp,
|
||||
len & 0x03);
|
||||
}
|
||||
} else {
|
||||
len = (len + 1) / 2;
|
||||
insw(fifoaddr, buf, len);
|
||||
ioread16_rep(fifoaddr, buf, len);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
|
||||
unsigned long offset)
|
||||
{
|
||||
outw(val, r8a66597->reg + offset);
|
||||
iowrite16(val, r8a66597->reg + offset);
|
||||
}
|
||||
|
||||
static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
|
||||
unsigned long offset, u16 *buf,
|
||||
int len)
|
||||
{
|
||||
unsigned long fifoaddr = r8a66597->reg + offset;
|
||||
void __iomem *fifoaddr = r8a66597->reg + offset;
|
||||
unsigned long count;
|
||||
unsigned char *pb;
|
||||
int i;
|
||||
|
||||
if (r8a66597->pdata->on_chip) {
|
||||
count = len / 4;
|
||||
outsl(fifoaddr, buf, count);
|
||||
iowrite32_rep(fifoaddr, buf, count);
|
||||
|
||||
if (len & 0x00000003) {
|
||||
pb = (unsigned char *)buf + count * 4;
|
||||
for (i = 0; i < (len & 0x00000003); i++) {
|
||||
if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
|
||||
outb(pb[i], fifoaddr + i);
|
||||
iowrite8(pb[i], fifoaddr + i);
|
||||
else
|
||||
outb(pb[i], fifoaddr + 3 - i);
|
||||
iowrite8(pb[i], fifoaddr + 3 - i);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
int odd = len & 0x0001;
|
||||
|
||||
len = len / 2;
|
||||
outsw(fifoaddr, buf, len);
|
||||
ioread16_rep(fifoaddr, buf, len);
|
||||
if (unlikely(odd)) {
|
||||
buf = &buf[len];
|
||||
outb((unsigned char)*buf, fifoaddr);
|
||||
iowrite8((unsigned char)*buf, fifoaddr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -991,13 +991,13 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
|
||||
priv->ch[j].lcdc = priv;
|
||||
memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
|
||||
|
||||
error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
|
||||
error = sh_mobile_lcdc_check_interface(&priv->ch[j]);
|
||||
if (error) {
|
||||
dev_err(&pdev->dev, "unsupported interface type\n");
|
||||
goto err1;
|
||||
}
|
||||
init_waitqueue_head(&priv->ch[i].frame_end_wait);
|
||||
init_completion(&priv->ch[i].vsync_completion);
|
||||
init_waitqueue_head(&priv->ch[j].frame_end_wait);
|
||||
init_completion(&priv->ch[j].vsync_completion);
|
||||
priv->ch[j].pan_offset = 0;
|
||||
|
||||
switch (pdata->ch[i].chan) {
|
||||
|
||||
@ -14,6 +14,9 @@
|
||||
#ifndef __SH_MMCIF_H__
|
||||
#define __SH_MMCIF_H__
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
/*
|
||||
* MMCIF : CE_CLK_CTRL [19:16]
|
||||
* 1000 : Peripheral clock / 512
|
||||
@ -36,4 +39,162 @@ struct sh_mmcif_plat_data {
|
||||
u32 ocr;
|
||||
};
|
||||
|
||||
#define MMCIF_CE_CMD_SET 0x00000000
|
||||
#define MMCIF_CE_ARG 0x00000008
|
||||
#define MMCIF_CE_ARG_CMD12 0x0000000C
|
||||
#define MMCIF_CE_CMD_CTRL 0x00000010
|
||||
#define MMCIF_CE_BLOCK_SET 0x00000014
|
||||
#define MMCIF_CE_CLK_CTRL 0x00000018
|
||||
#define MMCIF_CE_BUF_ACC 0x0000001C
|
||||
#define MMCIF_CE_RESP3 0x00000020
|
||||
#define MMCIF_CE_RESP2 0x00000024
|
||||
#define MMCIF_CE_RESP1 0x00000028
|
||||
#define MMCIF_CE_RESP0 0x0000002C
|
||||
#define MMCIF_CE_RESP_CMD12 0x00000030
|
||||
#define MMCIF_CE_DATA 0x00000034
|
||||
#define MMCIF_CE_INT 0x00000040
|
||||
#define MMCIF_CE_INT_MASK 0x00000044
|
||||
#define MMCIF_CE_HOST_STS1 0x00000048
|
||||
#define MMCIF_CE_HOST_STS2 0x0000004C
|
||||
#define MMCIF_CE_VERSION 0x0000007C
|
||||
|
||||
extern inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
|
||||
{
|
||||
return readl(addr + reg);
|
||||
}
|
||||
|
||||
extern inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
|
||||
{
|
||||
writel(val, addr + reg);
|
||||
}
|
||||
|
||||
#define SH_MMCIF_BBS 512 /* boot block size */
|
||||
|
||||
extern inline void sh_mmcif_boot_cmd_send(void __iomem *base,
|
||||
unsigned long cmd, unsigned long arg)
|
||||
{
|
||||
sh_mmcif_writel(base, MMCIF_CE_INT, 0);
|
||||
sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
|
||||
sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
|
||||
}
|
||||
|
||||
extern inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
|
||||
{
|
||||
unsigned long tmp;
|
||||
int cnt;
|
||||
|
||||
for (cnt = 0; cnt < 1000000; cnt++) {
|
||||
tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
|
||||
if (tmp & mask) {
|
||||
sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
extern inline int sh_mmcif_boot_cmd(void __iomem *base,
|
||||
unsigned long cmd, unsigned long arg)
|
||||
{
|
||||
sh_mmcif_boot_cmd_send(base, cmd, arg);
|
||||
return sh_mmcif_boot_cmd_poll(base, 0x00010000);
|
||||
}
|
||||
|
||||
extern inline int sh_mmcif_boot_do_read_single(void __iomem *base,
|
||||
unsigned int block_nr,
|
||||
unsigned long *buf)
|
||||
{
|
||||
int k;
|
||||
|
||||
/* CMD13 - Status */
|
||||
sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
|
||||
|
||||
if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
|
||||
return -1;
|
||||
|
||||
/* CMD17 - Read */
|
||||
sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
|
||||
if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
|
||||
return -1;
|
||||
|
||||
for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
|
||||
buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
extern inline int sh_mmcif_boot_do_read(void __iomem *base,
|
||||
unsigned long first_block,
|
||||
unsigned long nr_blocks,
|
||||
void *buf)
|
||||
{
|
||||
unsigned long k;
|
||||
int ret = 0;
|
||||
|
||||
/* CMD16 - Set the block size */
|
||||
sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
|
||||
|
||||
for (k = 0; !ret && k < nr_blocks; k++)
|
||||
ret = sh_mmcif_boot_do_read_single(base, first_block + k,
|
||||
buf + (k * SH_MMCIF_BBS));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
extern inline void sh_mmcif_boot_init(void __iomem *base)
|
||||
{
|
||||
unsigned long tmp;
|
||||
|
||||
/* reset */
|
||||
tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);
|
||||
sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | 0x80000000);
|
||||
sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & ~0x80000000);
|
||||
|
||||
/* byte swap */
|
||||
sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, 0x00010000);
|
||||
|
||||
/* Set block size in MMCIF hardware */
|
||||
sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
|
||||
|
||||
/* Enable the clock, set it to Bus clock/256 (about 325Khz)*/
|
||||
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01072fff);
|
||||
|
||||
/* CMD0 */
|
||||
sh_mmcif_boot_cmd(base, 0x00000040, 0);
|
||||
|
||||
/* CMD1 - Get OCR */
|
||||
do {
|
||||
sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
|
||||
} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
|
||||
!= 0x80000000);
|
||||
|
||||
/* CMD2 - Get CID */
|
||||
sh_mmcif_boot_cmd(base, 0x02806040, 0);
|
||||
|
||||
/* CMD3 - Set card relative address */
|
||||
sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
|
||||
}
|
||||
|
||||
extern inline void sh_mmcif_boot_slurp(void __iomem *base,
|
||||
unsigned char *buf,
|
||||
unsigned long no_bytes)
|
||||
{
|
||||
unsigned long tmp;
|
||||
|
||||
/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
|
||||
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
|
||||
|
||||
/* CMD9 - Get CSD */
|
||||
sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
|
||||
|
||||
/* CMD7 - Select the card */
|
||||
sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
|
||||
|
||||
tmp = no_bytes / SH_MMCIF_BBS;
|
||||
tmp += (no_bytes % SH_MMCIF_BBS) ? 1 : 0;
|
||||
|
||||
sh_mmcif_boot_do_read(base, 512, tmp, buf);
|
||||
}
|
||||
|
||||
#endif /* __SH_MMCIF_H__ */
|
||||
|
||||
@ -2,9 +2,7 @@
|
||||
#define __LINUX_SERIAL_SCI_H
|
||||
|
||||
#include <linux/serial_core.h>
|
||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||
#include <asm/dmaengine.h>
|
||||
#endif
|
||||
#include <linux/sh_dma.h>
|
||||
|
||||
/*
|
||||
* Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user