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drm/i915/gvt: mark symbols static where possible
Mark all local functions & variables as static. Signed-off-by: Du, Changbin <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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@ -480,8 +480,8 @@ struct parser_exec_state {
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#define gmadr_dw_number(s) \
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(s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
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unsigned long bypass_scan_mask = 0;
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bool bypass_batch_buffer_scan = true;
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static unsigned long bypass_scan_mask = 0;
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static bool bypass_batch_buffer_scan = true;
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/* ring ALL, type = 0 */
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static struct sub_op_bits sub_op_mi[] = {
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@ -960,7 +960,7 @@ struct cmd_interrupt_event {
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int mi_user_interrupt;
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};
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struct cmd_interrupt_event cmd_interrupt_events[] = {
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static struct cmd_interrupt_event cmd_interrupt_events[] = {
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[RCS] = {
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.pipe_control_notify = RCS_PIPE_CONTROL,
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.mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
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@ -120,7 +120,7 @@ static unsigned char virtual_dp_monitor_edid[] = {
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#define DPCD_HEADER_SIZE 0xb
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u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
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static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
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0x11, 0x0a, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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};
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@ -623,7 +623,7 @@ static int prepare_mm(struct intel_vgpu_workload *workload)
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(list_empty(q) ? NULL : container_of(q->prev, \
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struct intel_vgpu_workload, list))
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bool submit_context(struct intel_vgpu *vgpu, int ring_id,
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static bool submit_context(struct intel_vgpu *vgpu, int ring_id,
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struct execlist_ctx_descriptor_format *desc,
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bool emulate_schedule_in)
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{
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@ -1921,7 +1921,7 @@ int intel_vgpu_emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
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return ret;
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}
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bool intel_gvt_create_scratch_page(struct intel_vgpu *vgpu)
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static bool create_scratch_page(struct intel_vgpu *vgpu)
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{
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struct intel_vgpu_gtt *gtt = &vgpu->gtt;
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void *p;
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@ -1955,7 +1955,7 @@ bool intel_gvt_create_scratch_page(struct intel_vgpu *vgpu)
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return 0;
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}
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void intel_gvt_release_scratch_page(struct intel_vgpu *vgpu)
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static void release_scratch_page(struct intel_vgpu *vgpu)
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{
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if (vgpu->gtt.scratch_page != NULL) {
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__free_page(vgpu->gtt.scratch_page);
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@ -1995,7 +1995,7 @@ int intel_vgpu_init_gtt(struct intel_vgpu *vgpu)
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gtt->ggtt_mm = ggtt_mm;
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intel_gvt_create_scratch_page(vgpu);
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create_scratch_page(vgpu);
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return 0;
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}
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@ -2015,7 +2015,7 @@ void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu)
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struct intel_vgpu_mm *mm;
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ppgtt_free_all_shadow_page(vgpu);
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intel_gvt_release_scratch_page(vgpu);
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release_scratch_page(vgpu);
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list_for_each_safe(pos, n, &vgpu->gtt.mm_list_head) {
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mm = container_of(pos, struct intel_vgpu_mm, list);
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@ -50,7 +50,7 @@
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static void update_upstream_irq(struct intel_vgpu *vgpu,
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struct intel_gvt_irq_info *info);
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const char * const irq_name[INTEL_GVT_EVENT_MAX] = {
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static const char * const irq_name[INTEL_GVT_EVENT_MAX] = {
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[RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT",
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[RCS_DEBUG] = "Render EU debug from SVG",
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[RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status",
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@ -236,7 +236,7 @@ static void tbs_sched_stop_schedule(struct intel_vgpu *vgpu)
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list_del_init(&vgpu_data->list);
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}
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struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
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static struct intel_gvt_sched_policy_ops tbs_schedule_ops = {
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.init = tbs_sched_init,
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.clean = tbs_sched_clean,
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.init_vgpu = tbs_sched_init_vgpu,
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@ -41,7 +41,8 @@
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#define RING_CTX_OFF(x) \
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offsetof(struct execlist_ring_context, x)
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void set_context_pdp_root_pointer(struct execlist_ring_context *ring_context,
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static void set_context_pdp_root_pointer(
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struct execlist_ring_context *ring_context,
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u32 pdp[8])
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{
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struct execlist_mmio_pair *pdp_pair = &ring_context->pdp3_UDW;
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