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clk: bcm2835: divider value has to be 1 or more

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Current clamping of a normal divider allows a value < 1 to be valid.

A divider of < 1 would actually only be possible if we had a PLL...

So this patch clamps the divider to 1.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Martin Sperl 2016-02-29 11:39:20 +00:00 committed by Eric Anholt
parent ec36a5c668
commit 997f16bd5d
1 changed files with 3 additions and 2 deletions
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5
drivers/clk/bcm/clk-bcm2835.c
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@ -1190,8 +1190,9 @@ static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
div += unused_frac_mask + 1; div += unused_frac_mask + 1;
div &= ~unused_frac_mask; div &= ~unused_frac_mask;
/* Clamp to the limits. */ /* clamp to min divider of 1 */
div = max(div, unused_frac_mask + 1); div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS);
/* clamp to the highest possible fractional divider */
div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
CM_DIV_FRAC_BITS - data->frac_bits)); CM_DIV_FRAC_BITS - data->frac_bits));