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ARM: sh7372: fix cache clean / invalidate order

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According to the Cortex A8 TRM the L2 cache should be first cleaned and
then disabled. Fix the swapped order on sh7372.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Guennadi Liakhovetski 2012-12-28 12:32:54 +01:00 committed by Simon Horman
parent 529a7b3235
commit 9916152438
1 changed files with 7 additions and 5 deletions
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12
arch/arm/mach-shmobile/sleep-sh7372.S
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@ -59,16 +59,18 @@ sh7372_do_idle_sysc:
mcr p15, 0, r0, c1, c0, 0
isb
/*
* Clean and invalidate data cache again.
*/
ldr r1, kernel_flush
blx r1
/* disable L2 cache in the aux control register */
mrc p15, 0, r10, c1, c0, 1
bic r10, r10, #2
mcr p15, 0, r10, c1, c0, 1
isb
/*
* Invalidate data cache again.
*/
ldr r1, kernel_flush
blx r1
/*
* The kernel doesn't interwork: v7_flush_dcache_all in particluar will
* always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.