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Merge branch 'marvell-phy-refactor-and-cleanup'
Andrew Lunn says: ==================== More Marvell PHY refactoring and cleanup Consolidate more duplicated code into helpers, make use of core helpers, move code into a helper for later adding functionality to add marvell PHYs, etc. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
98c13bb750
@ -55,43 +55,35 @@
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#define MII_M1011_IMASK_INIT 0x6400
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#define MII_M1011_IMASK_CLEAR 0x0000
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#define MII_M1011_PHY_SCR 0x10
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#define MII_M1011_PHY_SCR_MDI 0x0000
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#define MII_M1011_PHY_SCR_MDI_X 0x0020
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#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
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#define MII_M1145_PHY_EXT_SR 0x1b
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#define MII_M1145_PHY_EXT_CR 0x14
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#define MII_M1145_RGMII_RX_DELAY 0x0080
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#define MII_M1145_RGMII_TX_DELAY 0x0002
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#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
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#define MII_M1145_HWCFG_MODE_MASK 0xf
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#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
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#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
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#define MII_M1145_HWCFG_MODE_MASK 0xf
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#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
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#define MII_M1011_PHY_SCR 0x10
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#define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
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#define MII_M1011_PHY_SCR_DOWNSHIFT_SHIFT 12
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#define MII_M1011_PHY_SRC_DOWNSHIFT_MASK 0x7800
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#define MII_M1011_PHY_SCR_MDI (0x0 << 5)
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#define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
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#define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
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#define MII_M1111_PHY_LED_CONTROL 0x18
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#define MII_M1111_PHY_LED_DIRECT 0x4100
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#define MII_M1111_PHY_LED_COMBINE 0x411c
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#define MII_M1111_PHY_EXT_CR 0x14
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#define MII_M1111_RX_DELAY 0x80
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#define MII_M1111_TX_DELAY 0x2
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#define MII_M1111_RGMII_RX_DELAY BIT(7)
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#define MII_M1111_RGMII_TX_DELAY BIT(1)
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#define MII_M1111_PHY_EXT_SR 0x1b
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#define MII_M1111_HWCFG_MODE_MASK 0xf
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#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
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#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
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#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
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#define MII_M1111_HWCFG_MODE_RTBI 0x7
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#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
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#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
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#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
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#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
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#define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
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#define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
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#define MII_88E1121_PHY_MSCR_REG 21
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#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
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#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
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#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
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#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(BIT(5) || BIT(4)))
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#define MII_88E1121_MISC_TEST 0x1a
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#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
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@ -108,24 +100,24 @@
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#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
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/* Copper Specific Interrupt Enable Register */
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#define MII_88E1318S_PHY_CSIER 0x12
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#define MII_88E1318S_PHY_CSIER 0x12
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/* WOL Event Interrupt Enable */
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#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
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#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
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/* LED Timer Control Register */
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#define MII_88E1318S_PHY_LED_TCR 0x12
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#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
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#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
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#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
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#define MII_88E1318S_PHY_LED_TCR 0x12
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#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
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#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
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#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
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/* Magic Packet MAC address registers */
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#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
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#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
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#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
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#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
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#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
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#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
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#define MII_88E1318S_PHY_WOL_CTRL 0x10
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#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
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#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
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#define MII_88E1318S_PHY_WOL_CTRL 0x10
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#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
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#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
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#define MII_88E1121_PHY_LED_CTRL 16
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#define MII_88E1121_PHY_LED_DEF 0x0030
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@ -138,8 +130,6 @@
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#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
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#define MII_M1011_PHY_STATUS_LINK 0x0400
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#define MII_M1116R_CONTROL_REG_MAC 21
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#define MII_88E3016_PHY_SPEC_CTRL 0x10
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#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
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#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
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@ -152,7 +142,7 @@
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#define LPA_FIBER_1000HALF 0x40
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#define LPA_FIBER_1000FULL 0x20
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#define LPA_PAUSE_FIBER 0x180
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#define LPA_PAUSE_FIBER 0x180
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#define LPA_PAUSE_ASYM_FIBER 0x100
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#define ADVERTISE_FIBER_1000HALF 0x40
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@ -274,6 +264,23 @@ static int marvell_set_polarity(struct phy_device *phydev, int polarity)
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return 0;
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}
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static int marvell_set_downshift(struct phy_device *phydev, bool enable,
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u8 retries)
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{
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int reg;
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reg = phy_read(phydev, MII_M1011_PHY_SCR);
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if (reg < 0)
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return reg;
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reg &= MII_M1011_PHY_SRC_DOWNSHIFT_MASK;
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reg |= ((retries - 1) << MII_M1011_PHY_SCR_DOWNSHIFT_SHIFT);
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if (enable)
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reg |= MII_M1011_PHY_SCR_DOWNSHIFT_EN;
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return phy_write(phydev, MII_M1011_PHY_SCR, reg);
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}
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static int marvell_config_aneg(struct phy_device *phydev)
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{
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int err;
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@ -292,17 +299,11 @@ static int marvell_config_aneg(struct phy_device *phydev)
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return err;
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if (phydev->autoneg != AUTONEG_ENABLE) {
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int bmcr;
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/* A write to speed/duplex bits (that is performed by
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* genphy_config_aneg() call above) must be followed by
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* a software reset. Otherwise, the write has no effect.
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*/
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bmcr = phy_read(phydev, MII_BMCR);
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if (bmcr < 0)
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return bmcr;
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err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
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err = genphy_soft_reset(phydev);
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if (err < 0)
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return err;
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}
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@ -318,8 +319,7 @@ static int m88e1101_config_aneg(struct phy_device *phydev)
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* that certain registers get written in order
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* to restart autonegotiation
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*/
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err = phy_write(phydev, MII_BMCR, BMCR_RESET);
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err = genphy_soft_reset(phydev);
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if (err < 0)
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return err;
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@ -354,7 +354,7 @@ static int m88e1111_config_aneg(struct phy_device *phydev)
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* that certain registers get written in order
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* to restart autonegotiation
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*/
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err = phy_write(phydev, MII_BMCR, BMCR_RESET);
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err = genphy_soft_reset(phydev);
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err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
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if (err < 0)
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@ -370,17 +370,11 @@ static int m88e1111_config_aneg(struct phy_device *phydev)
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return err;
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if (phydev->autoneg != AUTONEG_ENABLE) {
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int bmcr;
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/* A write to speed/duplex bits (that is performed by
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* genphy_config_aneg() call above) must be followed by
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* a software reset. Otherwise, the write has no effect.
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*/
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bmcr = phy_read(phydev, MII_BMCR);
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if (bmcr < 0)
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return bmcr;
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err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
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err = genphy_soft_reset(phydev);
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if (err < 0)
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return err;
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}
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@ -466,7 +460,7 @@ static int marvell_of_reg_init(struct phy_device *phydev)
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}
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#endif /* CONFIG_OF_MDIO */
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static int m88e1121_config_aneg(struct phy_device *phydev)
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static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
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{
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int err, oldpage, mscr;
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@ -474,31 +468,45 @@ static int m88e1121_config_aneg(struct phy_device *phydev)
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if (oldpage < 0)
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return oldpage;
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mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG);
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if (mscr < 0) {
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err = mscr;
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goto out;
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}
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mscr &= MII_88E1121_PHY_MSCR_DELAY_MASK;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
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MII_88E1121_PHY_MSCR_TX_DELAY);
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else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
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else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
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err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
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out:
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marvell_set_page(phydev, oldpage);
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return err;
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}
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static int m88e1121_config_aneg(struct phy_device *phydev)
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{
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int err = 0;
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if (phy_interface_is_rgmii(phydev)) {
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mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
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MII_88E1121_PHY_MSCR_DELAY_MASK;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
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MII_88E1121_PHY_MSCR_TX_DELAY);
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else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
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else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
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err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
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if (err < 0)
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err = m88e1121_config_aneg_rgmii_delays(phydev);
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if (err)
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return err;
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}
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marvell_set_page(phydev, oldpage);
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err = phy_write(phydev, MII_BMCR, BMCR_RESET);
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err = genphy_soft_reset(phydev);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_M1011_PHY_SCR,
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MII_M1011_PHY_SCR_AUTO_CROSS);
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err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
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if (err < 0)
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return err;
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@ -596,7 +604,7 @@ static int marvell_config_aneg_fiber(struct phy_device *phydev)
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if (changed == 0) {
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/* Advertisement hasn't changed, but maybe aneg was never on to
|
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* begin with? Or maybe phy was isolated?
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* begin with? Or maybe phy was isolated?
|
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*/
|
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int ctl = phy_read(phydev, MII_BMCR);
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|
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@ -653,12 +661,9 @@ static int marvell_config_init(struct phy_device *phydev)
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static int m88e1116r_config_init(struct phy_device *phydev)
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{
|
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int temp;
|
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int err;
|
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|
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temp = phy_read(phydev, MII_BMCR);
|
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temp |= BMCR_RESET;
|
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err = phy_write(phydev, MII_BMCR, temp);
|
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err = genphy_soft_reset(phydev);
|
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if (err < 0)
|
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return err;
|
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|
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@ -668,34 +673,21 @@ static int m88e1116r_config_init(struct phy_device *phydev)
|
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if (err < 0)
|
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return err;
|
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|
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temp = phy_read(phydev, MII_M1011_PHY_SCR);
|
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temp |= (7 << 12); /* max number of gigabit attempts */
|
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temp |= (1 << 11); /* enable downshift */
|
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temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
|
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err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
|
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err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
|
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if (err < 0)
|
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return err;
|
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|
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err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
|
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if (err < 0)
|
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return err;
|
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temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
|
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temp |= (1 << 5);
|
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temp |= (1 << 4);
|
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err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
|
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if (err < 0)
|
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return err;
|
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err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
|
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err = marvell_set_downshift(phydev, true, 8);
|
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if (err < 0)
|
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return err;
|
||||
|
||||
temp = phy_read(phydev, MII_BMCR);
|
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temp |= BMCR_RESET;
|
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err = phy_write(phydev, MII_BMCR, temp);
|
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err = m88e1121_config_aneg_rgmii_delays(phydev);
|
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if (err < 0)
|
||||
return err;
|
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|
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mdelay(500);
|
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err = genphy_soft_reset(phydev);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
return marvell_config_init(phydev);
|
||||
}
|
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@ -719,9 +711,29 @@ static int m88e3016_config_init(struct phy_device *phydev)
|
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return marvell_config_init(phydev);
|
||||
}
|
||||
|
||||
static int m88e1111_config_init_rgmii(struct phy_device *phydev)
|
||||
static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
|
||||
u16 mode,
|
||||
int fibre_copper_auto)
|
||||
{
|
||||
int temp;
|
||||
|
||||
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
|
||||
if (temp < 0)
|
||||
return temp;
|
||||
|
||||
temp &= ~(MII_M1111_HWCFG_MODE_MASK |
|
||||
MII_M1111_HWCFG_FIBER_COPPER_AUTO |
|
||||
MII_M1111_HWCFG_FIBER_COPPER_RES);
|
||||
temp |= mode;
|
||||
|
||||
if (fibre_copper_auto)
|
||||
temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
|
||||
|
||||
return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
|
||||
}
|
||||
|
||||
static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
|
||||
{
|
||||
int err;
|
||||
int temp;
|
||||
|
||||
temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
|
||||
@ -729,16 +741,24 @@ static int m88e1111_config_init_rgmii(struct phy_device *phydev)
|
||||
return temp;
|
||||
|
||||
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
|
||||
temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
|
||||
temp |= (MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY);
|
||||
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
|
||||
temp &= ~MII_M1111_TX_DELAY;
|
||||
temp |= MII_M1111_RX_DELAY;
|
||||
temp &= ~MII_M1111_RGMII_TX_DELAY;
|
||||
temp |= MII_M1111_RGMII_RX_DELAY;
|
||||
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
|
||||
temp &= ~MII_M1111_RX_DELAY;
|
||||
temp |= MII_M1111_TX_DELAY;
|
||||
temp &= ~MII_M1111_RGMII_RX_DELAY;
|
||||
temp |= MII_M1111_RGMII_TX_DELAY;
|
||||
}
|
||||
|
||||
err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
|
||||
return phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
|
||||
}
|
||||
|
||||
static int m88e1111_config_init_rgmii(struct phy_device *phydev)
|
||||
{
|
||||
int temp;
|
||||
int err;
|
||||
|
||||
err = m88e1111_config_init_rgmii_delays(phydev);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
@ -759,17 +779,11 @@ static int m88e1111_config_init_rgmii(struct phy_device *phydev)
|
||||
static int m88e1111_config_init_sgmii(struct phy_device *phydev)
|
||||
{
|
||||
int err;
|
||||
int temp;
|
||||
|
||||
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
|
||||
if (temp < 0)
|
||||
return temp;
|
||||
|
||||
temp &= ~(MII_M1111_HWCFG_MODE_MASK);
|
||||
temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
|
||||
temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
|
||||
|
||||
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
|
||||
err = m88e1111_config_init_hwcfg_mode(
|
||||
phydev,
|
||||
MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
|
||||
MII_M1111_HWCFG_FIBER_COPPER_AUTO);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
@ -780,48 +794,27 @@ static int m88e1111_config_init_sgmii(struct phy_device *phydev)
|
||||
static int m88e1111_config_init_rtbi(struct phy_device *phydev)
|
||||
{
|
||||
int err;
|
||||
int temp;
|
||||
|
||||
temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
|
||||
if (temp < 0)
|
||||
return temp;
|
||||
|
||||
temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
|
||||
err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
|
||||
if (err < 0)
|
||||
err = m88e1111_config_init_rgmii_delays(phydev);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
|
||||
if (temp < 0)
|
||||
return temp;
|
||||
|
||||
temp &= ~(MII_M1111_HWCFG_MODE_MASK |
|
||||
MII_M1111_HWCFG_FIBER_COPPER_RES);
|
||||
temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
|
||||
|
||||
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
|
||||
err = m88e1111_config_init_hwcfg_mode(
|
||||
phydev,
|
||||
MII_M1111_HWCFG_MODE_RTBI,
|
||||
MII_M1111_HWCFG_FIBER_COPPER_AUTO);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/* soft reset */
|
||||
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
|
||||
err = genphy_soft_reset(phydev);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
do
|
||||
temp = phy_read(phydev, MII_BMCR);
|
||||
while (temp & BMCR_RESET);
|
||||
|
||||
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
|
||||
if (temp < 0)
|
||||
return temp;
|
||||
|
||||
temp &= ~(MII_M1111_HWCFG_MODE_MASK |
|
||||
MII_M1111_HWCFG_FIBER_COPPER_RES);
|
||||
temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI |
|
||||
MII_M1111_HWCFG_FIBER_COPPER_AUTO;
|
||||
|
||||
return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
|
||||
return m88e1111_config_init_hwcfg_mode(
|
||||
phydev,
|
||||
MII_M1111_HWCFG_MODE_RTBI,
|
||||
MII_M1111_HWCFG_FIBER_COPPER_AUTO);
|
||||
}
|
||||
|
||||
static int m88e1111_config_init(struct phy_device *phydev)
|
||||
@ -850,7 +843,7 @@ static int m88e1111_config_init(struct phy_device *phydev)
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
return phy_write(phydev, MII_BMCR, BMCR_RESET);
|
||||
return genphy_soft_reset(phydev);
|
||||
}
|
||||
|
||||
static int m88e1121_config_init(struct phy_device *phydev)
|
||||
@ -912,12 +905,11 @@ static int m88e1118_config_aneg(struct phy_device *phydev)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
|
||||
err = genphy_soft_reset(phydev);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
err = phy_write(phydev, MII_M1011_PHY_SCR,
|
||||
MII_M1011_PHY_SCR_AUTO_CROSS);
|
||||
err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
@ -961,7 +953,7 @@ static int m88e1118_config_init(struct phy_device *phydev)
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
return phy_write(phydev, MII_BMCR, BMCR_RESET);
|
||||
return genphy_soft_reset(phydev);
|
||||
}
|
||||
|
||||
static int m88e1149_config_init(struct phy_device *phydev)
|
||||
@ -987,20 +979,15 @@ static int m88e1149_config_init(struct phy_device *phydev)
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
return phy_write(phydev, MII_BMCR, BMCR_RESET);
|
||||
return genphy_soft_reset(phydev);
|
||||
}
|
||||
|
||||
static int m88e1145_config_init_rgmii(struct phy_device *phydev)
|
||||
{
|
||||
int temp;
|
||||
int err;
|
||||
int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
|
||||
|
||||
if (temp < 0)
|
||||
return temp;
|
||||
|
||||
temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
|
||||
|
||||
err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
|
||||
err = m88e1111_config_init_rgmii_delays(phydev);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
@ -1032,16 +1019,9 @@ static int m88e1145_config_init_rgmii(struct phy_device *phydev)
|
||||
|
||||
static int m88e1145_config_init_sgmii(struct phy_device *phydev)
|
||||
{
|
||||
int temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
|
||||
|
||||
if (temp < 0)
|
||||
return temp;
|
||||
|
||||
temp &= ~MII_M1145_HWCFG_MODE_MASK;
|
||||
temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
|
||||
temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
|
||||
|
||||
return phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
|
||||
return m88e1111_config_init_hwcfg_mode(
|
||||
phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
|
||||
MII_M1111_HWCFG_FIBER_COPPER_AUTO);
|
||||
}
|
||||
|
||||
static int m88e1145_config_init(struct phy_device *phydev)
|
||||
@ -1515,7 +1495,7 @@ static void marvell_get_strings(struct phy_device *phydev, u8 *data)
|
||||
}
|
||||
|
||||
#ifndef UINT64_MAX
|
||||
#define UINT64_MAX (u64)(~((u64)0))
|
||||
#define UINT64_MAX (u64)(~((u64)0))
|
||||
#endif
|
||||
static u64 marvell_get_stat(struct phy_device *phydev, int i)
|
||||
{
|
||||
|
Loading…
Reference in New Issue
Block a user