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Merge series "ASoC: qcom: Add AudioReach support" from Srinivas Kandagatla <srinivas.kandagatla@linaro.org>:

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Hi Mark,

This version is a respin of v10 fixing a build error in 12/17 patch.

QCOM SoC relevant non-audio patches in this series has been merged into
the Qualcomm drivers-for-5.16 tree, as this series depends those patches
an immutable tag is available at:
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/20210927135559.738-6-srinivas.kandagatla@linaro.org

This patchset adds ASoC driver support to configure signal processing
framework ("AudioReach") which is integral part of Qualcomm next
generation audio SDK and will be deployed on upcoming Qualcomm chipsets.
It makes use of ASoC Topology to load graphs on to the DSP which is then
managed by APM (Audio Processing Manager) service to prepare/start/stop.

Here is simplified high-level block diagram of AudioReach:

 ___________________________________________________________
|                 CPU (Application Processor)               |
|  +---------+          +---------+         +----------+    |
|  |  q6apm  |          |  q6apm  |         |  q6apm   |    |
|  |   dais  | <------> |         | <-----> |lpass-dais|    |
|  +---------+          +---------+         +----------+    |
|                            ^  ^                           |
|                            |  |           +---------+     |
|  +---------+               v  +---------->|topology |     |
|  | q6prm   |          +---------+         |         |     |
|  |         |<-------->|   GPR   |         +---------+     |
|  +---------+          +---------+                         |
|       ^                    ^                              |
|       |                    |                              |
|  +----------+              |                              |
|  |   q6prm  |              |                              |
|  |lpass-clks|              |                              |
|  +----------+              |                              |
|____________________________|______________________________|
                             |
                             | RPMSG (IPC over GLINK)
 ____________________________|______________________________
|                            |                              |
|    +-----------------------+                              |
|    |                       |                              |
|    v                       v              q6 (Audio DSP)  |
|+-----+    +----------------------------------+            |
|| PRM |    | APM (Audio Processing Manager)   |            |
|+-----+    |  . Graph Management              |            |
|           |  . Command Handing               |            |
|           |  . Event Management              |            |
|           |  ...                             |            |
|           +----------------------------------+            |
|                            ^                              |
|____________________________|______________________________|
                             |
                             |   LPASS AIF
 ____________________________|______________________________
|                            |            Audio I/O         |
|                            v                              |
|    +--------------------------------------------------+   |
|    |                Audio devices                     |   |
|    | CODEC | HDMI-TX | PCM  | SLIMBUS | I2S |MI2S |...|   |
|    |                                                  |   |
|    +--------------------------------------------------+   |
|___________________________________________________________|

AudioReach has constructs of sub-graph, container and modules.
Each sub-graph can have N containers and each Container can have N Modules
and connections between them can be linear or non-linear.
An audio function can be realized with one or many connected
sub-graphs. There are also control/event paths between modules that can
be wired up while building graph to achieve various control mechanism
between modules. These concepts of Sub-Graph, Containers and Modules
are represented in ASoC topology.

Here is simple I2S graph with a Write Shared Memory and a
Volume control module within a single Subgraph (1) with one Container (1)
and 5 modules.

  ____________________________________________________________
 |                        Sub-Graph [1]                       |
 |  _______________________________________________________   |
 | |                       Container [1]                   |  |
 | | [WR_SH] -> [PCM DEC] -> [PCM CONV] -> [VOL]-> [I2S-EP]|  |
 | |_______________________________________________________|  |
 |____________________________________________________________|

For now this graph is split into two subgraphs to achieve dpcm like below:
 ________________________________________________    _________________
|                Sub-Graph [1]                   |  |  Sub-Graph [2]  |
|  ____________________________________________  |  |  _____________  |
| |              Container [1]                 | |  | |Container [2]| |
| | [WR_SH] -> [PCM DEC] -> [PCM CONV] -> [VOL]| |  | |   [I2S-EP]  | |
| |____________________________________________| |  | |_____________| |
|________________________________________________|  |_________________|

                                                      _________________
                                                    |  Sub-Graph [3]  |
                                                    |  _____________  |
                                                    | |Container [3]| |
                                                    | |  [DMA-EP]   | |
                                                    | |_____________| |
                                                    |_________________|

This patchset adds very minimal support for AudioReach which includes
supporting sub-graphs containing CODEC DMA ports and simple PCM
Decoder/Encoder and Logger Modules. Additional capabilities will
be built over time to expose features offered by AudioReach.

This patchset is Tested on SM8250 SoC based Qualcomm Robotics Platform RB5
and SM9250 MTP with WSA881X Smart Speaker Amplifiers, DMICs connected via
VA Macro and WCD938x Codec connected via TX and RX Macro and HDMI audio
via I2S.

First 10 Patches are mostly reorganization existing Old QDSP Audio
Framework code and bindings so that we could reuse them on AudioReach.

ASoC topology graphs for DragonBoard RB5 and SM8250 MTP are available at
https://git.linaro.org/people/srinivas.kandagatla/audioreach-topology.git/
and Qualcomm AudioReach DSP headers are available at:
https://source.codeaurora.org/quic/la/platform/vendor/opensource/arspf-headers

Note: There is one false positive warning in this patchset:
audioreach.c:80:45: warning: array of flexible structures

Thanks,
srini

Changes since v10:
- fix build error during arm64 defconfig build reported by Mark in 12/17 patch
for audioreach_tplg_init symbol

Srinivas Kandagatla (17):
  ASoC: dt-bindings: move LPASS dai related bindings out of q6afe
  ASoC: dt-bindings: move LPASS clocks related bindings out of q6afe
  ASoC: dt-bindings: rename q6afe.h to q6dsp-lpass-ports.h
  ASoC: qdsp6: q6afe-dai: move lpass audio ports to common file
  ASoC: qdsp6: q6afe-clocks: move audio-clocks to common file
  ASoC: dt-bindings: q6dsp: add q6apm-lpass-dai compatible
  ASoC: dt-bindings: lpass-clocks: add q6prm clocks compatible
  ASoC: dt-bindings: add q6apm digital audio stream bindings
  ASoC: qdsp6: audioreach: add basic pkt alloc support
  ASoC: qdsp6: audioreach: add q6apm support
  ASoC: qdsp6: audioreach: add module configuration command helpers
  ASoC: qdsp6: audioreach: add Kconfig and Makefile
  ASoC: qdsp6: audioreach: add topology support
  ASoC: qdsp6: audioreach: add q6apm-dai support
  ASoC: qdsp6: audioreach: add q6apm lpass dai support
  ASoC: qdsp6: audioreach: add q6prm support
  ASoC: qdsp6: audioreach: add support for q6prm-clocks

 .../devicetree/bindings/sound/qcom,q6afe.txt  |  181 ---
 .../bindings/sound/qcom,q6apm-dai.yaml        |   53 +
 .../sound/qcom,q6dsp-lpass-clocks.yaml        |   77 ++
 .../sound/qcom,q6dsp-lpass-ports.yaml         |  205 +++
 include/dt-bindings/sound/qcom,q6afe.h        |  203 +--
 .../sound/qcom,q6dsp-lpass-ports.h            |  208 +++
 include/uapi/sound/snd_ar_tokens.h            |  208 +++
 sound/soc/qcom/Kconfig                        |   22 +
 sound/soc/qcom/qdsp6/Makefile                 |   11 +-
 sound/soc/qcom/qdsp6/audioreach.c             | 1130 +++++++++++++++++
 sound/soc/qcom/qdsp6/audioreach.h             |  726 +++++++++++
 sound/soc/qcom/qdsp6/q6afe-clocks.c           |  187 +--
 sound/soc/qcom/qdsp6/q6afe-dai.c              |  687 +---------
 sound/soc/qcom/qdsp6/q6apm-dai.c              |  416 ++++++
 sound/soc/qcom/qdsp6/q6apm-lpass-dais.c       |  260 ++++
 sound/soc/qcom/qdsp6/q6apm.c                  |  822 ++++++++++++
 sound/soc/qcom/qdsp6/q6apm.h                  |  152 +++
 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c     |  186 +++
 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h     |   30 +
 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c      |  627 +++++++++
 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h      |   22 +
 sound/soc/qcom/qdsp6/q6prm-clocks.c           |   85 ++
 sound/soc/qcom/qdsp6/q6prm.c                  |  202 +++
 sound/soc/qcom/qdsp6/q6prm.h                  |   78 ++
 sound/soc/qcom/qdsp6/topology.c               | 1113 ++++++++++++++++
 25 files changed, 6664 insertions(+), 1227 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml
 create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml
 create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml
 create mode 100644 include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
 create mode 100644 include/uapi/sound/snd_ar_tokens.h
 create mode 100644 sound/soc/qcom/qdsp6/audioreach.c
 create mode 100644 sound/soc/qcom/qdsp6/audioreach.h
 create mode 100644 sound/soc/qcom/qdsp6/q6apm-dai.c
 create mode 100644 sound/soc/qcom/qdsp6/q6apm-lpass-dais.c
 create mode 100644 sound/soc/qcom/qdsp6/q6apm.c
 create mode 100644 sound/soc/qcom/qdsp6/q6apm.h
 create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c
 create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h
 create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c
 create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h
 create mode 100644 sound/soc/qcom/qdsp6/q6prm-clocks.c
 create mode 100644 sound/soc/qcom/qdsp6/q6prm.c
 create mode 100644 sound/soc/qcom/qdsp6/q6prm.h
 create mode 100644 sound/soc/qcom/qdsp6/topology.c

--
2.21.0
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Mark Brown 2021-10-26 20:00:39 +01:00
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31 changed files with 7165 additions and 1415 deletions
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134
Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt
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@ -1,134 +0,0 @@
Qualcomm APR (Asynchronous Packet Router) binding
This binding describes the Qualcomm APR. APR is a IPC protocol for
communication between Application processor and QDSP. APR is mainly
used for audio/voice services on the QDSP.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,apr-v<VERSION-NUMBER>", example "qcom,apr-v2"
- qcom,apr-domain
Usage: required
Value type: <u32>
Definition: Destination processor ID.
Possible values are :
1 - APR simulator
2 - PC
3 - MODEM
4 - ADSP
5 - APPS
6 - MODEM2
7 - APPS2
= APR SERVICES
Each subnode of the APR node represents service tied to this apr. The name
of the nodes are not important. The properties of these nodes are defined
by the individual bindings for the specific service
- All APR services MUST contain the following property:
- reg
Usage: required
Value type: <u32>
Definition: APR Service ID
Possible values are :
3 - DSP Core Service
4 - Audio Front End Service.
5 - Voice Stream Manager Service.
6 - Voice processing manager.
7 - Audio Stream Manager Service.
8 - Audio Device Manager Service.
9 - Multimode voice manager.
10 - Core voice stream.
11 - Core voice processor.
12 - Ultrasound stream manager.
13 - Listen stream manager.
- qcom,protection-domain
Usage: optional
Value type: <stringlist>
Definition: Must list the protection domain service name and path
that the particular apr service has a dependency on.
Possible values are :
"avs/audio", "msm/adsp/audio_pd".
"kernel/elf_loader", "msm/modem/wlan_pd".
"tms/servreg", "msm/adsp/audio_pd".
"tms/servreg", "msm/modem/wlan_pd".
"tms/servreg", "msm/slpi/sensor_pd".
= EXAMPLE
The following example represents a QDSP based sound card on a MSM8996 device
which uses apr as communication between Apps and QDSP.
apr {
compatible = "qcom,apr-v2";
qcom,apr-domain = <APR_DOMAIN_ADSP>;
apr-service@3 {
compatible = "qcom,q6core";
reg = <APR_SVC_ADSP_CORE>;
};
apr-service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
dais {
#sound-dai-cells = <1>;
dai@1 {
reg = <HDMI_RX>;
};
};
};
apr-service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
...
};
apr-service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
...
};
};
= EXAMPLE 2
The following example represents a QDSP based sound card with protection domain
dependencies specified. Here some of the apr services are dependent on services
running on protection domain hosted on ADSP/SLPI remote processors while others
have no such dependency.
apr {
compatible = "qcom,apr-v2";
qcom,glink-channels = "apr_audio_svc";
qcom,apr-domain = <APR_DOMAIN_ADSP>;
apr-service@3 {
compatible = "qcom,q6core";
reg = <APR_SVC_ADSP_CORE>;
};
q6afe: apr-service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
...
};
q6asm: apr-service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
qcom,protection-domain = "tms/servreg", "msm/slpi/sensor_pd";
...
};
q6adm: apr-service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
...
};
};

177
Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml Normal file
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@ -0,0 +1,177 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,apr.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm APR/GPR (Asynchronous/Generic Packet Router) binding
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
This binding describes the Qualcomm APR/GPR, APR/GPR is a IPC protocol for
communication between Application processor and QDSP. APR/GPR is mainly
used for audio/voice services on the QDSP.
properties:
compatible:
enum:
- qcom,apr-v2
- qcom,gpr
qcom,apr-domain:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3, 4, 5, 6, 7]
description:
Selects the processor domain for apr
1 = APR simulator
2 = PC Domain
3 = Modem Domain
4 = ADSP Domain
5 = Application processor Domain
6 = Modem2 Domain
7 = Application Processor2 Domain
deprecated: true
qcom,domain:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 7
description:
Selects the processor domain for apr
1 = APR simulator
2 = PC Domain
3 = Modem Domain
4 = ADSP Domain
5 = Application processor Domain
6 = Modem2 Domain
7 = Application Processor2 Domain
Selects the processor domain for gpr
1 = Modem Domain
2 = Audio DSP Domain
3 = Application Processor Domain
'#address-cells':
const: 1
'#size-cells':
const: 0
#APR/GPR Services
patternProperties:
"^service@[1-9a-d]$":
type: object
description:
APR/GPR node's client devices use subnodes for desired static port services.
properties:
compatible:
enum:
- qcom,q6core
- qcom,q6asm
- qcom,q6afe
- qcom,q6adm
- qcom,q6apm
- qcom,q6prm
reg:
minimum: 1
maximum: 13
description:
APR Service ID
3 = DSP Core Service
4 = Audio Front End Service.
5 = Voice Stream Manager Service.
6 = Voice processing manager.
7 = Audio Stream Manager Service.
8 = Audio Device Manager Service.
9 = Multimode voice manager.
10 = Core voice stream.
11 = Core voice processor.
12 = Ultrasound stream manager.
13 = Listen stream manager.
GPR Service ID
1 = Audio Process Manager Service
2 = Proxy Resource Manager Service.
3 = AMDB Service.
4 = Voice processing manager.
qcom,protection-domain:
$ref: /schemas/types.yaml#/definitions/string-array
description: protection domain service name and path for apr service
possible values are
"avs/audio", "msm/adsp/audio_pd".
"kernel/elf_loader", "msm/modem/wlan_pd".
"tms/servreg", "msm/adsp/audio_pd".
"tms/servreg", "msm/modem/wlan_pd".
"tms/servreg", "msm/slpi/sensor_pd".
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^.*@[0-9a-f]+$":
type: object
description:
Service based devices like clock controllers or digital audio interfaces.
additionalProperties: false
required:
- compatible
- qcom,domain
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/qcom,apr.h>
apr {
compatible = "qcom,apr-v2";
qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
q6core: service@3 {
compatible = "qcom,q6core";
reg = <APR_SVC_ADSP_CORE>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
};
q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
};
q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
};
q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
};
};
- |
#include <dt-bindings/soc/qcom,gpr.h>
gpr {
compatible = "qcom,gpr";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
};
};

181
Documentation/devicetree/bindings/sound/qcom,q6afe.txt
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@ -12,190 +12,9 @@ used by all apr services. Must contain the following properties.
from DSP.
example "qcom,q6afe"
= AFE DAIs (Digital Audio Interface)
"dais" subnode of the AFE node. It represents afe dais, each afe dai is a
subnode of "dais" representing board specific dai setup.
"dais" node should have following properties followed by dai children.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,q6afe-dais"
- #sound-dai-cells
Usage: required
Value type: <u32>
Definition: Must be 1
- #address-cells
Usage: required
Value type: <u32>
Definition: Must be 1
- #size-cells
Usage: required
Value type: <u32>
Definition: Must be 0
== AFE DAI is subnode of "dais" and represent a dai, it includes board specific
configuration of each dai. Must contain the following properties.
- reg
Usage: required
Value type: <u32>
Definition: Must be dai id
- qcom,sd-lines
Usage: required for mi2s interface
Value type: <prop-encoded-array>
Definition: Must be list of serial data lines used by this dai.
should be one or more of the 0-3 sd lines.
- qcom,tdm-sync-mode:
Usage: required for tdm interface
Value type: <prop-encoded-array>
Definition: Synchronization mode.
0 - Short sync bit mode
1 - Long sync mode
2 - Short sync slot mode
- qcom,tdm-sync-src:
Usage: required for tdm interface
Value type: <prop-encoded-array>
Definition: Synchronization source.
0 - External source
1 - Internal source
- qcom,tdm-data-out:
Usage: required for tdm interface
Value type: <prop-encoded-array>
Definition: Data out signal to drive with other masters.
0 - Disable
1 - Enable
- qcom,tdm-invert-sync:
Usage: required for tdm interface
Value type: <prop-encoded-array>
Definition: Invert the sync.
0 - Normal
1 - Invert
- qcom,tdm-data-delay:
Usage: required for tdm interface
Value type: <prop-encoded-array>
Definition: Number of bit clock to delay data
with respect to sync edge.
0 - 0 bit clock cycle
1 - 1 bit clock cycle
2 - 2 bit clock cycle
- qcom,tdm-data-align:
Usage: required for tdm interface
Value type: <prop-encoded-array>
Definition: Indicate how data is packed
within the slot. For example, 32 slot width in case of
sample bit width is 24.
0 - MSB
1 - LSB
= AFE CLOCKSS
"clocks" subnode of the AFE node. It represents q6afe clocks
"clocks" node should have following properties.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,q6afe-clocks"
- #clock-cells:
Usage: required
Value type: <u32>
Definition: Must be 2. Clock Id followed by
below valid clock coupling attributes.
1 - for no coupled clock
2 - for dividend of the coupled clock
3 - for divisor of the coupled clock
4 - for inverted and no couple clock
= EXAMPLE
apr-service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
dais {
compatible = "qcom,q6afe-dais";
#sound-dai-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
dai@1 {
reg = <HDMI_RX>;
};
dai@24 {
reg = <PRIMARY_TDM_RX_0>;
qcom,tdm-sync-mode = <1>:
qcom,tdm-sync-src = <1>;
qcom,tdm-data-out = <0>;
qcom,tdm-invert-sync = <1>;
qcom,tdm-data-delay = <1>;
qcom,tdm-data-align = <0>;
};
dai@25 {
reg = <PRIMARY_TDM_TX_0>;
qcom,tdm-sync-mode = <1>:
qcom,tdm-sync-src = <1>;
qcom,tdm-data-out = <0>;
qcom,tdm-invert-sync = <1>;
qcom,tdm-data-delay <1>:
qcom,tdm-data-align = <0>;
};
dai@16 {
reg = <PRIMARY_MI2S_RX>;
qcom,sd-lines = <0 2>;
};
dai@17 {
reg = <PRIMARY_MI2S_TX>;
qcom,sd-lines = <1>;
};
dai@18 {
reg = <SECONDARY_MI2S_RX>;
qcom,sd-lines = <0 3>;
};
dai@19 {
reg = <SECONDARY_MI2S_TX>;
qcom,sd-lines = <1>;
};
dai@20 {
reg = <TERTIARY_MI2S_RX>;
qcom,sd-lines = <1 3>;
};
dai@21 {
reg = <TERTIARY_MI2S_TX>;
qcom,sd-lines = <0>;
};
dai@22 {
reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <0>;
};
dai@23 {
reg = <QUATERNARY_MI2S_TX>;
qcom,sd-lines = <1>;
};
};
clocks {
compatible = "qcom,q6afe-clocks";
#clock-cells = <2>;
};
};

53
Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml Normal file
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@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/sound/qcom,q6apm-dai.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Audio Process Manager Digital Audio Interfaces binding
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
This binding describes the Qualcomm APM DAIs in DSP
properties:
compatible:
const: qcom,q6apm-dais
reg:
maxItems: 1
iommus:
maxItems: 1
required:
- compatible
- iommus
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/qcom,gpr.h>
gpr {
compatible = "qcom,gpr";
#address-cells = <1>;
#size-cells = <0>;
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
service@1 {
compatible = "qcom,q6apm";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
apm-dai@1 {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1801 0x0>;
reg = <1>;
};
};
};

77
Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml Normal file
View File

@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-clocks.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm DSP LPASS Clock Controller binding
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
This binding describes the Qualcomm DSP Clock Controller
properties:
compatible:
enum:
- qcom,q6afe-clocks
- qcom,q6prm-lpass-clocks
reg:
maxItems: 1
'#clock-cells':
const: 2
description:
Clock Id is followed by clock coupling attributes.
1 = for no coupled clock
2 = for dividend of the coupled clock
3 = for divisor of the coupled clock
4 = for inverted and no couple clock
required:
- compatible
- reg
- "#clock-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/sound/qcom,q6afe.h>
apr {
#address-cells = <1>;
#size-cells = <0>;
apr-service@4 {
reg = <APR_SVC_AFE>;
#address-cells = <1>;
#size-cells = <0>;
clock-controller@2 {
compatible = "qcom,q6afe-clocks";
reg = <2>;
#clock-cells = <2>;
};
};
};
- |
#include <dt-bindings/soc/qcom,gpr.h>
gpr {
compatible = "qcom,gpr";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
service@2 {
reg = <GPR_PRM_MODULE_IID>;
compatible = "qcom,q6prm";
#address-cells = <1>;
#size-cells = <0>;
clock-controller@2 {
compatible = "qcom,q6prm-lpass-clocks";
reg = <2>;
#clock-cells = <2>;
};
};
};

205
Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml Normal file
View File

@ -0,0 +1,205 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-ports.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm DSP LPASS(Low Power Audio SubSystem) Audio Ports binding
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
This binding describes the Qualcomm DSP LPASS Audio ports
properties:
compatible:
enum:
- qcom,q6afe-dais
- qcom,q6apm-lpass-dais
reg:
maxItems: 1
'#sound-dai-cells':
const: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
#Digital Audio Interfaces
patternProperties:
'^dai@[0-9]+$':
type: object
description:
Q6DSP Digital Audio Interfaces.
properties:
reg:
description:
Digital Audio Interface ID
qcom,sd-lines:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
List of serial data lines used by this dai.should be one or more of the 0-3 sd lines.
minItems: 1
maxItems: 4
uniqueItems: true
items:
minimum: 0
maximum: 3
qcom,tdm-sync-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
description:
TDM Synchronization mode
0 = Short sync bit mode
1 = Long sync mode
2 = Short sync slot mode
qcom,tdm-sync-src:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description:
TDM Synchronization source
0 = External source
1 = Internal source
qcom,tdm-data-out:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description:
TDM Data out signal to drive with other masters
0 = Disable
1 = Enable
qcom,tdm-invert-sync:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description:
TDM Invert the sync
0 = Normal
1 = Invert
qcom,tdm-data-delay:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
description:
TDM Number of bit clock to delay data
0 = 0 bit clock cycle
1 = 1 bit clock cycle
2 = 2 bit clock cycle
qcom,tdm-data-align:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description:
Indicate how data is packed within the slot. For example, 32 slot
width in case of sample bit width is 24TDM Invert the sync.
0 = MSB
1 = LSB
required:
- reg
allOf:
- if:
properties:
reg:
contains:
# TDM DAI ID range from PRIMARY_TDM_RX_0 - QUINARY_TDM_TX_7
items:
minimum: 24
maximum: 103
then:
required:
- qcom,tdm-sync-mode
- qcom,tdm-sync-src
- qcom,tdm-data-out
- qcom,tdm-invert-sync
- qcom,tdm-data-delay
- qcom,tdm-data-align
- if:
properties:
reg:
contains:
# MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and
# QUINARY_MI2S_RX - QUINARY_MI2S_TX
items:
oneOf:
- minimum: 16
maximum: 23
- minimum: 127
maximum: 128
then:
required:
- qcom,sd-lines
additionalProperties: false
required:
- compatible
- reg
- "#sound-dai-cells"
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/sound/qcom,q6afe.h>
apr {
#address-cells = <1>;
#size-cells = <0>;
apr-service@4 {
reg = <APR_SVC_AFE>;
#address-cells = <1>;
#size-cells = <0>;
q6afedai@1 {
compatible = "qcom,q6afe-dais";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
dai@22 {
reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <0 1 2 3>;
};
};
};
};
- |
#include <dt-bindings/soc/qcom,gpr.h>
gpr {
compatible = "qcom,gpr";
#address-cells = <1>;
#size-cells = <0>;
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#address-cells = <1>;
#size-cells = <0>;
q6apmdai@1 {
compatible = "qcom,q6apm-lpass-dais";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
dai@22 {
reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <0 1 2 3>;
};
};
};
};

2
drivers/soc/qcom/Kconfig
View File

@ -199,7 +199,7 @@ config QCOM_WCNSS_CTRL
firmware to a newly booted WCNSS chip.
config QCOM_APR
tristate "Qualcomm APR Bus (Asynchronous Packet Router)"
tristate "Qualcomm APR/GPR Bus (Asynchronous/Generic Packet Router)"
depends on ARCH_QCOM || COMPILE_TEST
depends on RPMSG
depends on NET

287
drivers/soc/qcom/apr.c
View File

@ -15,13 +15,23 @@
#include <linux/rpmsg.h>
#include <linux/of.h>
struct apr {
enum {
PR_TYPE_APR = 0,
PR_TYPE_GPR,
};
/* Some random values tbh which does not collide with static modules */
#define GPR_DYNAMIC_PORT_START 0x10000000
#define GPR_DYNAMIC_PORT_END 0x20000000
struct packet_router {
struct rpmsg_endpoint *ch;
struct device *dev;
spinlock_t svcs_lock;
spinlock_t rx_lock;
struct idr svcs_idr;
int dest_domain_id;
int type;
struct pdr_handle *pdr;
struct workqueue_struct *rxwq;
struct work_struct rx_work;
@ -44,26 +54,103 @@ struct apr_rx_buf {
*/
int apr_send_pkt(struct apr_device *adev, struct apr_pkt *pkt)
{
struct apr *apr = dev_get_drvdata(adev->dev.parent);
struct packet_router *apr = dev_get_drvdata(adev->dev.parent);
struct apr_hdr *hdr;
unsigned long flags;
int ret;
spin_lock_irqsave(&adev->lock, flags);
spin_lock_irqsave(&adev->svc.lock, flags);
hdr = &pkt->hdr;
hdr->src_domain = APR_DOMAIN_APPS;
hdr->src_svc = adev->svc_id;
hdr->src_svc = adev->svc.id;
hdr->dest_domain = adev->domain_id;
hdr->dest_svc = adev->svc_id;
hdr->dest_svc = adev->svc.id;
ret = rpmsg_trysend(apr->ch, pkt, hdr->pkt_size);
spin_unlock_irqrestore(&adev->lock, flags);
spin_unlock_irqrestore(&adev->svc.lock, flags);
return ret ? ret : hdr->pkt_size;
}
EXPORT_SYMBOL_GPL(apr_send_pkt);
void gpr_free_port(gpr_port_t *port)
{
struct packet_router *gpr = port->pr;
unsigned long flags;
spin_lock_irqsave(&gpr->svcs_lock, flags);
idr_remove(&gpr->svcs_idr, port->id);
spin_unlock_irqrestore(&gpr->svcs_lock, flags);
kfree(port);
}
EXPORT_SYMBOL_GPL(gpr_free_port);
gpr_port_t *gpr_alloc_port(struct apr_device *gdev, struct device *dev,
gpr_port_cb cb, void *priv)
{
struct packet_router *pr = dev_get_drvdata(gdev->dev.parent);
gpr_port_t *port;
struct pkt_router_svc *svc;
int id;
port = kzalloc(sizeof(*port), GFP_KERNEL);
if (!port)
return ERR_PTR(-ENOMEM);
svc = port;
svc->callback = cb;
svc->pr = pr;
svc->priv = priv;
svc->dev = dev;
spin_lock_init(&svc->lock);
spin_lock(&pr->svcs_lock);
id = idr_alloc_cyclic(&pr->svcs_idr, svc, GPR_DYNAMIC_PORT_START,
GPR_DYNAMIC_PORT_END, GFP_ATOMIC);
if (id < 0) {
dev_err(dev, "Unable to allocate dynamic GPR src port\n");
kfree(port);
spin_unlock(&pr->svcs_lock);
return ERR_PTR(id);
}
svc->id = id;
spin_unlock(&pr->svcs_lock);
return port;
}
EXPORT_SYMBOL_GPL(gpr_alloc_port);
static int pkt_router_send_svc_pkt(struct pkt_router_svc *svc, struct gpr_pkt *pkt)
{
struct packet_router *pr = svc->pr;
struct gpr_hdr *hdr;
unsigned long flags;
int ret;
hdr = &pkt->hdr;
spin_lock_irqsave(&svc->lock, flags);
ret = rpmsg_trysend(pr->ch, pkt, hdr->pkt_size);
spin_unlock_irqrestore(&svc->lock, flags);
return ret ? ret : hdr->pkt_size;
}
int gpr_send_pkt(struct apr_device *gdev, struct gpr_pkt *pkt)
{
return pkt_router_send_svc_pkt(&gdev->svc, pkt);
}
EXPORT_SYMBOL_GPL(gpr_send_pkt);
int gpr_send_port_pkt(gpr_port_t *port, struct gpr_pkt *pkt)
{
return pkt_router_send_svc_pkt(port, pkt);
}
EXPORT_SYMBOL_GPL(gpr_send_port_pkt);
static void apr_dev_release(struct device *dev)
{
struct apr_device *adev = to_apr_device(dev);
@ -74,7 +161,7 @@ static void apr_dev_release(struct device *dev)
static int apr_callback(struct rpmsg_device *rpdev, void *buf,
int len, void *priv, u32 addr)
{
struct apr *apr = dev_get_drvdata(&rpdev->dev);
struct packet_router *apr = dev_get_drvdata(&rpdev->dev);
struct apr_rx_buf *abuf;
unsigned long flags;
@ -100,11 +187,11 @@ static int apr_callback(struct rpmsg_device *rpdev, void *buf,
return 0;
}
static int apr_do_rx_callback(struct apr *apr, struct apr_rx_buf *abuf)
static int apr_do_rx_callback(struct packet_router *apr, struct apr_rx_buf *abuf)
{
uint16_t hdr_size, msg_type, ver, svc_id;
struct apr_device *svc = NULL;
struct pkt_router_svc *svc;
struct apr_device *adev;
struct apr_driver *adrv = NULL;
struct apr_resp_pkt resp;
struct apr_hdr *hdr;
@ -145,12 +232,15 @@ static int apr_do_rx_callback(struct apr *apr, struct apr_rx_buf *abuf)
svc_id = hdr->dest_svc;
spin_lock_irqsave(&apr->svcs_lock, flags);
svc = idr_find(&apr->svcs_idr, svc_id);
if (svc && svc->dev.driver)
adrv = to_apr_driver(svc->dev.driver);
if (svc && svc->dev->driver) {
adev = svc_to_apr_device(svc);
adrv = to_apr_driver(adev->dev.driver);
}
spin_unlock_irqrestore(&apr->svcs_lock, flags);
if (!adrv) {
dev_err(apr->dev, "APR: service is not registered\n");
if (!adrv || !adev) {
dev_err(apr->dev, "APR: service is not registered (%d)\n",
svc_id);
return -EINVAL;
}
@ -164,20 +254,82 @@ static int apr_do_rx_callback(struct apr *apr, struct apr_rx_buf *abuf)
if (resp.payload_size > 0)
resp.payload = buf + hdr_size;
adrv->callback(svc, &resp);
adrv->callback(adev, &resp);
return 0;
}
static int gpr_do_rx_callback(struct packet_router *gpr, struct apr_rx_buf *abuf)
{
uint16_t hdr_size, ver;
struct pkt_router_svc *svc = NULL;
struct gpr_resp_pkt resp;
struct gpr_hdr *hdr;
unsigned long flags;
void *buf = abuf->buf;
int len = abuf->len;
hdr = buf;
ver = hdr->version;
if (ver > GPR_PKT_VER + 1)
return -EINVAL;
hdr_size = hdr->hdr_size;
if (hdr_size < GPR_PKT_HEADER_WORD_SIZE) {
dev_err(gpr->dev, "GPR: Wrong hdr size:%d\n", hdr_size);
return -EINVAL;
}
if (hdr->pkt_size < GPR_PKT_HEADER_BYTE_SIZE || hdr->pkt_size != len) {
dev_err(gpr->dev, "GPR: Wrong packet size\n");
return -EINVAL;
}
resp.hdr = *hdr;
resp.payload_size = hdr->pkt_size - (hdr_size * 4);
/*
* NOTE: hdr_size is not same as GPR_HDR_SIZE as remote can include
* optional headers in to gpr_hdr which should be ignored
*/
if (resp.payload_size > 0)
resp.payload = buf + (hdr_size * 4);
spin_lock_irqsave(&gpr->svcs_lock, flags);
svc = idr_find(&gpr->svcs_idr, hdr->dest_port);
spin_unlock_irqrestore(&gpr->svcs_lock, flags);
if (!svc) {
dev_err(gpr->dev, "GPR: Port(%x) is not registered\n",
hdr->dest_port);
return -EINVAL;
}
if (svc->callback)
svc->callback(&resp, svc->priv, 0);
return 0;
}
static void apr_rxwq(struct work_struct *work)
{
struct apr *apr = container_of(work, struct apr, rx_work);
struct packet_router *apr = container_of(work, struct packet_router, rx_work);
struct apr_rx_buf *abuf, *b;
unsigned long flags;
if (!list_empty(&apr->rx_list)) {
list_for_each_entry_safe(abuf, b, &apr->rx_list, node) {
apr_do_rx_callback(apr, abuf);
switch (apr->type) {
case PR_TYPE_APR:
apr_do_rx_callback(apr, abuf);
break;
case PR_TYPE_GPR:
gpr_do_rx_callback(apr, abuf);
break;
default:
break;
}
spin_lock_irqsave(&apr->rx_lock, flags);
list_del(&abuf->node);
spin_unlock_irqrestore(&apr->rx_lock, flags);
@ -201,7 +353,7 @@ static int apr_device_match(struct device *dev, struct device_driver *drv)
while (id->domain_id != 0 || id->svc_id != 0) {
if (id->domain_id == adev->domain_id &&
id->svc_id == adev->svc_id)
id->svc_id == adev->svc.id)
return 1;
id++;
}
@ -213,22 +365,27 @@ static int apr_device_probe(struct device *dev)
{
struct apr_device *adev = to_apr_device(dev);
struct apr_driver *adrv = to_apr_driver(dev->driver);
int ret;
return adrv->probe(adev);
ret = adrv->probe(adev);
if (!ret)
adev->svc.callback = adrv->gpr_callback;
return ret;
}
static void apr_device_remove(struct device *dev)
{
struct apr_device *adev = to_apr_device(dev);
struct apr_driver *adrv;
struct apr *apr = dev_get_drvdata(adev->dev.parent);
struct packet_router *apr = dev_get_drvdata(adev->dev.parent);
if (dev->driver) {
adrv = to_apr_driver(dev->driver);
if (adrv->remove)
adrv->remove(adev);
spin_lock(&apr->svcs_lock);
idr_remove(&apr->svcs_idr, adev->svc_id);
idr_remove(&apr->svcs_idr, adev->svc.id);
spin_unlock(&apr->svcs_lock);
}
}
@ -255,28 +412,43 @@ struct bus_type aprbus = {
EXPORT_SYMBOL_GPL(aprbus);
static int apr_add_device(struct device *dev, struct device_node *np,
const struct apr_device_id *id)
u32 svc_id, u32 domain_id)
{
struct apr *apr = dev_get_drvdata(dev);
struct packet_router *apr = dev_get_drvdata(dev);
struct apr_device *adev = NULL;
struct pkt_router_svc *svc;
int ret;
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
if (!adev)
return -ENOMEM;
spin_lock_init(&adev->lock);
adev->svc_id = svc_id;
svc = &adev->svc;
svc->id = svc_id;
svc->pr = apr;
svc->priv = adev;
svc->dev = dev;
spin_lock_init(&svc->lock);
adev->domain_id = domain_id;
adev->svc_id = id->svc_id;
adev->domain_id = id->domain_id;
adev->version = id->svc_version;
if (np)
snprintf(adev->name, APR_NAME_SIZE, "%pOFn", np);
else
strscpy(adev->name, id->name, APR_NAME_SIZE);
dev_set_name(&adev->dev, "aprsvc:%s:%x:%x", adev->name,
id->domain_id, id->svc_id);
switch (apr->type) {
case PR_TYPE_APR:
dev_set_name(&adev->dev, "aprsvc:%s:%x:%x", adev->name,
domain_id, svc_id);
break;
case PR_TYPE_GPR:
dev_set_name(&adev->dev, "gprsvc:%s:%x:%x", adev->name,
domain_id, svc_id);
break;
default:
break;
}
adev->dev.bus = &aprbus;
adev->dev.parent = dev;
@ -285,14 +457,13 @@ static int apr_add_device(struct device *dev, struct device_node *np,
adev->dev.driver = NULL;
spin_lock(&apr->svcs_lock);
idr_alloc(&apr->svcs_idr, adev, id->svc_id,
id->svc_id + 1, GFP_ATOMIC);
idr_alloc(&apr->svcs_idr, svc, svc_id, svc_id + 1, GFP_ATOMIC);
spin_unlock(&apr->svcs_lock);
of_property_read_string_index(np, "qcom,protection-domain",
1, &adev->service_path);
dev_info(dev, "Adding APR dev: %s\n", dev_name(&adev->dev));
dev_info(dev, "Adding APR/GPR dev: %s\n", dev_name(&adev->dev));
ret = device_register(&adev->dev);
if (ret) {
@ -306,7 +477,7 @@ static int apr_add_device(struct device *dev, struct device_node *np,
static int of_apr_add_pd_lookups(struct device *dev)
{
const char *service_name, *service_path;
struct apr *apr = dev_get_drvdata(dev);
struct packet_router *apr = dev_get_drvdata(dev);
struct device_node *node;
struct pdr_service *pds;
int ret;
@ -336,13 +507,14 @@ static int of_apr_add_pd_lookups(struct device *dev)
static void of_register_apr_devices(struct device *dev, const char *svc_path)
{
struct apr *apr = dev_get_drvdata(dev);
struct packet_router *apr = dev_get_drvdata(dev);
struct device_node *node;
const char *service_path;
int ret;
for_each_child_of_node(dev->of_node, node) {
struct apr_device_id id = { {0} };
u32 svc_id;
u32 domain_id;
/*
* This function is called with svc_path NULL during
@ -372,13 +544,13 @@ static void of_register_apr_devices(struct device *dev, const char *svc_path)
continue;
}
if (of_property_read_u32(node, "reg", &id.svc_id))
if (of_property_read_u32(node, "reg", &svc_id))
continue;
id.domain_id = apr->dest_domain_id;
domain_id = apr->dest_domain_id;
if (apr_add_device(dev, node, &id))
dev_err(dev, "Failed to add apr %d svc\n", id.svc_id);
if (apr_add_device(dev, node, svc_id, domain_id))
dev_err(dev, "Failed to add apr %d svc\n", svc_id);
}
}
@ -398,7 +570,7 @@ static int apr_remove_device(struct device *dev, void *svc_path)
static void apr_pd_status(int state, char *svc_path, void *priv)
{
struct apr *apr = (struct apr *)priv;
struct packet_router *apr = (struct packet_router *)priv;
switch (state) {
case SERVREG_SERVICE_STATE_UP:
@ -413,16 +585,26 @@ static void apr_pd_status(int state, char *svc_path, void *priv)
static int apr_probe(struct rpmsg_device *rpdev)
{
struct device *dev = &rpdev->dev;
struct apr *apr;
struct packet_router *apr;
int ret;
apr = devm_kzalloc(dev, sizeof(*apr), GFP_KERNEL);
if (!apr)
return -ENOMEM;
ret = of_property_read_u32(dev->of_node, "qcom,apr-domain", &apr->dest_domain_id);
ret = of_property_read_u32(dev->of_node, "qcom,domain", &apr->dest_domain_id);
if (of_device_is_compatible(dev->of_node, "qcom,gpr")) {
apr->type = PR_TYPE_GPR;
} else {
if (ret) /* try deprecated apr-domain property */
ret = of_property_read_u32(dev->of_node, "qcom,apr-domain",
&apr->dest_domain_id);
apr->type = PR_TYPE_APR;
}
if (ret) {
dev_err(dev, "APR Domain ID not specified in DT\n");
dev_err(dev, "Domain ID not specified in DT\n");
return ret;
}
@ -465,7 +647,7 @@ destroy_wq:
static void apr_remove(struct rpmsg_device *rpdev)
{
struct apr *apr = dev_get_drvdata(&rpdev->dev);
struct packet_router *apr = dev_get_drvdata(&rpdev->dev);
pdr_handle_release(apr->pdr);
device_for_each_child(&rpdev->dev, NULL, apr_remove_device);
@ -502,20 +684,21 @@ void apr_driver_unregister(struct apr_driver *drv)
}
EXPORT_SYMBOL_GPL(apr_driver_unregister);
static const struct of_device_id apr_of_match[] = {
static const struct of_device_id pkt_router_of_match[] = {
{ .compatible = "qcom,apr"},
{ .compatible = "qcom,apr-v2"},
{ .compatible = "qcom,gpr"},
{}
};
MODULE_DEVICE_TABLE(of, apr_of_match);
MODULE_DEVICE_TABLE(of, pkt_router_of_match);
static struct rpmsg_driver apr_driver = {
static struct rpmsg_driver packet_router_driver = {
.probe = apr_probe,
.remove = apr_remove,
.callback = apr_callback,
.drv = {
.name = "qcom,apr",
.of_match_table = apr_of_match,
.of_match_table = pkt_router_of_match,
},
};
@ -525,7 +708,7 @@ static int __init apr_init(void)
ret = bus_register(&aprbus);
if (!ret)
ret = register_rpmsg_driver(&apr_driver);
ret = register_rpmsg_driver(&packet_router_driver);
else
bus_unregister(&aprbus);
@ -535,7 +718,7 @@ static int __init apr_init(void)
static void __exit apr_exit(void)
{
bus_unregister(&aprbus);
unregister_rpmsg_driver(&apr_driver);
unregister_rpmsg_driver(&packet_router_driver);
}
subsys_initcall(apr_init);

19
include/dt-bindings/soc/qcom,gpr.h Normal file
View File

@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
#ifndef __DT_BINDINGS_QCOM_GPR_H
#define __DT_BINDINGS_QCOM_GPR_H
/* DOMAINS */
#define GPR_DOMAIN_ID_MODEM 1
#define GPR_DOMAIN_ID_ADSP 2
#define GPR_DOMAIN_ID_APPS 3
/* Static Services */
#define GPR_APM_MODULE_IID 1
#define GPR_PRM_MODULE_IID 2
#define GPR_AMDB_MODULE_IID 3
#define GPR_VCPM_MODULE_IID 4
#endif /* __DT_BINDINGS_QCOM_GPR_H */

203
include/dt-bindings/sound/qcom,q6afe.h
View File

@ -2,207 +2,8 @@
#ifndef __DT_BINDINGS_Q6_AFE_H__
#define __DT_BINDINGS_Q6_AFE_H__
/* Audio Front End (AFE) virtual ports IDs */
#define HDMI_RX 1
#define SLIMBUS_0_RX 2
#define SLIMBUS_0_TX 3
#define SLIMBUS_1_RX 4
#define SLIMBUS_1_TX 5
#define SLIMBUS_2_RX 6
#define SLIMBUS_2_TX 7
#define SLIMBUS_3_RX 8
#define SLIMBUS_3_TX 9
#define SLIMBUS_4_RX 10
#define SLIMBUS_4_TX 11
#define SLIMBUS_5_RX 12
#define SLIMBUS_5_TX 13
#define SLIMBUS_6_RX 14
#define SLIMBUS_6_TX 15
#define PRIMARY_MI2S_RX 16
#define PRIMARY_MI2S_TX 17
#define SECONDARY_MI2S_RX 18
#define SECONDARY_MI2S_TX 19
#define TERTIARY_MI2S_RX 20
#define TERTIARY_MI2S_TX 21
#define QUATERNARY_MI2S_RX 22
#define QUATERNARY_MI2S_TX 23
#define PRIMARY_TDM_RX_0 24
#define PRIMARY_TDM_TX_0 25
#define PRIMARY_TDM_RX_1 26
#define PRIMARY_TDM_TX_1 27
#define PRIMARY_TDM_RX_2 28
#define PRIMARY_TDM_TX_2 29
#define PRIMARY_TDM_RX_3 30
#define PRIMARY_TDM_TX_3 31
#define PRIMARY_TDM_RX_4 32
#define PRIMARY_TDM_TX_4 33
#define PRIMARY_TDM_RX_5 34
#define PRIMARY_TDM_TX_5 35
#define PRIMARY_TDM_RX_6 36
#define PRIMARY_TDM_TX_6 37
#define PRIMARY_TDM_RX_7 38
#define PRIMARY_TDM_TX_7 39
#define SECONDARY_TDM_RX_0 40
#define SECONDARY_TDM_TX_0 41
#define SECONDARY_TDM_RX_1 42
#define SECONDARY_TDM_TX_1 43
#define SECONDARY_TDM_RX_2 44
#define SECONDARY_TDM_TX_2 45
#define SECONDARY_TDM_RX_3 46
#define SECONDARY_TDM_TX_3 47
#define SECONDARY_TDM_RX_4 48
#define SECONDARY_TDM_TX_4 49
#define SECONDARY_TDM_RX_5 50
#define SECONDARY_TDM_TX_5 51
#define SECONDARY_TDM_RX_6 52
#define SECONDARY_TDM_TX_6 53
#define SECONDARY_TDM_RX_7 54
#define SECONDARY_TDM_TX_7 55
#define TERTIARY_TDM_RX_0 56
#define TERTIARY_TDM_TX_0 57
#define TERTIARY_TDM_RX_1 58
#define TERTIARY_TDM_TX_1 59
#define TERTIARY_TDM_RX_2 60
#define TERTIARY_TDM_TX_2 61
#define TERTIARY_TDM_RX_3 62
#define TERTIARY_TDM_TX_3 63
#define TERTIARY_TDM_RX_4 64
#define TERTIARY_TDM_TX_4 65
#define TERTIARY_TDM_RX_5 66
#define TERTIARY_TDM_TX_5 67
#define TERTIARY_TDM_RX_6 68
#define TERTIARY_TDM_TX_6 69
#define TERTIARY_TDM_RX_7 70
#define TERTIARY_TDM_TX_7 71
#define QUATERNARY_TDM_RX_0 72
#define QUATERNARY_TDM_TX_0 73
#define QUATERNARY_TDM_RX_1 74
#define QUATERNARY_TDM_TX_1 75
#define QUATERNARY_TDM_RX_2 76
#define QUATERNARY_TDM_TX_2 77
#define QUATERNARY_TDM_RX_3 78
#define QUATERNARY_TDM_TX_3 79
#define QUATERNARY_TDM_RX_4 80
#define QUATERNARY_TDM_TX_4 81
#define QUATERNARY_TDM_RX_5 82
#define QUATERNARY_TDM_TX_5 83
#define QUATERNARY_TDM_RX_6 84
#define QUATERNARY_TDM_TX_6 85
#define QUATERNARY_TDM_RX_7 86
#define QUATERNARY_TDM_TX_7 87
#define QUINARY_TDM_RX_0 88
#define QUINARY_TDM_TX_0 89
#define QUINARY_TDM_RX_1 90
#define QUINARY_TDM_TX_1 91
#define QUINARY_TDM_RX_2 92
#define QUINARY_TDM_TX_2 93
#define QUINARY_TDM_RX_3 94
#define QUINARY_TDM_TX_3 95
#define QUINARY_TDM_RX_4 96
#define QUINARY_TDM_TX_4 97
#define QUINARY_TDM_RX_5 98
#define QUINARY_TDM_TX_5 99
#define QUINARY_TDM_RX_6 100
#define QUINARY_TDM_TX_6 101
#define QUINARY_TDM_RX_7 102
#define QUINARY_TDM_TX_7 103
#define DISPLAY_PORT_RX 104
#define WSA_CODEC_DMA_RX_0 105
#define WSA_CODEC_DMA_TX_0 106
#define WSA_CODEC_DMA_RX_1 107
#define WSA_CODEC_DMA_TX_1 108
#define WSA_CODEC_DMA_TX_2 109
#define VA_CODEC_DMA_TX_0 110
#define VA_CODEC_DMA_TX_1 111
#define VA_CODEC_DMA_TX_2 112
#define RX_CODEC_DMA_RX_0 113
#define TX_CODEC_DMA_TX_0 114
#define RX_CODEC_DMA_RX_1 115
#define TX_CODEC_DMA_TX_1 116
#define RX_CODEC_DMA_RX_2 117
#define TX_CODEC_DMA_TX_2 118
#define RX_CODEC_DMA_RX_3 119
#define TX_CODEC_DMA_TX_3 120
#define RX_CODEC_DMA_RX_4 121
#define TX_CODEC_DMA_TX_4 122
#define RX_CODEC_DMA_RX_5 123
#define TX_CODEC_DMA_TX_5 124
#define RX_CODEC_DMA_RX_6 125
#define RX_CODEC_DMA_RX_7 126
#define QUINARY_MI2S_RX 127
#define QUINARY_MI2S_TX 128
/* This file exists due to backward compatibility reasons, Please do not DELETE! */
#define LPASS_CLK_ID_PRI_MI2S_IBIT 1
#define LPASS_CLK_ID_PRI_MI2S_EBIT 2
#define LPASS_CLK_ID_SEC_MI2S_IBIT 3
#define LPASS_CLK_ID_SEC_MI2S_EBIT 4
#define LPASS_CLK_ID_TER_MI2S_IBIT 5
#define LPASS_CLK_ID_TER_MI2S_EBIT 6
#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7
#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8
#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9
#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10
#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11
#define LPASS_CLK_ID_QUI_MI2S_IBIT 12
#define LPASS_CLK_ID_QUI_MI2S_EBIT 13
#define LPASS_CLK_ID_SEN_MI2S_IBIT 14
#define LPASS_CLK_ID_SEN_MI2S_EBIT 15
#define LPASS_CLK_ID_INT0_MI2S_IBIT 16
#define LPASS_CLK_ID_INT1_MI2S_IBIT 17
#define LPASS_CLK_ID_INT2_MI2S_IBIT 18
#define LPASS_CLK_ID_INT3_MI2S_IBIT 19
#define LPASS_CLK_ID_INT4_MI2S_IBIT 20
#define LPASS_CLK_ID_INT5_MI2S_IBIT 21
#define LPASS_CLK_ID_INT6_MI2S_IBIT 22
#define LPASS_CLK_ID_QUI_MI2S_OSR 23
#define LPASS_CLK_ID_PRI_PCM_IBIT 24
#define LPASS_CLK_ID_PRI_PCM_EBIT 25
#define LPASS_CLK_ID_SEC_PCM_IBIT 26
#define LPASS_CLK_ID_SEC_PCM_EBIT 27
#define LPASS_CLK_ID_TER_PCM_IBIT 28
#define LPASS_CLK_ID_TER_PCM_EBIT 29
#define LPASS_CLK_ID_QUAD_PCM_IBIT 30
#define LPASS_CLK_ID_QUAD_PCM_EBIT 31
#define LPASS_CLK_ID_QUIN_PCM_IBIT 32
#define LPASS_CLK_ID_QUIN_PCM_EBIT 33
#define LPASS_CLK_ID_QUI_PCM_OSR 34
#define LPASS_CLK_ID_PRI_TDM_IBIT 35
#define LPASS_CLK_ID_PRI_TDM_EBIT 36
#define LPASS_CLK_ID_SEC_TDM_IBIT 37
#define LPASS_CLK_ID_SEC_TDM_EBIT 38
#define LPASS_CLK_ID_TER_TDM_IBIT 39
#define LPASS_CLK_ID_TER_TDM_EBIT 40
#define LPASS_CLK_ID_QUAD_TDM_IBIT 41
#define LPASS_CLK_ID_QUAD_TDM_EBIT 42
#define LPASS_CLK_ID_QUIN_TDM_IBIT 43
#define LPASS_CLK_ID_QUIN_TDM_EBIT 44
#define LPASS_CLK_ID_QUIN_TDM_OSR 45
#define LPASS_CLK_ID_MCLK_1 46
#define LPASS_CLK_ID_MCLK_2 47
#define LPASS_CLK_ID_MCLK_3 48
#define LPASS_CLK_ID_MCLK_4 49
#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50
#define LPASS_CLK_ID_INT_MCLK_0 51
#define LPASS_CLK_ID_INT_MCLK_1 52
#define LPASS_CLK_ID_MCLK_5 53
#define LPASS_CLK_ID_WSA_CORE_MCLK 54
#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55
#define LPASS_CLK_ID_VA_CORE_MCLK 56
#define LPASS_CLK_ID_TX_CORE_MCLK 57
#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58
#define LPASS_CLK_ID_RX_CORE_MCLK 59
#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60
#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61
#define LPASS_HW_AVTIMER_VOTE 101
#define LPASS_HW_MACRO_VOTE 102
#define LPASS_HW_DCODEC_VOTE 103
#define Q6AFE_MAX_CLK_ID 104
#define LPASS_CLK_ATTRIBUTE_INVALID 0x0
#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#endif /* __DT_BINDINGS_Q6_AFE_H__ */

208
include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h Normal file
View File

@ -0,0 +1,208 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__
#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__
/* LPASS Audio virtual ports IDs */
#define HDMI_RX 1
#define SLIMBUS_0_RX 2
#define SLIMBUS_0_TX 3
#define SLIMBUS_1_RX 4
#define SLIMBUS_1_TX 5
#define SLIMBUS_2_RX 6
#define SLIMBUS_2_TX 7
#define SLIMBUS_3_RX 8
#define SLIMBUS_3_TX 9
#define SLIMBUS_4_RX 10
#define SLIMBUS_4_TX 11
#define SLIMBUS_5_RX 12
#define SLIMBUS_5_TX 13
#define SLIMBUS_6_RX 14
#define SLIMBUS_6_TX 15
#define PRIMARY_MI2S_RX 16
#define PRIMARY_MI2S_TX 17
#define SECONDARY_MI2S_RX 18
#define SECONDARY_MI2S_TX 19
#define TERTIARY_MI2S_RX 20
#define TERTIARY_MI2S_TX 21
#define QUATERNARY_MI2S_RX 22
#define QUATERNARY_MI2S_TX 23
#define PRIMARY_TDM_RX_0 24
#define PRIMARY_TDM_TX_0 25
#define PRIMARY_TDM_RX_1 26
#define PRIMARY_TDM_TX_1 27
#define PRIMARY_TDM_RX_2 28
#define PRIMARY_TDM_TX_2 29
#define PRIMARY_TDM_RX_3 30
#define PRIMARY_TDM_TX_3 31
#define PRIMARY_TDM_RX_4 32
#define PRIMARY_TDM_TX_4 33
#define PRIMARY_TDM_RX_5 34
#define PRIMARY_TDM_TX_5 35
#define PRIMARY_TDM_RX_6 36
#define PRIMARY_TDM_TX_6 37
#define PRIMARY_TDM_RX_7 38
#define PRIMARY_TDM_TX_7 39
#define SECONDARY_TDM_RX_0 40
#define SECONDARY_TDM_TX_0 41
#define SECONDARY_TDM_RX_1 42
#define SECONDARY_TDM_TX_1 43
#define SECONDARY_TDM_RX_2 44
#define SECONDARY_TDM_TX_2 45
#define SECONDARY_TDM_RX_3 46
#define SECONDARY_TDM_TX_3 47
#define SECONDARY_TDM_RX_4 48
#define SECONDARY_TDM_TX_4 49
#define SECONDARY_TDM_RX_5 50
#define SECONDARY_TDM_TX_5 51
#define SECONDARY_TDM_RX_6 52
#define SECONDARY_TDM_TX_6 53
#define SECONDARY_TDM_RX_7 54
#define SECONDARY_TDM_TX_7 55
#define TERTIARY_TDM_RX_0 56
#define TERTIARY_TDM_TX_0 57
#define TERTIARY_TDM_RX_1 58
#define TERTIARY_TDM_TX_1 59
#define TERTIARY_TDM_RX_2 60
#define TERTIARY_TDM_TX_2 61
#define TERTIARY_TDM_RX_3 62
#define TERTIARY_TDM_TX_3 63
#define TERTIARY_TDM_RX_4 64
#define TERTIARY_TDM_TX_4 65
#define TERTIARY_TDM_RX_5 66
#define TERTIARY_TDM_TX_5 67
#define TERTIARY_TDM_RX_6 68
#define TERTIARY_TDM_TX_6 69
#define TERTIARY_TDM_RX_7 70
#define TERTIARY_TDM_TX_7 71
#define QUATERNARY_TDM_RX_0 72
#define QUATERNARY_TDM_TX_0 73
#define QUATERNARY_TDM_RX_1 74
#define QUATERNARY_TDM_TX_1 75
#define QUATERNARY_TDM_RX_2 76
#define QUATERNARY_TDM_TX_2 77
#define QUATERNARY_TDM_RX_3 78
#define QUATERNARY_TDM_TX_3 79
#define QUATERNARY_TDM_RX_4 80
#define QUATERNARY_TDM_TX_4 81
#define QUATERNARY_TDM_RX_5 82
#define QUATERNARY_TDM_TX_5 83
#define QUATERNARY_TDM_RX_6 84
#define QUATERNARY_TDM_TX_6 85
#define QUATERNARY_TDM_RX_7 86
#define QUATERNARY_TDM_TX_7 87
#define QUINARY_TDM_RX_0 88
#define QUINARY_TDM_TX_0 89
#define QUINARY_TDM_RX_1 90
#define QUINARY_TDM_TX_1 91
#define QUINARY_TDM_RX_2 92
#define QUINARY_TDM_TX_2 93
#define QUINARY_TDM_RX_3 94
#define QUINARY_TDM_TX_3 95
#define QUINARY_TDM_RX_4 96
#define QUINARY_TDM_TX_4 97
#define QUINARY_TDM_RX_5 98
#define QUINARY_TDM_TX_5 99
#define QUINARY_TDM_RX_6 100
#define QUINARY_TDM_TX_6 101
#define QUINARY_TDM_RX_7 102
#define QUINARY_TDM_TX_7 103
#define DISPLAY_PORT_RX 104
#define WSA_CODEC_DMA_RX_0 105
#define WSA_CODEC_DMA_TX_0 106
#define WSA_CODEC_DMA_RX_1 107
#define WSA_CODEC_DMA_TX_1 108
#define WSA_CODEC_DMA_TX_2 109
#define VA_CODEC_DMA_TX_0 110
#define VA_CODEC_DMA_TX_1 111
#define VA_CODEC_DMA_TX_2 112
#define RX_CODEC_DMA_RX_0 113
#define TX_CODEC_DMA_TX_0 114
#define RX_CODEC_DMA_RX_1 115
#define TX_CODEC_DMA_TX_1 116
#define RX_CODEC_DMA_RX_2 117
#define TX_CODEC_DMA_TX_2 118
#define RX_CODEC_DMA_RX_3 119
#define TX_CODEC_DMA_TX_3 120
#define RX_CODEC_DMA_RX_4 121
#define TX_CODEC_DMA_TX_4 122
#define RX_CODEC_DMA_RX_5 123
#define TX_CODEC_DMA_TX_5 124
#define RX_CODEC_DMA_RX_6 125
#define RX_CODEC_DMA_RX_7 126
#define QUINARY_MI2S_RX 127
#define QUINARY_MI2S_TX 128
#define LPASS_CLK_ID_PRI_MI2S_IBIT 1
#define LPASS_CLK_ID_PRI_MI2S_EBIT 2
#define LPASS_CLK_ID_SEC_MI2S_IBIT 3
#define LPASS_CLK_ID_SEC_MI2S_EBIT 4
#define LPASS_CLK_ID_TER_MI2S_IBIT 5
#define LPASS_CLK_ID_TER_MI2S_EBIT 6
#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7
#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8
#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9
#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10
#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11
#define LPASS_CLK_ID_QUI_MI2S_IBIT 12
#define LPASS_CLK_ID_QUI_MI2S_EBIT 13
#define LPASS_CLK_ID_SEN_MI2S_IBIT 14
#define LPASS_CLK_ID_SEN_MI2S_EBIT 15
#define LPASS_CLK_ID_INT0_MI2S_IBIT 16
#define LPASS_CLK_ID_INT1_MI2S_IBIT 17
#define LPASS_CLK_ID_INT2_MI2S_IBIT 18
#define LPASS_CLK_ID_INT3_MI2S_IBIT 19
#define LPASS_CLK_ID_INT4_MI2S_IBIT 20
#define LPASS_CLK_ID_INT5_MI2S_IBIT 21
#define LPASS_CLK_ID_INT6_MI2S_IBIT 22
#define LPASS_CLK_ID_QUI_MI2S_OSR 23
#define LPASS_CLK_ID_PRI_PCM_IBIT 24
#define LPASS_CLK_ID_PRI_PCM_EBIT 25
#define LPASS_CLK_ID_SEC_PCM_IBIT 26
#define LPASS_CLK_ID_SEC_PCM_EBIT 27
#define LPASS_CLK_ID_TER_PCM_IBIT 28
#define LPASS_CLK_ID_TER_PCM_EBIT 29
#define LPASS_CLK_ID_QUAD_PCM_IBIT 30
#define LPASS_CLK_ID_QUAD_PCM_EBIT 31
#define LPASS_CLK_ID_QUIN_PCM_IBIT 32
#define LPASS_CLK_ID_QUIN_PCM_EBIT 33
#define LPASS_CLK_ID_QUI_PCM_OSR 34
#define LPASS_CLK_ID_PRI_TDM_IBIT 35
#define LPASS_CLK_ID_PRI_TDM_EBIT 36
#define LPASS_CLK_ID_SEC_TDM_IBIT 37
#define LPASS_CLK_ID_SEC_TDM_EBIT 38
#define LPASS_CLK_ID_TER_TDM_IBIT 39
#define LPASS_CLK_ID_TER_TDM_EBIT 40
#define LPASS_CLK_ID_QUAD_TDM_IBIT 41
#define LPASS_CLK_ID_QUAD_TDM_EBIT 42
#define LPASS_CLK_ID_QUIN_TDM_IBIT 43
#define LPASS_CLK_ID_QUIN_TDM_EBIT 44
#define LPASS_CLK_ID_QUIN_TDM_OSR 45
#define LPASS_CLK_ID_MCLK_1 46
#define LPASS_CLK_ID_MCLK_2 47
#define LPASS_CLK_ID_MCLK_3 48
#define LPASS_CLK_ID_MCLK_4 49
#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50
#define LPASS_CLK_ID_INT_MCLK_0 51
#define LPASS_CLK_ID_INT_MCLK_1 52
#define LPASS_CLK_ID_MCLK_5 53
#define LPASS_CLK_ID_WSA_CORE_MCLK 54
#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55
#define LPASS_CLK_ID_VA_CORE_MCLK 56
#define LPASS_CLK_ID_TX_CORE_MCLK 57
#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58
#define LPASS_CLK_ID_RX_CORE_MCLK 59
#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60
#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61
#define LPASS_HW_AVTIMER_VOTE 101
#define LPASS_HW_MACRO_VOTE 102
#define LPASS_HW_DCODEC_VOTE 103
#define Q6AFE_MAX_CLK_ID 104
#define LPASS_CLK_ATTRIBUTE_INVALID 0x0
#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */

70
include/linux/soc/qcom/apr.h
View File

@ -7,6 +7,7 @@
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,gpr.h>
extern struct bus_type aprbus;
@ -75,10 +76,65 @@ struct apr_resp_pkt {
int payload_size;
};
struct gpr_hdr {
uint32_t version:4;
uint32_t hdr_size:4;
uint32_t pkt_size:24;
uint32_t dest_domain:8;
uint32_t src_domain:8;
uint32_t reserved:16;
uint32_t src_port;
uint32_t dest_port;
uint32_t token;
uint32_t opcode;
} __packed;
struct gpr_pkt {
struct gpr_hdr hdr;
uint32_t payload[];
};
struct gpr_resp_pkt {
struct gpr_hdr hdr;
void *payload;
int payload_size;
};
#define GPR_HDR_SIZE sizeof(struct gpr_hdr)
#define GPR_PKT_VER 0x0
#define GPR_PKT_HEADER_WORD_SIZE ((sizeof(struct gpr_pkt) + 3) >> 2)
#define GPR_PKT_HEADER_BYTE_SIZE (GPR_PKT_HEADER_WORD_SIZE << 2)
#define GPR_BASIC_RSP_RESULT 0x02001005
struct gpr_ibasic_rsp_result_t {
uint32_t opcode;
uint32_t status;
};
#define GPR_BASIC_EVT_ACCEPTED 0x02001006
struct gpr_ibasic_rsp_accepted_t {
uint32_t opcode;
};
/* Bits 0 to 15 -- Minor version, Bits 16 to 31 -- Major version */
#define APR_SVC_MAJOR_VERSION(v) ((v >> 16) & 0xFF)
#define APR_SVC_MINOR_VERSION(v) (v & 0xFF)
typedef int (*gpr_port_cb) (struct gpr_resp_pkt *d, void *priv, int op);
struct packet_router;
struct pkt_router_svc {
struct device *dev;
gpr_port_cb callback;
struct packet_router *pr;
spinlock_t lock;
int id;
void *priv;
};
typedef struct pkt_router_svc gpr_port_t;
struct apr_device {
struct device dev;
uint16_t svc_id;
@ -86,21 +142,26 @@ struct apr_device {
uint32_t version;
char name[APR_NAME_SIZE];
const char *service_path;
spinlock_t lock;
struct pkt_router_svc svc;
struct list_head node;
};
typedef struct apr_device gpr_device_t;
#define to_apr_device(d) container_of(d, struct apr_device, dev)
#define svc_to_apr_device(d) container_of(d, struct apr_device, svc)
struct apr_driver {
int (*probe)(struct apr_device *sl);
int (*remove)(struct apr_device *sl);
int (*callback)(struct apr_device *a,
struct apr_resp_pkt *d);
int (*gpr_callback)(struct gpr_resp_pkt *d, void *data, int op);
struct device_driver driver;
const struct apr_device_id *id_table;
};
typedef struct apr_driver gpr_driver_t;
#define to_apr_driver(d) container_of(d, struct apr_driver, driver)
/*
@ -123,7 +184,14 @@ void apr_driver_unregister(struct apr_driver *drv);
#define module_apr_driver(__apr_driver) \
module_driver(__apr_driver, apr_driver_register, \
apr_driver_unregister)
#define module_gpr_driver(__gpr_driver) module_apr_driver(__gpr_driver)
int apr_send_pkt(struct apr_device *adev, struct apr_pkt *pkt);
gpr_port_t *gpr_alloc_port(gpr_device_t *gdev, struct device *dev,
gpr_port_cb cb, void *priv);
void gpr_free_port(gpr_port_t *port);
int gpr_send_port_pkt(gpr_port_t *port, struct gpr_pkt *pkt);
int gpr_send_pkt(gpr_device_t *gdev, struct gpr_pkt *pkt);
#endif /* __QCOM_APR_H_ */

208
include/uapi/sound/snd_ar_tokens.h Normal file
View File

@ -0,0 +1,208 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef __SND_AR_TOKENS_H__
#define __SND_AR_TOKENS_H__
#define APM_SUB_GRAPH_PERF_MODE_LOW_POWER 0x1
#define APM_SUB_GRAPH_PERF_MODE_LOW_LATENCY 0x2
#define APM_SUB_GRAPH_DIRECTION_TX 0x1
#define APM_SUB_GRAPH_DIRECTION_RX 0x2
/** Scenario ID Audio Playback */
#define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1
/* Scenario ID Audio Record */
#define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2
/* Scenario ID Voice call. */
#define APM_SUB_GRAPH_SID_VOICE_CALL 0x3
/* container capability ID Pre/Post Processing (PP) */
#define APM_CONTAINER_CAP_ID_PP 0x1
/* container capability ID Compression/Decompression (CD) */
#define APM_CONTAINER_CAP_ID_CD 0x2
/* container capability ID End Point(EP) */
#define APM_CONTAINER_CAP_ID_EP 0x3
/* container capability ID Offload (OLC) */
#define APM_CONTAINER_CAP_ID_OLC 0x4
/* container graph position Stream */
#define APM_CONT_GRAPH_POS_STREAM 0x1
/* container graph position Per Stream Per Device*/
#define APM_CONT_GRAPH_POS_PER_STR_PER_DEV 0x2
/* container graph position Stream-Device */
#define APM_CONT_GRAPH_POS_STR_DEV 0x3
/* container graph position Global Device */
#define APM_CONT_GRAPH_POS_GLOBAL_DEV 0x4
#define APM_PROC_DOMAIN_ID_MDSP 0x1
#define APM_PROC_DOMAIN_ID_ADSP 0x2
#define APM_PROC_DOMAIN_ID_SDSP 0x4
#define APM_PROC_DOMAIN_ID_CDSP 0x5
#define PCM_INTERLEAVED 1
#define PCM_DEINTERLEAVED_PACKED 2
#define PCM_DEINTERLEAVED_UNPACKED 3
#define AR_I2S_WS_SRC_EXTERNAL 0
#define AR_I2S_WS_SRC_INTERNAL 1
enum ar_event_types {
AR_EVENT_NONE = 0,
AR_PGA_DAPM_EVENT
};
/*
* Kcontrol IDs
*/
#define SND_SOC_AR_TPLG_FE_BE_GRAPH_CTL_MIX 256
#define SND_SOC_AR_TPLG_VOL_CTL 257
/**
* %AR_TKN_U32_SUB_GRAPH_INSTANCE_ID: Sub Graph Instance Id
*
* %AR_TKN_U32_SUB_GRAPH_PERF_MODE: Performance mode of subgraph
* APM_SUB_GRAPH_PERF_MODE_LOW_POWER = 1,
* APM_SUB_GRAPH_PERF_MODE_LOW_LATENCY = 2
*
* %AR_TKN_U32_SUB_GRAPH_DIRECTION: Direction of subgraph
* APM_SUB_GRAPH_DIRECTION_TX = 1,
* APM_SUB_GRAPH_DIRECTION_RX = 2
*
* %AR_TKN_U32_SUB_GRAPH_SCENARIO_ID: Scenario ID for subgraph
* APM_SUB_GRAPH_SID_AUDIO_PLAYBACK = 1,
* APM_SUB_GRAPH_SID_AUDIO_RECORD = 2,
* APM_SUB_GRAPH_SID_VOICE_CALL = 3
*
* %AR_TKN_U32_CONTAINER_INSTANCE_ID: Container Instance ID
*
* %AR_TKN_U32_CONTAINER_CAPABILITY_ID: Container capability ID
* APM_CONTAINER_CAP_ID_PP = 1,
* APM_CONTAINER_CAP_ID_CD = 2,
* APM_CONTAINER_CAP_ID_EP = 3,
* APM_CONTAINER_CAP_ID_OLC = 4
*
* %AR_TKN_U32_CONTAINER_STACK_SIZE: Stack size in the container.
*
* %AR_TKN_U32_CONTAINER_GRAPH_POS: Graph Position
* APM_CONT_GRAPH_POS_STREAM = 1,
* APM_CONT_GRAPH_POS_PER_STR_PER_DEV = 2,
* APM_CONT_GRAPH_POS_STR_DEV = 3,
* APM_CONT_GRAPH_POS_GLOBAL_DEV = 4
*
* %AR_TKN_U32_CONTAINER_PROC_DOMAIN: Processor domain of container
* APM_PROC_DOMAIN_ID_MDSP = 1,
* APM_PROC_DOMAIN_ID_ADSP = 2,
* APM_PROC_DOMAIN_ID_SDSP = 4,
* APM_PROC_DOMAIN_ID_CDSP = 5
*
* %AR_TKN_U32_MODULE_ID: Module ID
*
* %AR_TKN_U32_MODULE_INSTANCE_ID: Module Instance ID.
*
* %AR_TKN_U32_MODULE_MAX_IP_PORTS: Module maximum input ports
*
* %AR_TKN_U32_MODULE_MAX_OP_PORTS: Module maximum output ports.
*
* %AR_TKN_U32_MODULE_IN_PORTS: Number of in ports
*
* %AR_TKN_U32_MODULE_OUT_PORTS: Number of out ports.
*
* %AR_TKN_U32_MODULE_SRC_OP_PORT_ID: Source module output port ID
*
* %AR_TKN_U32_MODULE_DST_IN_PORT_ID: Destination module input port ID
*
* %AR_TKN_U32_MODULE_HW_IF_IDX: Interface index types for I2S/LPAIF
*
* %AR_TKN_U32_MODULE_HW_IF_TYPE: Interface type
* LPAIF = 0,
* LPAIF_RXTX = 1,
* LPAIF_WSA = 2,
* LPAIF_VA = 3,
* LPAIF_AXI = 4
*
* %AR_TKN_U32_MODULE_FMT_INTERLEAVE: PCM Interleaving
* PCM_INTERLEAVED = 1,
* PCM_DEINTERLEAVED_PACKED = 2,
* PCM_DEINTERLEAVED_UNPACKED = 3
*
* %AR_TKN_U32_MODULE_FMT_DATA: data format
* FIXED POINT = 1,
* IEC60958 PACKETIZED = 3,
* IEC60958 PACKETIZED NON LINEAR = 8,
* COMPR OVER PCM PACKETIZED = 7,
* IEC61937 PACKETIZED = 2,
* GENERIC COMPRESSED = 5
*
* %AR_TKN_U32_MODULE_FMT_SAMPLE_RATE: sample rate
*
* %AR_TKN_U32_MODULE_FMT_BIT_DEPTH: bit depth
*
* %AR_TKN_U32_MODULE_SD_LINE_IDX: I2S serial data line idx
* I2S_SD0 = 1,
* I2S_SD1 = 2,
* I2S_SD2 = 3,
* I2S_SD3 = 4,
* I2S_QUAD01 = 5,
* I2S_QUAD23 = 6,
* I2S_6CHS = 7,
* I2S_8CHS = 8
*
* %AR_TKN_U32_MODULE_WS_SRC: Word Select Source
* AR_I2S_WS_SRC_EXTERNAL = 0,
* AR_I2S_WS_SRC_INTERNAL = 1,
*
* %AR_TKN_U32_MODULE_FRAME_SZ_FACTOR: Frame size factor
*
* %AR_TKN_U32_MODULE_LOG_CODE: Log Module Code
*
* %AR_TKN_U32_MODULE_LOG_TAP_POINT_ID: logging tap point of this module
*
* %AR_TKN_U32_MODULE_LOG_MODE: logging mode
* LOG_WAIT = 0,
* LOG_IMMEDIATELY = 1
*
* %AR_TKN_DAI_INDEX: dai index
*
*/
/* DAI Tokens */
#define AR_TKN_DAI_INDEX 1
/* SUB GRAPH Tokens */
#define AR_TKN_U32_SUB_GRAPH_INSTANCE_ID 2
#define AR_TKN_U32_SUB_GRAPH_PERF_MODE 3
#define AR_TKN_U32_SUB_GRAPH_DIRECTION 4
#define AR_TKN_U32_SUB_GRAPH_SCENARIO_ID 5
/* Container Tokens */
#define AR_TKN_U32_CONTAINER_INSTANCE_ID 100
#define AR_TKN_U32_CONTAINER_CAPABILITY_ID 101
#define AR_TKN_U32_CONTAINER_STACK_SIZE 102
#define AR_TKN_U32_CONTAINER_GRAPH_POS 103
#define AR_TKN_U32_CONTAINER_PROC_DOMAIN 104
/* Module Tokens */
#define AR_TKN_U32_MODULE_ID 200
#define AR_TKN_U32_MODULE_INSTANCE_ID 201
#define AR_TKN_U32_MODULE_MAX_IP_PORTS 202
#define AR_TKN_U32_MODULE_MAX_OP_PORTS 203
#define AR_TKN_U32_MODULE_IN_PORTS 204
#define AR_TKN_U32_MODULE_OUT_PORTS 205
#define AR_TKN_U32_MODULE_SRC_OP_PORT_ID 206
#define AR_TKN_U32_MODULE_DST_IN_PORT_ID 207
#define AR_TKN_U32_MODULE_SRC_INSTANCE_ID 208
#define AR_TKN_U32_MODULE_DST_INSTANCE_ID 209
#define AR_TKN_U32_MODULE_HW_IF_IDX 250
#define AR_TKN_U32_MODULE_HW_IF_TYPE 251
#define AR_TKN_U32_MODULE_FMT_INTERLEAVE 252
#define AR_TKN_U32_MODULE_FMT_DATA 253
#define AR_TKN_U32_MODULE_FMT_SAMPLE_RATE 254
#define AR_TKN_U32_MODULE_FMT_BIT_DEPTH 255
#define AR_TKN_U32_MODULE_SD_LINE_IDX 256
#define AR_TKN_U32_MODULE_WS_SRC 257
#define AR_TKN_U32_MODULE_FRAME_SZ_FACTOR 258
#define AR_TKN_U32_MODULE_LOG_CODE 259
#define AR_TKN_U32_MODULE_LOG_TAP_POINT_ID 260
#define AR_TKN_U32_MODULE_LOG_MODE 261
#endif /* __SND_AR_TOKENS_H__ */

22
sound/soc/qcom/Kconfig
View File

@ -85,6 +85,25 @@ config SND_SOC_QDSP6_ASM_DAI
select SND_SOC_COMPRESS
tristate
config SND_SOC_QDSP6_APM_DAI
tristate
select SND_SOC_COMPRESS
config SND_SOC_QDSP6_APM_LPASS_DAI
tristate
config SND_SOC_QDSP6_APM
tristate
select SND_SOC_QDSP6_APM_DAI
select SND_SOC_QDSP6_APM_LPASS_DAI
config SND_SOC_QDSP6_PRM_LPASS_CLOCKS
tristate
config SND_SOC_QDSP6_PRM
tristate
select SND_SOC_QDSP6_PRM_LPASS_CLOCKS
config SND_SOC_QDSP6
tristate "SoC ALSA audio driver for QDSP6"
depends on QCOM_APR
@ -98,6 +117,9 @@ config SND_SOC_QDSP6
select SND_SOC_QDSP6_ROUTING
select SND_SOC_QDSP6_ASM
select SND_SOC_QDSP6_ASM_DAI
select SND_SOC_TOPOLOGY
select SND_SOC_QDSP6_APM
select SND_SOC_QDSP6_PRM
help
To add support for MSM QDSP6 Soc Audio.
This will enable sound soc platform specific

11
sound/soc/qcom/qdsp6/Makefile
View File

@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_SND_SOC_QDSP6_COMMON) += q6dsp-common.o
snd-q6dsp-common-objs := q6dsp-common.o q6dsp-lpass-ports.o q6dsp-lpass-clocks.o
snd-q6apm-objs := q6apm.o audioreach.o topology.o
obj-$(CONFIG_SND_SOC_QDSP6_COMMON) += snd-q6dsp-common.o
obj-$(CONFIG_SND_SOC_QDSP6_CORE) += q6core.o
obj-$(CONFIG_SND_SOC_QDSP6_AFE) += q6afe.o
obj-$(CONFIG_SND_SOC_QDSP6_AFE_DAI) += q6afe-dai.o
@ -8,3 +11,9 @@ obj-$(CONFIG_SND_SOC_QDSP6_ADM) += q6adm.o
obj-$(CONFIG_SND_SOC_QDSP6_ROUTING) += q6routing.o
obj-$(CONFIG_SND_SOC_QDSP6_ASM) += q6asm.o
obj-$(CONFIG_SND_SOC_QDSP6_ASM_DAI) += q6asm-dai.o
obj-$(CONFIG_SND_SOC_QDSP6_APM) += snd-q6apm.o
obj-$(CONFIG_SND_SOC_QDSP6_APM_DAI) += q6apm-dai.o
obj-$(CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI) += q6apm-lpass-dais.o
obj-$(CONFIG_SND_SOC_QDSP6_PRM) += q6prm.o
obj-$(CONFIG_SND_SOC_QDSP6_PRM_LPASS_CLOCKS) += q6prm-clocks.o

1130
sound/soc/qcom/qdsp6/audioreach.c Normal file
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File diff suppressed because it is too large Load Diff

726
sound/soc/qcom/qdsp6/audioreach.h Normal file
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@ -0,0 +1,726 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __AUDIOREACH_H__
#define __AUDIOREACH_H__
#include <linux/types.h>
#include <linux/soc/qcom/apr.h>
#include <sound/soc.h>
struct q6apm;
struct q6apm_graph;
/* Module IDs */
#define MODULE_ID_WR_SHARED_MEM_EP 0x07001000
#define MODULE_ID_RD_SHARED_MEM_EP 0x07001001
#define MODULE_ID_GAIN 0x07001002
#define MODULE_ID_PCM_CNV 0x07001003
#define MODULE_ID_PCM_ENC 0x07001004
#define MODULE_ID_PCM_DEC 0x07001005
#define MODULE_ID_CODEC_DMA_SINK 0x07001023
#define MODULE_ID_CODEC_DMA_SOURCE 0x07001024
#define MODULE_ID_I2S_SINK 0x0700100A
#define MODULE_ID_I2S_SOURCE 0x0700100B
#define MODULE_ID_DATA_LOGGING 0x0700101A
#define APM_CMD_GET_SPF_STATE 0x01001021
#define APM_CMD_RSP_GET_SPF_STATE 0x02001007
#define APM_MODULE_INSTANCE_ID 0x00000001
#define PRM_MODULE_INSTANCE_ID 0x00000002
#define AMDB_MODULE_INSTANCE_ID 0x00000003
#define VCPM_MODULE_INSTANCE_ID 0x00000004
#define AR_MODULE_INSTANCE_ID_START 0x00006000
#define AR_MODULE_INSTANCE_ID_END 0x00007000
#define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000
#define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000
#define AR_CONT_INSTANCE_ID_START 0x00005000
#define AR_CONT_INSTANCE_ID_END 0x00006000
#define AR_SG_INSTANCE_ID_START 0x00004000
#define APM_CMD_GRAPH_OPEN 0x01001000
#define APM_CMD_GRAPH_PREPARE 0x01001001
#define APM_CMD_GRAPH_START 0x01001002
#define APM_CMD_GRAPH_STOP 0x01001003
#define APM_CMD_GRAPH_CLOSE 0x01001004
#define APM_CMD_GRAPH_FLUSH 0x01001005
#define APM_CMD_SET_CFG 0x01001006
#define APM_CMD_GET_CFG 0x01001007
#define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C
#define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D
#define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001
#define APM_CMD_RSP_GET_CFG 0x02001000
#define APM_CMD_CLOSE_ALL 0x01001013
#define APM_CMD_REGISTER_SHARED_CFG 0x0100100A
#define APM_MEMORY_MAP_SHMEM8_4K_POOL 3
struct apm_cmd_shared_mem_map_regions {
uint16_t mem_pool_id;
uint16_t num_regions;
uint32_t property_flag;
} __packed;
struct apm_shared_map_region_payload {
uint32_t shm_addr_lsw;
uint32_t shm_addr_msw;
uint32_t mem_size_bytes;
} __packed;
struct apm_cmd_shared_mem_unmap_regions {
uint32_t mem_map_handle;
} __packed;
struct apm_cmd_rsp_shared_mem_map_regions {
uint32_t mem_map_handle;
} __packed;
/* APM module */
#define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005
#define APM_PARAM_ID_MODULE_LIST 0x08001002
struct apm_param_id_modules_list {
uint32_t num_modules_list;
} __packed;
#define APM_PARAM_ID_MODULE_PROP 0x08001003
struct apm_param_id_module_prop {
uint32_t num_modules_prop_cfg;
} __packed;
struct apm_module_prop_cfg {
uint32_t instance_id;
uint32_t num_props;
} __packed;
#define APM_PARAM_ID_MODULE_CONN 0x08001004
struct apm_param_id_module_conn {
uint32_t num_connections;
} __packed;
struct apm_module_conn_obj {
uint32_t src_mod_inst_id;
uint32_t src_mod_op_port_id;
uint32_t dst_mod_inst_id;
uint32_t dst_mod_ip_port_id;
} __packed;
#define APM_PARAM_ID_GAIN 0x08001006
struct param_id_gain_cfg {
uint16_t gain;
uint16_t reserved;
} __packed;
#define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008
struct param_id_pcm_output_format_cfg {
uint32_t data_format;
uint32_t fmt_id;
uint32_t payload_size;
} __packed;
struct payload_pcm_output_format_cfg {
uint16_t bit_width;
uint16_t alignment;
uint16_t bits_per_sample;
uint16_t q_factor;
uint16_t endianness;
uint16_t interleaved;
uint16_t reserved;
uint16_t num_channels;
uint8_t channel_mapping[];
} __packed;
#define PARAM_ID_ENC_BITRATE 0x08001052
struct param_id_enc_bitrate_param {
uint32_t bitrate;
} __packed;
#define DATA_FORMAT_FIXED_POINT 1
#define PCM_LSB_ALIGNED 1
#define PCM_MSB_ALIGNED 2
#define PCM_LITTLE_ENDIAN 1
#define PCM_BIT_ENDIAN 2
#define MEDIA_FMT_ID_PCM 0x09001000
#define PCM_CHANNEL_L 1
#define PCM_CHANNEL_R 2
#define SAMPLE_RATE_48K 48000
#define BIT_WIDTH_16 16
#define APM_PARAM_ID_PROP_PORT_INFO 0x08001015
struct apm_modules_prop_info {
uint32_t max_ip_port;
uint32_t max_op_port;
} __packed;
/* Shared memory module */
#define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000
#define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31)
#define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30)
#define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29)
#define WR_SH_MEM_EP_EOF_FLAG BIT(4)
struct apm_data_cmd_wr_sh_mem_ep_data_buffer {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t buf_size;
uint32_t timestamp_lsw;
uint32_t timestamp_msw;
uint32_t flags;
} __packed;
#define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A
struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t buf_size;
uint32_t timestamp_lsw;
uint32_t timestamp_msw;
uint32_t flags;
uint32_t md_addr_lsw;
uint32_t md_addr_msw;
uint32_t md_map_handle;
uint32_t md_buf_size;
} __packed;
#define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000
struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t status;
} __packed;
#define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004
struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t status;
uint32_t md_buf_addr_lsw;
uint32_t md_buf_addr_msw;
uint32_t md_mem_map_handle;
uint32_t md_status;
} __packed;
#define PARAM_ID_MEDIA_FORMAT 0x0800100C
#define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001
struct apm_media_format {
uint32_t data_format;
uint32_t fmt_id;
uint32_t payload_size;
} __packed;
#define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002
#define WR_SH_MEM_EP_EOS_POLICY_LAST 1
#define WR_SH_MEM_EP_EOS_POLICY_EACH 2
struct data_cmd_wr_sh_mem_ep_eos {
uint32_t policy;
} __packed;
#define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003
struct data_cmd_rd_sh_mem_ep_data_buffer {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t buf_size;
} __packed;
#define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002
struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done {
uint32_t status;
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t data_size;
uint32_t offset;
uint32_t timestamp_lsw;
uint32_t timestamp_msw;
uint32_t flags;
uint32_t num_frames;
} __packed;
#define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B
struct data_cmd_rd_sh_mem_ep_data_buffer_v2 {
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t buf_size;
uint32_t md_buf_addr_lsw;
uint32_t md_buf_addr_msw;
uint32_t md_mem_map_handle;
uint32_t md_buf_size;
} __packed;
#define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005
struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 {
uint32_t status;
uint32_t buf_addr_lsw;
uint32_t buf_addr_msw;
uint32_t mem_map_handle;
uint32_t data_size;
uint32_t offset;
uint32_t timestamp_lsw;
uint32_t timestamp_msw;
uint32_t flags;
uint32_t num_frames;
uint32_t md_status;
uint32_t md_buf_addr_lsw;
uint32_t md_buf_addr_msw;
uint32_t md_mem_map_handle;
uint32_t md_size;
} __packed;
#define PARAM_ID_RD_SH_MEM_CFG 0x08001007
struct param_id_rd_sh_mem_cfg {
uint32_t num_frames_per_buffer;
uint32_t metadata_control_flags;
} __packed;
#define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001
struct data_cmd_wr_sh_mem_ep_eos_rendered {
uint32_t module_instance_id;
uint32_t render_status;
} __packed;
#define MODULE_ID_WR_SHARED_MEM_EP 0x07001000
struct apm_cmd_header {
uint32_t payload_address_lsw;
uint32_t payload_address_msw;
uint32_t mem_map_handle;
uint32_t payload_size;
} __packed;
#define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header)
struct apm_module_param_data {
uint32_t module_instance_id;
uint32_t param_id;
uint32_t param_size;
uint32_t error_code;
} __packed;
#define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data)
struct apm_module_param_shared_data {
uint32_t param_id;
uint32_t param_size;
} __packed;
struct apm_prop_data {
uint32_t prop_id;
uint32_t prop_size;
} __packed;
/* Sub-Graph Properties */
#define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001
struct apm_param_id_sub_graph_cfg {
uint32_t num_sub_graphs;
} __packed;
struct apm_sub_graph_cfg {
uint32_t sub_graph_id;
uint32_t num_sub_graph_prop;
} __packed;
#define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E
struct apm_sg_prop_id_perf_mode {
uint32_t perf_mode;
} __packed;
#define APM_SG_PROP_ID_PERF_MODE_SIZE 4
#define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F
struct apm_sg_prop_id_direction {
uint32_t direction;
} __packed;
#define APM_SG_PROP_ID_DIR_SIZE 4
#define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010
#define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1
#define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2
#define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3
struct apm_sg_prop_id_scenario_id {
uint32_t scenario_id;
} __packed;
#define APM_SG_PROP_ID_SID_SIZE 4
/* container api */
#define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000
struct apm_param_id_container_cfg {
uint32_t num_containers;
} __packed;
struct apm_container_cfg {
uint32_t container_id;
uint32_t num_prop;
} __packed;
struct apm_cont_capability {
uint32_t capability_id;
} __packed;
#define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011
#define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8
#define APM_PROP_ID_INVALID 0x0
#define APM_CONTAINER_CAP_ID_PP 0x1
#define APM_CONTAINER_CAP_ID_PP 0x1
struct apm_cont_prop_id_cap_list {
uint32_t num_capability_id;
} __packed;
#define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012
struct apm_cont_prop_id_graph_pos {
uint32_t graph_pos;
} __packed;
#define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013
struct apm_cont_prop_id_stack_size {
uint32_t stack_size;
} __packed;
#define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014
struct apm_cont_prop_id_domain {
uint32_t proc_domain;
} __packed;
#define CONFIG_I2S_WS_SRC_EXTERNAL 0x0
#define CONFIG_I2S_WS_SRC_INTERNAL 0x1
#define PARAM_ID_I2S_INTF_CFG 0x08001019
struct param_id_i2s_intf_cfg {
uint32_t lpaif_type;
uint32_t intf_idx;
uint16_t sd_line_idx;
uint16_t ws_src;
} __packed;
#define I2S_INTF_TYPE_PRIMARY 0
#define I2S_INTF_TYPE_SECOINDARY 1
#define I2S_INTF_TYPE_TERTINARY 2
#define I2S_INTF_TYPE_QUATERNARY 3
#define I2S_INTF_TYPE_QUINARY 4
#define I2S_SD0 1
#define I2S_SD1 2
#define I2S_SD2 3
#define I2S_SD3 4
#define PORT_ID_I2S_INPUT 2
#define PORT_ID_I2S_OUPUT 1
#define I2S_STACK_SIZE 2048
#define PARAM_ID_HW_EP_MF_CFG 0x08001017
struct param_id_hw_ep_mf {
uint32_t sample_rate;
uint16_t bit_width;
uint16_t num_channels;
uint32_t data_format;
} __packed;
#define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018
struct param_id_fram_size_factor {
uint32_t frame_size_factor;
} __packed;
#define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB
struct apm_cont_prop_id_parent_container {
uint32_t parent_container_id;
} __packed;
#define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174
#define APM_CONT_HEAP_DEFAULT 0x1
#define APM_CONT_HEAP_LOW_POWER 0x2
struct apm_cont_prop_id_headp_id {
uint32_t heap_id;
} __packed;
struct apm_modules_list {
uint32_t sub_graph_id;
uint32_t container_id;
uint32_t num_modules;
} __packed;
struct apm_module_obj {
uint32_t module_id;
uint32_t instance_id;
} __packed;
#define APM_MODULE_PROP_ID_PORT_INFO 0x08001015
#define APM_MODULE_PROP_ID_PORT_INFO_SZ 8
struct apm_module_prop_id_port_info {
uint32_t max_ip_port;
uint32_t max_op_port;
} __packed;
#define DATA_LOGGING_MAX_INPUT_PORTS 0x1
#define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1
#define DATA_LOGGING_STACK_SIZE 2048
#define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031
struct data_logging_config {
uint32_t log_code;
uint32_t log_tap_point_id;
uint32_t mode;
} __packed;
#define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024
struct param_id_mfc_media_format {
uint32_t sample_rate;
uint16_t bit_width;
uint16_t num_channels;
uint16_t channel_mapping[];
} __packed;
struct media_format {
uint32_t data_format;
uint32_t fmt_id;
uint32_t payload_size;
} __packed;
struct payload_media_fmt_pcm {
uint32_t sample_rate;
uint16_t bit_width;
uint16_t alignment;
uint16_t bits_per_sample;
uint16_t q_factor;
uint16_t endianness;
uint16_t num_channels;
uint8_t channel_mapping[];
} __packed;
#define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063
struct param_id_codec_dma_intf_cfg {
/* 1 - RXTX
* 2 - WSA
* 3 - VA
* 4 - AXI
*/
uint32_t lpaif_type;
/*
* RX0 | TX0 = 1
* RX1 | TX1 = 2
* RX2 | TX2 = 3... so on
*/
uint32_t intf_index;
uint32_t active_channels_mask;
} __packed;
struct audio_hw_clk_cfg {
uint32_t clock_id;
uint32_t clock_freq;
uint32_t clock_attri;
uint32_t clock_root;
} __packed;
#define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176
#define AR_HW_EP_POWER_MODE_0 0 /* default */
#define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */
#define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */
struct param_id_hw_ep_power_mode_cfg {
uint32_t power_mode;
} __packed;
#define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233
#define AR_HW_EP_DMA_DATA_ALIGN_MSB 0
#define AR_HW_EP_DMA_DATA_ALIGN_LSB 1
#define AR_PCM_MAX_NUM_CHANNEL 8
struct param_id_hw_ep_dma_data_align {
uint32_t dma_data_align;
} __packed;
#define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035
#define VOL_CTRL_DEFAULT_GAIN 0x2000
struct param_id_vol_ctrl_master_gain {
uint16_t master_gain;
uint16_t reserved;
} __packed;
/* Graph */
struct audioreach_connection {
/* Connections */
uint32_t src_mod_inst_id;
uint32_t src_mod_op_port_id;
uint32_t dst_mod_inst_id;
uint32_t dst_mod_ip_port_id;
struct list_head node;
};
struct audioreach_graph_info {
int id;
uint32_t num_sub_graphs;
struct list_head sg_list;
struct list_head connection_list;
};
struct audioreach_sub_graph {
uint32_t sub_graph_id;
uint32_t perf_mode;
uint32_t direction;
uint32_t scenario_id;
struct list_head node;
struct audioreach_graph_info *info;
uint32_t num_containers;
struct list_head container_list;
};
struct audioreach_container {
uint32_t container_id;
uint32_t capability_id;
uint32_t graph_pos;
uint32_t stack_size;
uint32_t proc_domain;
struct list_head node;
uint32_t num_modules;
struct list_head modules_list;
struct audioreach_sub_graph *sub_graph;
};
struct audioreach_module {
uint32_t module_id;
uint32_t instance_id;
uint32_t max_ip_port;
uint32_t max_op_port;
uint32_t in_port;
uint32_t out_port;
/* Connections */
uint32_t src_mod_inst_id;
uint32_t src_mod_op_port_id;
uint32_t dst_mod_inst_id;
uint32_t dst_mod_ip_port_id;
/* Format specifics */
uint32_t ch_fmt;
uint32_t rate;
uint32_t bit_depth;
/* I2S module */
uint32_t hw_interface_idx;
uint32_t sd_line_idx;
uint32_t ws_src;
uint32_t frame_size_factor;
uint32_t data_format;
uint32_t hw_interface_type;
/* PCM module specific */
uint32_t interleave_type;
/* GAIN/Vol Control Module */
uint16_t gain;
/* Logging */
uint32_t log_code;
uint32_t log_tap_point_id;
uint32_t log_mode;
/* bookkeeping */
struct list_head node;
struct audioreach_container *container;
struct snd_soc_dapm_widget *widget;
};
struct audioreach_module_config {
int direction;
u32 sample_rate;
u16 bit_width;
u16 bits_per_sample;
u16 data_format;
u16 num_channels;
u16 active_channels_mask;
u32 sd_line_mask;
int fmt;
u8 channel_map[AR_PCM_MAX_NUM_CHANNEL];
};
/* Packet Allocation routines */
void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t
token);
void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode,
uint32_t token, uint32_t src_port,
uint32_t dest_port);
void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token,
uint32_t src_port);
void *audioreach_alloc_pkt(int payload_size, uint32_t opcode,
uint32_t token, uint32_t src_port,
uint32_t dest_port);
void *audioreach_alloc_graph_pkt(struct q6apm *apm,
struct list_head *sg_list,
int graph_id);
/* Topology specific */
int audioreach_tplg_init(struct snd_soc_component *component);
/* Module specific */
void audioreach_graph_free_buf(struct q6apm_graph *graph);
int audioreach_map_memory_regions(struct q6apm_graph *graph,
unsigned int dir, size_t period_sz,
unsigned int periods,
bool is_contiguous);
int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result,
struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait,
struct gpr_pkt *pkt, uint32_t rsp_opcode);
int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt,
uint32_t rsp_opcode);
int audioreach_set_media_format(struct q6apm_graph *graph,
struct audioreach_module *module,
struct audioreach_module_config *cfg);
int audioreach_shared_memory_send_eos(struct q6apm_graph *graph);
int audioreach_gain_set_vol_ctrl(struct q6apm *apm,
struct audioreach_module *module, int vol);
struct audioreach_module *audioreach_get_container_last_module(
struct audioreach_container *container);
struct audioreach_module *audioreach_get_container_first_module(
struct audioreach_container *container);
struct audioreach_module *audioreach_get_container_next_module(
struct audioreach_container *container,
struct audioreach_module *module);
#define list_for_each_container_module(mod, cont) \
for (mod = audioreach_get_container_first_module(cont); mod != NULL; \
mod = audioreach_get_container_next_module(cont, mod))
#endif /* __AUDIOREACH_H__ */

187
sound/soc/qcom/qdsp6/q6afe-clocks.c
View File

@ -7,115 +7,18 @@
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/slab.h>
#include "q6dsp-lpass-clocks.h"
#include "q6afe.h"
#define Q6AFE_CLK(id) { \
.clk_id = id, \
.afe_clk_id = Q6AFE_##id, \
.q6dsp_clk_id = Q6AFE_##id, \
.name = #id, \
.rate = 19200000, \
}
#define Q6AFE_VOTE_CLK(id, blkid, n) { \
.clk_id = id, \
.afe_clk_id = blkid, \
.name = n, \
}
struct q6afe_clk_init {
int clk_id;
int afe_clk_id;
char *name;
int rate;
};
struct q6afe_clk {
struct device *dev;
int afe_clk_id;
int attributes;
int rate;
uint32_t handle;
struct clk_hw hw;
};
#define to_q6afe_clk(_hw) container_of(_hw, struct q6afe_clk, hw)
struct q6afe_cc {
struct device *dev;
struct q6afe_clk *clks[Q6AFE_MAX_CLK_ID];
};
static int clk_q6afe_prepare(struct clk_hw *hw)
{
struct q6afe_clk *clk = to_q6afe_clk(hw);
return q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes,
Q6AFE_LPASS_CLK_ROOT_DEFAULT, clk->rate);
}
static void clk_q6afe_unprepare(struct clk_hw *hw)
{
struct q6afe_clk *clk = to_q6afe_clk(hw);
q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes,
Q6AFE_LPASS_CLK_ROOT_DEFAULT, 0);
}
static int clk_q6afe_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct q6afe_clk *clk = to_q6afe_clk(hw);
clk->rate = rate;
return 0;
}
static unsigned long clk_q6afe_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct q6afe_clk *clk = to_q6afe_clk(hw);
return clk->rate;
}
static long clk_q6afe_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
return rate;
}
static const struct clk_ops clk_q6afe_ops = {
.prepare = clk_q6afe_prepare,
.unprepare = clk_q6afe_unprepare,
.set_rate = clk_q6afe_set_rate,
.round_rate = clk_q6afe_round_rate,
.recalc_rate = clk_q6afe_recalc_rate,
};
static int clk_vote_q6afe_block(struct clk_hw *hw)
{
struct q6afe_clk *clk = to_q6afe_clk(hw);
return q6afe_vote_lpass_core_hw(clk->dev, clk->afe_clk_id,
clk_hw_get_name(&clk->hw), &clk->handle);
}
static void clk_unvote_q6afe_block(struct clk_hw *hw)
{
struct q6afe_clk *clk = to_q6afe_clk(hw);
q6afe_unvote_lpass_core_hw(clk->dev, clk->afe_clk_id, clk->handle);
}
static const struct clk_ops clk_vote_q6afe_ops = {
.prepare = clk_vote_q6afe_block,
.unprepare = clk_unvote_q6afe_block,
};
static const struct q6afe_clk_init q6afe_clks[] = {
static const struct q6dsp_clk_init q6afe_clks[] = {
Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
@ -176,88 +79,28 @@ static const struct q6afe_clk_init q6afe_clks[] = {
Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
Q6AFE_VOTE_CLK(LPASS_HW_AVTIMER_VOTE,
Q6DSP_VOTE_CLK(LPASS_HW_AVTIMER_VOTE,
Q6AFE_LPASS_CORE_AVTIMER_BLOCK,
"LPASS_AVTIMER_MACRO"),
Q6AFE_VOTE_CLK(LPASS_HW_MACRO_VOTE,
Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE,
Q6AFE_LPASS_CORE_HW_MACRO_BLOCK,
"LPASS_HW_MACRO"),
Q6AFE_VOTE_CLK(LPASS_HW_DCODEC_VOTE,
Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE,
Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK,
"LPASS_HW_DCODEC"),
};
static struct clk_hw *q6afe_of_clk_hw_get(struct of_phandle_args *clkspec,
void *data)
{
struct q6afe_cc *cc = data;
unsigned int idx = clkspec->args[0];
unsigned int attr = clkspec->args[1];
if (idx >= Q6AFE_MAX_CLK_ID || attr > LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR) {
dev_err(cc->dev, "Invalid clk specifier (%d, %d)\n", idx, attr);
return ERR_PTR(-EINVAL);
}
if (cc->clks[idx]) {
cc->clks[idx]->attributes = attr;
return &cc->clks[idx]->hw;
}
return ERR_PTR(-ENOENT);
}
static int q6afe_clock_dev_probe(struct platform_device *pdev)
{
struct q6afe_cc *cc;
struct device *dev = &pdev->dev;
int i, ret;
cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
if (!cc)
return -ENOMEM;
cc->dev = dev;
for (i = 0; i < ARRAY_SIZE(q6afe_clks); i++) {
unsigned int id = q6afe_clks[i].clk_id;
struct clk_init_data init = {
.name = q6afe_clks[i].name,
};
struct q6afe_clk *clk;
clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
if (!clk)
return -ENOMEM;
clk->dev = dev;
clk->afe_clk_id = q6afe_clks[i].afe_clk_id;
clk->rate = q6afe_clks[i].rate;
clk->hw.init = &init;
if (clk->rate)
init.ops = &clk_q6afe_ops;
else
init.ops = &clk_vote_q6afe_ops;
cc->clks[id] = clk;
ret = devm_clk_hw_register(dev, &clk->hw);
if (ret)
return ret;
}
ret = devm_of_clk_add_hw_provider(dev, q6afe_of_clk_hw_get, cc);
if (ret)
return ret;
dev_set_drvdata(dev, cc);
return 0;
}
static const struct q6dsp_clk_desc q6dsp_clk_q6afe __maybe_unused = {
.clks = q6afe_clks,
.num_clks = ARRAY_SIZE(q6afe_clks),
.lpass_set_clk = q6afe_set_lpass_clock,
.lpass_vote_clk = q6afe_vote_lpass_core_hw,
.lpass_unvote_clk = q6afe_unvote_lpass_core_hw,
};
#ifdef CONFIG_OF
static const struct of_device_id q6afe_clock_device_id[] = {
{ .compatible = "qcom,q6afe-clocks" },
{ .compatible = "qcom,q6afe-clocks", .data = &q6dsp_clk_q6afe },
{},
};
MODULE_DEVICE_TABLE(of, q6afe_clock_device_id);
@ -268,7 +111,7 @@ static struct platform_driver q6afe_clock_platform_driver = {
.name = "q6afe-clock",
.of_match_table = of_match_ptr(q6afe_clock_device_id),
},
.probe = q6afe_clock_dev_probe,
.probe = q6dsp_clock_dev_probe,
};
module_platform_driver(q6afe_clock_platform_driver);

687
sound/soc/qcom/qdsp6/q6afe-dai.c
View File

@ -11,91 +11,9 @@
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include "q6dsp-lpass-ports.h"
#include "q6afe.h"
#define Q6AFE_TDM_PB_DAI(pre, num, did) { \
.playback = { \
.stream_name = pre" TDM"#num" Playback", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.ops = &q6tdm_ops, \
.id = did, \
.probe = msm_dai_q6_dai_probe, \
.remove = msm_dai_q6_dai_remove, \
}
#define Q6AFE_TDM_CAP_DAI(pre, num, did) { \
.capture = { \
.stream_name = pre" TDM"#num" Capture", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.ops = &q6tdm_ops, \
.id = did, \
.probe = msm_dai_q6_dai_probe, \
.remove = msm_dai_q6_dai_remove, \
}
#define Q6AFE_CDC_DMA_RX_DAI(did) { \
.playback = { \
.stream_name = #did" Playback", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.ops = &q6dma_ops, \
.id = did, \
.probe = msm_dai_q6_dai_probe, \
.remove = msm_dai_q6_dai_remove, \
}
#define Q6AFE_CDC_DMA_TX_DAI(did) { \
.capture = { \
.stream_name = #did" Capture", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.ops = &q6dma_ops, \
.id = did, \
.probe = msm_dai_q6_dai_probe, \
.remove = msm_dai_q6_dai_remove, \
}
struct q6afe_dai_priv_data {
uint32_t sd_line_mask;
@ -784,591 +702,6 @@ static int msm_dai_q6_dai_remove(struct snd_soc_dai *dai)
return 0;
}
static struct snd_soc_dai_driver q6afe_dais[] = {
{
.playback = {
.stream_name = "HDMI Playback",
.rates = SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 2,
.channels_max = 8,
.rate_max = 192000,
.rate_min = 48000,
},
.ops = &q6hdmi_ops,
.id = HDMI_RX,
.name = "HDMI",
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.name = "SLIMBUS_0_RX",
.ops = &q6slim_ops,
.id = SLIMBUS_0_RX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.playback = {
.stream_name = "Slimbus Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.name = "SLIMBUS_0_TX",
.ops = &q6slim_ops,
.id = SLIMBUS_0_TX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.capture = {
.stream_name = "Slimbus Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus1 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_1_RX",
.ops = &q6slim_ops,
.id = SLIMBUS_1_RX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.name = "SLIMBUS_1_TX",
.ops = &q6slim_ops,
.id = SLIMBUS_1_TX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.capture = {
.stream_name = "Slimbus1 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus2 Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_2_RX",
.ops = &q6slim_ops,
.id = SLIMBUS_2_RX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.name = "SLIMBUS_2_TX",
.ops = &q6slim_ops,
.id = SLIMBUS_2_TX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.capture = {
.stream_name = "Slimbus2 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus3 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_3_RX",
.ops = &q6slim_ops,
.id = SLIMBUS_3_RX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.name = "SLIMBUS_3_TX",
.ops = &q6slim_ops,
.id = SLIMBUS_3_TX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.capture = {
.stream_name = "Slimbus3 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus4 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_4_RX",
.ops = &q6slim_ops,
.id = SLIMBUS_4_RX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.name = "SLIMBUS_4_TX",
.ops = &q6slim_ops,
.id = SLIMBUS_4_TX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.capture = {
.stream_name = "Slimbus4 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus5 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_5_RX",
.ops = &q6slim_ops,
.id = SLIMBUS_5_RX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.name = "SLIMBUS_5_TX",
.ops = &q6slim_ops,
.id = SLIMBUS_5_TX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.capture = {
.stream_name = "Slimbus5 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus6 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.ops = &q6slim_ops,
.name = "SLIMBUS_6_RX",
.id = SLIMBUS_6_RX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.name = "SLIMBUS_6_TX",
.ops = &q6slim_ops,
.id = SLIMBUS_6_TX,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.capture = {
.stream_name = "Slimbus6 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Primary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = PRIMARY_MI2S_RX,
.name = "PRI_MI2S_RX",
.ops = &q6i2s_ops,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.capture = {
.stream_name = "Primary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = PRIMARY_MI2S_TX,
.name = "PRI_MI2S_TX",
.ops = &q6i2s_ops,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.playback = {
.stream_name = "Secondary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "SEC_MI2S_RX",
.id = SECONDARY_MI2S_RX,
.ops = &q6i2s_ops,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.capture = {
.stream_name = "Secondary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = SECONDARY_MI2S_TX,
.name = "SEC_MI2S_TX",
.ops = &q6i2s_ops,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.playback = {
.stream_name = "Tertiary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "TERT_MI2S_RX",
.id = TERTIARY_MI2S_RX,
.ops = &q6i2s_ops,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.capture = {
.stream_name = "Tertiary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = TERTIARY_MI2S_TX,
.name = "TERT_MI2S_TX",
.ops = &q6i2s_ops,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.playback = {
.stream_name = "Quaternary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "QUAT_MI2S_RX",
.id = QUATERNARY_MI2S_RX,
.ops = &q6i2s_ops,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.capture = {
.stream_name = "Quaternary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = QUATERNARY_MI2S_TX,
.name = "QUAT_MI2S_TX",
.ops = &q6i2s_ops,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.playback = {
.stream_name = "Quinary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
.id = QUINARY_MI2S_RX,
.name = "QUIN_MI2S_RX",
.ops = &q6i2s_ops,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
}, {
.capture = {
.stream_name = "Quinary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = QUINARY_MI2S_TX,
.name = "QUIN_MI2S_TX",
.ops = &q6i2s_ops,
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
},
Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Primary", 2, PRIMARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Primary", 3, PRIMARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Primary", 4, PRIMARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Primary", 5, PRIMARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Primary", 6, PRIMARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Primary", 7, PRIMARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Primary", 0, PRIMARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Primary", 1, PRIMARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Primary", 2, PRIMARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Primary", 3, PRIMARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Primary", 4, PRIMARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Primary", 5, PRIMARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Primary", 6, PRIMARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Primary", 7, PRIMARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Secondary", 0, SECONDARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Secondary", 1, SECONDARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Secondary", 2, SECONDARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Secondary", 3, SECONDARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Secondary", 4, SECONDARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Secondary", 5, SECONDARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Secondary", 6, SECONDARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Secondary", 7, SECONDARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Secondary", 0, SECONDARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Secondary", 1, SECONDARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Secondary", 2, SECONDARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Secondary", 3, SECONDARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Secondary", 4, SECONDARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Secondary", 5, SECONDARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Secondary", 6, SECONDARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Secondary", 7, SECONDARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Tertiary", 0, TERTIARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Tertiary", 1, TERTIARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Tertiary", 2, TERTIARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Tertiary", 3, TERTIARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Tertiary", 4, TERTIARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Tertiary", 5, TERTIARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Tertiary", 6, TERTIARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Tertiary", 7, TERTIARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Tertiary", 0, TERTIARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Tertiary", 1, TERTIARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Tertiary", 2, TERTIARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Tertiary", 3, TERTIARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Tertiary", 4, TERTIARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Tertiary", 5, TERTIARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Tertiary", 6, TERTIARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Tertiary", 7, TERTIARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Quaternary", 0, QUATERNARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Quaternary", 1, QUATERNARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Quaternary", 2, QUATERNARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Quaternary", 3, QUATERNARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Quaternary", 4, QUATERNARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Quaternary", 5, QUATERNARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Quaternary", 6, QUATERNARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Quaternary", 7, QUATERNARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Quaternary", 0, QUATERNARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Quaternary", 1, QUATERNARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Quaternary", 2, QUATERNARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Quaternary", 3, QUATERNARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Quaternary", 4, QUATERNARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Quaternary", 5, QUATERNARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Quaternary", 6, QUATERNARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Quaternary", 7, QUATERNARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Quinary", 0, QUINARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Quinary", 1, QUINARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Quinary", 2, QUINARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Quinary", 3, QUINARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Quinary", 4, QUINARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Quinary", 5, QUINARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Quinary", 6, QUINARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Quinary", 7, QUINARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Quinary", 0, QUINARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Quinary", 1, QUINARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Quinary", 2, QUINARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Quinary", 3, QUINARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Quinary", 4, QUINARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Quinary", 5, QUINARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Quinary", 6, QUINARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Quinary", 7, QUINARY_TDM_TX_7),
{
.playback = {
.stream_name = "Display Port Playback",
.rates = SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 2,
.channels_max = 8,
.rate_max = 192000,
.rate_min = 48000,
},
.ops = &q6hdmi_ops,
.id = DISPLAY_PORT_RX,
.name = "DISPLAY_PORT",
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
},
Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_0),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_1),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_0),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_1),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_2),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_3),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_3),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_4),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_4),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_5),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_5),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_6),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_7),
};
static int q6afe_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name)
{
int id = args->args[0];
int ret = -EINVAL;
int i;
for (i = 0; i < ARRAY_SIZE(q6afe_dais); i++) {
if (q6afe_dais[i].id == id) {
*dai_name = q6afe_dais[i].name;
ret = 0;
break;
}
}
return ret;
}
static const struct snd_soc_dapm_widget q6afe_dai_widgets[] = {
SND_SOC_DAPM_AIF_IN("HDMI_RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SLIMBUS_0_RX", NULL, 0, SND_SOC_NOPM, 0, 0),
@ -1627,7 +960,7 @@ static const struct snd_soc_component_driver q6afe_dai_component = {
.num_dapm_widgets = ARRAY_SIZE(q6afe_dai_widgets),
.dapm_routes = q6afe_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(q6afe_dapm_routes),
.of_xlate_dai_name = q6afe_of_xlate_dai_name,
.of_xlate_dai_name = q6dsp_audio_ports_of_xlate_dai_name,
};
@ -1715,19 +1048,29 @@ static void of_q6afe_parse_dai_data(struct device *dev,
static int q6afe_dai_dev_probe(struct platform_device *pdev)
{
struct q6dsp_audio_port_dai_driver_config cfg;
struct snd_soc_dai_driver *dais;
struct q6afe_dai_data *dai_data;
struct device *dev = &pdev->dev;
int num_dais;
dai_data = devm_kzalloc(dev, sizeof(*dai_data), GFP_KERNEL);
if (!dai_data)
return -ENOMEM;
dev_set_drvdata(dev, dai_data);
of_q6afe_parse_dai_data(dev, dai_data);
return devm_snd_soc_register_component(dev, &q6afe_dai_component,
q6afe_dais, ARRAY_SIZE(q6afe_dais));
cfg.probe = msm_dai_q6_dai_probe;
cfg.remove = msm_dai_q6_dai_remove;
cfg.q6hdmi_ops = &q6hdmi_ops;
cfg.q6slim_ops = &q6slim_ops;
cfg.q6i2s_ops = &q6i2s_ops;
cfg.q6tdm_ops = &q6tdm_ops;
cfg.q6dma_ops = &q6dma_ops;
dais = q6dsp_audio_ports_set_config(dev, &cfg, &num_dais);
return devm_snd_soc_register_component(dev, &q6afe_dai_component, dais, num_dais);
}
#ifdef CONFIG_OF

416
sound/soc/qcom/qdsp6/q6apm-dai.c Normal file
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@ -0,0 +1,416 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <linux/init.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include <asm/dma.h>
#include <linux/dma-mapping.h>
#include <linux/of_device.h>
#include <sound/pcm_params.h>
#include "q6apm.h"
#define DRV_NAME "q6apm-dai"
#define PLAYBACK_MIN_NUM_PERIODS 2
#define PLAYBACK_MAX_NUM_PERIODS 8
#define PLAYBACK_MAX_PERIOD_SIZE 65536
#define PLAYBACK_MIN_PERIOD_SIZE 128
#define CAPTURE_MIN_NUM_PERIODS 2
#define CAPTURE_MAX_NUM_PERIODS 8
#define CAPTURE_MAX_PERIOD_SIZE 4096
#define CAPTURE_MIN_PERIOD_SIZE 320
#define BUFFER_BYTES_MAX (PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE)
#define BUFFER_BYTES_MIN (PLAYBACK_MIN_NUM_PERIODS * PLAYBACK_MIN_PERIOD_SIZE)
#define SID_MASK_DEFAULT 0xF
enum stream_state {
Q6APM_STREAM_IDLE = 0,
Q6APM_STREAM_STOPPED,
Q6APM_STREAM_RUNNING,
};
struct q6apm_dai_rtd {
struct snd_pcm_substream *substream;
struct snd_compr_stream *cstream;
struct snd_compr_params codec_param;
struct snd_dma_buffer dma_buffer;
phys_addr_t phys;
unsigned int pcm_size;
unsigned int pcm_count;
unsigned int pos; /* Buffer position */
unsigned int periods;
unsigned int bytes_sent;
unsigned int bytes_received;
unsigned int copied_total;
uint16_t bits_per_sample;
uint16_t source; /* Encoding source bit mask */
uint16_t session_id;
enum stream_state state;
struct q6apm_graph *graph;
};
struct q6apm_dai_data {
long long sid;
};
static struct snd_pcm_hardware q6apm_dai_hardware_capture = {
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME),
.formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE),
.rates = SNDRV_PCM_RATE_8000_48000,
.rate_min = 8000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 4,
.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
.fifo_size = 0,
};
static struct snd_pcm_hardware q6apm_dai_hardware_playback = {
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME),
.formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE),
.rates = SNDRV_PCM_RATE_8000_192000,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 2,
.channels_max = 8,
.buffer_bytes_max = (PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE),
.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
.periods_min = PLAYBACK_MIN_NUM_PERIODS,
.periods_max = PLAYBACK_MAX_NUM_PERIODS,
.fifo_size = 0,
};
static void event_handler(uint32_t opcode, uint32_t token, uint32_t *payload, void *priv)
{
struct q6apm_dai_rtd *prtd = priv;
struct snd_pcm_substream *substream = prtd->substream;
switch (opcode) {
case APM_CLIENT_EVENT_CMD_EOS_DONE:
prtd->state = Q6APM_STREAM_STOPPED;
break;
case APM_CLIENT_EVENT_DATA_WRITE_DONE:
prtd->pos += prtd->pcm_count;
snd_pcm_period_elapsed(substream);
if (prtd->state == Q6APM_STREAM_RUNNING)
q6apm_write_async(prtd->graph, prtd->pcm_count, 0, 0, 0);
break;
case APM_CLIENT_EVENT_DATA_READ_DONE:
prtd->pos += prtd->pcm_count;
snd_pcm_period_elapsed(substream);
if (prtd->state == Q6APM_STREAM_RUNNING)
q6apm_read(prtd->graph);
break;
default:
break;
}
}
static int q6apm_dai_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
struct audioreach_module_config cfg;
struct device *dev = component->dev;
struct q6apm_dai_data *pdata;
int ret;
pdata = snd_soc_component_get_drvdata(component);
if (!pdata)
return -EINVAL;
if (!prtd || !prtd->graph) {
dev_err(dev, "%s: private data null or audio client freed\n", __func__);
return -EINVAL;
}
cfg.direction = substream->stream;
cfg.sample_rate = runtime->rate;
cfg.num_channels = runtime->channels;
cfg.bit_width = prtd->bits_per_sample;
prtd->pcm_count = snd_pcm_lib_period_bytes(substream);
prtd->pos = 0;
/* rate and channels are sent to audio driver */
ret = q6apm_graph_media_format_shmem(prtd->graph, &cfg);
if (ret < 0) {
dev_err(dev, "%s: q6apm_open_write failed\n", __func__);
return ret;
}
ret = q6apm_graph_media_format_pcm(prtd->graph, &cfg);
if (ret < 0)
dev_err(dev, "%s: CMD Format block failed\n", __func__);
ret = q6apm_map_memory_regions(prtd->graph, substream->stream, prtd->phys,
(prtd->pcm_size / prtd->periods), prtd->periods);
if (ret < 0) {
dev_err(dev, "Audio Start: Buffer Allocation failed rc = %d\n", ret);
return -ENOMEM;
}
ret = q6apm_graph_prepare(prtd->graph);
if (ret) {
dev_err(dev, "Failed to prepare Graph %d\n", ret);
return ret;
}
ret = q6apm_graph_start(prtd->graph);
if (ret) {
dev_err(dev, "Failed to Start Graph %d\n", ret);
return ret;
}
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
int i;
/* Queue the buffers for Capture ONLY after graph is started */
for (i = 0; i < runtime->periods; i++)
q6apm_read(prtd->graph);
}
/* Now that graph as been prepared and started update the internal state accordingly */
prtd->state = Q6APM_STREAM_RUNNING;
return 0;
}
static int q6apm_dai_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
/* start writing buffers for playback only as we already queued capture buffers */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = q6apm_write_async(prtd->graph, prtd->pcm_count, 0, 0, 0);
break;
case SNDRV_PCM_TRIGGER_STOP:
/* TODO support be handled via SoftPause Module */
prtd->state = Q6APM_STREAM_STOPPED;
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int q6apm_dai_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *soc_prtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_prtd, 0);
struct device *dev = component->dev;
struct q6apm_dai_data *pdata;
struct q6apm_dai_rtd *prtd;
int graph_id, ret;
graph_id = cpu_dai->driver->id;
pdata = snd_soc_component_get_drvdata(component);
if (!pdata) {
dev_err(dev, "Drv data not found ..\n");
return -EINVAL;
}
prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
if (prtd == NULL)
return -ENOMEM;
prtd->substream = substream;
prtd->graph = q6apm_graph_open(dev, (q6apm_cb)event_handler, prtd, graph_id);
if (IS_ERR(prtd->graph)) {
dev_err(dev, "%s: Could not allocate memory\n", __func__);
ret = PTR_ERR(prtd->graph);
goto err;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
runtime->hw = q6apm_dai_hardware_playback;
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
runtime->hw = q6apm_dai_hardware_capture;
/* Ensure that buffer size is a multiple of period size */
ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(dev, "snd_pcm_hw_constraint_integer failed\n");
goto err;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
BUFFER_BYTES_MIN, BUFFER_BYTES_MAX);
if (ret < 0) {
dev_err(dev, "constraint for buffer bytes min max ret = %d\n", ret);
goto err;
}
}
ret = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
if (ret < 0) {
dev_err(dev, "constraint for period bytes step ret = %d\n", ret);
goto err;
}
ret = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
if (ret < 0) {
dev_err(dev, "constraint for buffer bytes step ret = %d\n", ret);
goto err;
}
runtime->private_data = prtd;
runtime->dma_bytes = BUFFER_BYTES_MAX;
if (pdata->sid < 0)
prtd->phys = substream->dma_buffer.addr;
else
prtd->phys = substream->dma_buffer.addr | (pdata->sid << 32);
return 0;
err:
kfree(prtd);
return ret;
}
static int q6apm_dai_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
q6apm_graph_stop(prtd->graph);
q6apm_unmap_memory_regions(prtd->graph, substream->stream);
q6apm_graph_close(prtd->graph);
prtd->graph = NULL;
kfree(prtd);
runtime->private_data = NULL;
return 0;
}
static snd_pcm_uframes_t q6apm_dai_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
if (prtd->pos == prtd->pcm_size)
prtd->pos = 0;
return bytes_to_frames(runtime, prtd->pos);
}
static int q6apm_dai_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
prtd->pcm_size = params_buffer_bytes(params);
prtd->periods = params_periods(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
prtd->bits_per_sample = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
prtd->bits_per_sample = 24;
break;
default:
return -EINVAL;
}
return 0;
}
static int q6apm_dai_pcm_new(struct snd_soc_component *component, struct snd_soc_pcm_runtime *rtd)
{
int size = BUFFER_BYTES_MAX;
return snd_pcm_set_fixed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, component->dev, size);
}
static const struct snd_soc_component_driver q6apm_fe_dai_component = {
.name = DRV_NAME,
.open = q6apm_dai_open,
.close = q6apm_dai_close,
.prepare = q6apm_dai_prepare,
.pcm_construct = q6apm_dai_pcm_new,
.hw_params = q6apm_dai_hw_params,
.pointer = q6apm_dai_pointer,
.trigger = q6apm_dai_trigger,
};
static int q6apm_dai_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct q6apm_dai_data *pdata;
struct of_phandle_args args;
int rc;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
rc = of_parse_phandle_with_fixed_args(node, "iommus", 1, 0, &args);
if (rc < 0)
pdata->sid = -1;
else
pdata->sid = args.args[0] & SID_MASK_DEFAULT;
dev_set_drvdata(dev, pdata);
return devm_snd_soc_register_component(dev, &q6apm_fe_dai_component, NULL, 0);
}
#ifdef CONFIG_OF
static const struct of_device_id q6apm_dai_device_id[] = {
{ .compatible = "qcom,q6apm-dais" },
{},
};
MODULE_DEVICE_TABLE(of, q6apm_dai_device_id);
#endif
static struct platform_driver q6apm_dai_platform_driver = {
.driver = {
.name = "q6apm-dai",
.of_match_table = of_match_ptr(q6apm_dai_device_id),
},
.probe = q6apm_dai_probe,
};
module_platform_driver(q6apm_dai_platform_driver);
MODULE_DESCRIPTION("Q6APM dai driver");
MODULE_LICENSE("GPL");

260
sound/soc/qcom/qdsp6/q6apm-lpass-dais.c Normal file
View File

@ -0,0 +1,260 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include "q6dsp-lpass-ports.h"
#include "audioreach.h"
#include "q6apm.h"
#define AUDIOREACH_BE_PCM_BASE 16
struct q6apm_lpass_dai_data {
struct q6apm_graph *graph[APM_PORT_MAX];
bool is_port_started[APM_PORT_MAX];
struct audioreach_module_config module_config[APM_PORT_MAX];
};
static int q6dma_set_channel_map(struct snd_soc_dai *dai,
unsigned int tx_num, unsigned int *tx_ch_mask,
unsigned int rx_num, unsigned int *rx_ch_mask)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
int ch_mask;
switch (dai->id) {
case WSA_CODEC_DMA_TX_0:
case WSA_CODEC_DMA_TX_1:
case WSA_CODEC_DMA_TX_2:
case VA_CODEC_DMA_TX_0:
case VA_CODEC_DMA_TX_1:
case VA_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
case TX_CODEC_DMA_TX_4:
case TX_CODEC_DMA_TX_5:
if (!tx_ch_mask) {
dev_err(dai->dev, "tx slot not found\n");
return -EINVAL;
}
if (tx_num > AR_PCM_MAX_NUM_CHANNEL) {
dev_err(dai->dev, "invalid tx num %d\n",
tx_num);
return -EINVAL;
}
ch_mask = *tx_ch_mask;
break;
case WSA_CODEC_DMA_RX_0:
case WSA_CODEC_DMA_RX_1:
case RX_CODEC_DMA_RX_0:
case RX_CODEC_DMA_RX_1:
case RX_CODEC_DMA_RX_2:
case RX_CODEC_DMA_RX_3:
case RX_CODEC_DMA_RX_4:
case RX_CODEC_DMA_RX_5:
case RX_CODEC_DMA_RX_6:
case RX_CODEC_DMA_RX_7:
/* rx */
if (!rx_ch_mask) {
dev_err(dai->dev, "rx slot not found\n");
return -EINVAL;
}
if (rx_num > APM_PORT_MAX_AUDIO_CHAN_CNT) {
dev_err(dai->dev, "invalid rx num %d\n",
rx_num);
return -EINVAL;
}
ch_mask = *rx_ch_mask;
break;
default:
dev_err(dai->dev, "%s: invalid dai id 0x%x\n",
__func__, dai->id);
return -EINVAL;
}
cfg->active_channels_mask = ch_mask;
return 0;
}
static int q6dma_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
cfg->bit_width = params_width(params);
cfg->sample_rate = params_rate(params);
cfg->num_channels = params_channels(params);
return 0;
}
static void q6apm_lpass_dai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
int rc;
if (!dai_data->is_port_started[dai->id])
return;
rc = q6apm_graph_stop(dai_data->graph[dai->id]);
if (rc < 0)
dev_err(dai->dev, "fail to close APM port (%d)\n", rc);
q6apm_graph_close(dai_data->graph[dai->id]);
dai_data->is_port_started[dai->id] = false;
}
static int q6apm_lpass_dai_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
struct q6apm_graph *graph;
int graph_id = dai->id;
int rc;
/**
* It is recommend to load DSP with source graph first and then sink
* graph, so sequence for playback and capture will be different
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
graph = q6apm_graph_open(dai->dev, NULL, dai->dev, graph_id);
if (IS_ERR(graph)) {
dev_err(dai->dev, "Failed to open graph (%d)\n", graph_id);
rc = PTR_ERR(graph);
return rc;
}
dai_data->graph[graph_id] = graph;
}
cfg->direction = substream->stream;
rc = q6apm_graph_media_format_pcm(dai_data->graph[dai->id], cfg);
if (rc) {
dev_err(dai->dev, "Failed to set media format %d\n", rc);
return rc;
}
rc = q6apm_graph_prepare(dai_data->graph[dai->id]);
if (rc) {
dev_err(dai->dev, "Failed to prepare Graph %d\n", rc);
return rc;
}
rc = q6apm_graph_start(dai_data->graph[dai->id]);
if (rc < 0) {
dev_err(dai->dev, "fail to start APM port %x\n", dai->id);
return rc;
}
dai_data->is_port_started[dai->id] = true;
return 0;
}
static int q6apm_lpass_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6apm_graph *graph;
int graph_id = dai->id;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
graph = q6apm_graph_open(dai->dev, NULL, dai->dev, graph_id);
if (IS_ERR(graph)) {
dev_err(dai->dev, "Failed to open graph (%d)\n", graph_id);
return PTR_ERR(graph);
}
dai_data->graph[graph_id] = graph;
}
return 0;
}
static int q6i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
cfg->fmt = fmt;
return 0;
}
static const struct snd_soc_dai_ops q6dma_ops = {
.prepare = q6apm_lpass_dai_prepare,
.startup = q6apm_lpass_dai_startup,
.shutdown = q6apm_lpass_dai_shutdown,
.set_channel_map = q6dma_set_channel_map,
.hw_params = q6dma_hw_params,
};
static const struct snd_soc_dai_ops q6i2s_ops = {
.prepare = q6apm_lpass_dai_prepare,
.startup = q6apm_lpass_dai_startup,
.shutdown = q6apm_lpass_dai_shutdown,
.set_channel_map = q6dma_set_channel_map,
.hw_params = q6dma_hw_params,
.set_fmt = q6i2s_set_fmt,
};
static const struct snd_soc_component_driver q6apm_lpass_dai_component = {
.name = "q6apm-be-dai-component",
.of_xlate_dai_name = q6dsp_audio_ports_of_xlate_dai_name,
.be_pcm_base = AUDIOREACH_BE_PCM_BASE,
.use_dai_pcm_id = true,
};
static int q6apm_lpass_dai_dev_probe(struct platform_device *pdev)
{
struct q6dsp_audio_port_dai_driver_config cfg;
struct q6apm_lpass_dai_data *dai_data;
struct snd_soc_dai_driver *dais;
struct device *dev = &pdev->dev;
int num_dais;
dai_data = devm_kzalloc(dev, sizeof(*dai_data), GFP_KERNEL);
if (!dai_data)
return -ENOMEM;
dev_set_drvdata(dev, dai_data);
memset(&cfg, 0, sizeof(cfg));
cfg.q6i2s_ops = &q6i2s_ops;
cfg.q6dma_ops = &q6dma_ops;
dais = q6dsp_audio_ports_set_config(dev, &cfg, &num_dais);
return devm_snd_soc_register_component(dev, &q6apm_lpass_dai_component, dais, num_dais);
}
#ifdef CONFIG_OF
static const struct of_device_id q6apm_lpass_dai_device_id[] = {
{ .compatible = "qcom,q6apm-lpass-dais" },
{},
};
MODULE_DEVICE_TABLE(of, q6apm_lpass_dai_device_id);
#endif
static struct platform_driver q6apm_lpass_dai_platform_driver = {
.driver = {
.name = "q6apm-lpass-dais",
.of_match_table = of_match_ptr(q6apm_lpass_dai_device_id),
},
.probe = q6apm_lpass_dai_dev_probe,
};
module_platform_driver(q6apm_lpass_dai_platform_driver);
MODULE_DESCRIPTION("AUDIOREACH APM LPASS dai driver");
MODULE_LICENSE("GPL");

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sound/soc/qcom/qdsp6/q6apm.c Normal file
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// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <dt-bindings/soc/qcom,gpr.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/soc/qcom/apr.h>
#include <linux/wait.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include "audioreach.h"
#include "q6apm.h"
/* Graph Management */
struct apm_graph_mgmt_cmd {
struct apm_module_param_data param_data;
uint32_t num_sub_graphs;
uint32_t sub_graph_id_list[];
} __packed;
#define APM_GRAPH_MGMT_PSIZE(p, n) ALIGN(struct_size(p, sub_graph_id_list, n), 8)
int q6apm_send_cmd_sync(struct q6apm *apm, struct gpr_pkt *pkt, uint32_t rsp_opcode)
{
gpr_device_t *gdev = apm->gdev;
return audioreach_send_cmd_sync(&gdev->dev, gdev, &apm->result, &apm->lock,
NULL, &apm->wait, pkt, rsp_opcode);
}
static struct audioreach_graph *q6apm_get_audioreach_graph(struct q6apm *apm, uint32_t graph_id)
{
struct audioreach_graph_info *info;
struct audioreach_graph *graph;
int id;
mutex_lock(&apm->lock);
graph = idr_find(&apm->graph_idr, graph_id);
mutex_unlock(&apm->lock);
if (graph) {
kref_get(&graph->refcount);
return graph;
}
info = idr_find(&apm->graph_info_idr, graph_id);
if (!info)
return ERR_PTR(-ENODEV);
graph = kzalloc(sizeof(*graph), GFP_KERNEL);
if (!graph)
return ERR_PTR(-ENOMEM);
graph->apm = apm;
graph->info = info;
graph->id = graph_id;
graph->graph = audioreach_alloc_graph_pkt(apm, &info->sg_list, graph_id);
if (IS_ERR(graph->graph)) {
void *err = graph->graph;
kfree(graph);
return ERR_CAST(err);
}
mutex_lock(&apm->lock);
id = idr_alloc(&apm->graph_idr, graph, graph_id, graph_id + 1, GFP_KERNEL);
if (id < 0) {
dev_err(apm->dev, "Unable to allocate graph id (%d)\n", graph_id);
kfree(graph);
mutex_unlock(&apm->lock);
return ERR_PTR(id);
}
mutex_unlock(&apm->lock);
kref_init(&graph->refcount);
q6apm_send_cmd_sync(apm, graph->graph, 0);
return graph;
}
static int audioreach_graph_mgmt_cmd(struct audioreach_graph *graph, uint32_t opcode)
{
struct audioreach_graph_info *info = graph->info;
int num_sub_graphs = info->num_sub_graphs;
struct apm_module_param_data *param_data;
struct apm_graph_mgmt_cmd *mgmt_cmd;
struct audioreach_sub_graph *sg;
struct q6apm *apm = graph->apm;
int i = 0, rc, payload_size;
struct gpr_pkt *pkt;
payload_size = APM_GRAPH_MGMT_PSIZE(mgmt_cmd, num_sub_graphs);
pkt = audioreach_alloc_apm_cmd_pkt(payload_size, opcode, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
mgmt_cmd = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
mgmt_cmd->num_sub_graphs = num_sub_graphs;
param_data = &mgmt_cmd->param_data;
param_data->module_instance_id = APM_MODULE_INSTANCE_ID;
param_data->param_id = APM_PARAM_ID_SUB_GRAPH_LIST;
param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE;
list_for_each_entry(sg, &info->sg_list, node)
mgmt_cmd->sub_graph_id_list[i++] = sg->sub_graph_id;
rc = q6apm_send_cmd_sync(apm, pkt, 0);
kfree(pkt);
return rc;
}
static void q6apm_put_audioreach_graph(struct kref *ref)
{
struct audioreach_graph *graph;
struct q6apm *apm;
graph = container_of(ref, struct audioreach_graph, refcount);
apm = graph->apm;
audioreach_graph_mgmt_cmd(graph, APM_CMD_GRAPH_CLOSE);
mutex_lock(&apm->lock);
graph = idr_remove(&apm->graph_idr, graph->id);
mutex_unlock(&apm->lock);
kfree(graph->graph);
kfree(graph);
}
static int q6apm_get_apm_state(struct q6apm *apm)
{
struct gpr_pkt *pkt;
pkt = audioreach_alloc_apm_cmd_pkt(0, APM_CMD_GET_SPF_STATE, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
q6apm_send_cmd_sync(apm, pkt, APM_CMD_RSP_GET_SPF_STATE);
kfree(pkt);
return apm->state;
}
static struct audioreach_module *__q6apm_find_module_by_mid(struct q6apm *apm,
struct audioreach_graph_info *info,
uint32_t mid)
{
struct audioreach_container *container;
struct audioreach_sub_graph *sgs;
struct audioreach_module *module;
list_for_each_entry(sgs, &info->sg_list, node) {
list_for_each_entry(container, &sgs->container_list, node) {
list_for_each_entry(module, &container->modules_list, node) {
if (mid == module->module_id)
return module;
}
}
}
return NULL;
}
static struct audioreach_module *q6apm_graph_get_last_module(struct q6apm *apm, u32 sgid)
{
struct audioreach_container *container;
struct audioreach_module *module;
struct audioreach_sub_graph *sg;
mutex_lock(&apm->lock);
sg = idr_find(&apm->sub_graphs_idr, sgid);
mutex_unlock(&apm->lock);
if (!sg)
return NULL;
container = list_last_entry(&sg->container_list, struct audioreach_container, node);
module = audioreach_get_container_last_module(container);
return module;
}
static struct audioreach_module *q6apm_graph_get_first_module(struct q6apm *apm, u32 sgid)
{
struct audioreach_container *container;
struct audioreach_module *module;
struct audioreach_sub_graph *sg;
mutex_lock(&apm->lock);
sg = idr_find(&apm->sub_graphs_idr, sgid);
mutex_unlock(&apm->lock);
if (!sg)
return NULL;
container = list_first_entry(&sg->container_list, struct audioreach_container, node);
module = audioreach_get_container_first_module(container);
return module;
}
bool q6apm_is_sub_graphs_connected(struct q6apm *apm, u32 src_sgid, u32 dst_sgid)
{
struct audioreach_module *module;
u32 iid;
module = q6apm_graph_get_last_module(apm, src_sgid);
if (!module)
return false;
iid = module->instance_id;
module = q6apm_graph_get_first_module(apm, dst_sgid);
if (!module)
return false;
if (module->src_mod_inst_id == iid)
return true;
return false;
}
int q6apm_connect_sub_graphs(struct q6apm *apm, u32 src_sgid, u32 dst_sgid, bool connect)
{
struct audioreach_module *module;
u32 iid;
if (connect) {
module = q6apm_graph_get_last_module(apm, src_sgid);
if (!module)
return -ENODEV;
iid = module->instance_id;
} else {
iid = 0;
}
module = q6apm_graph_get_first_module(apm, dst_sgid);
if (!module)
return -ENODEV;
/* set src module in dst subgraph first module */
module->src_mod_inst_id = iid;
return 0;
}
int q6apm_graph_media_format_shmem(struct q6apm_graph *graph,
struct audioreach_module_config *cfg)
{
struct audioreach_module *module;
if (cfg->direction == SNDRV_PCM_STREAM_CAPTURE)
module = q6apm_find_module_by_mid(graph, MODULE_ID_RD_SHARED_MEM_EP);
else
module = q6apm_find_module_by_mid(graph, MODULE_ID_WR_SHARED_MEM_EP);
if (!module)
return -ENODEV;
audioreach_set_media_format(graph, module, cfg);
return 0;
}
EXPORT_SYMBOL_GPL(q6apm_graph_media_format_shmem);
int q6apm_map_memory_regions(struct q6apm_graph *graph, unsigned int dir, phys_addr_t phys,
size_t period_sz, unsigned int periods)
{
struct audioreach_graph_data *data;
struct audio_buffer *buf;
int cnt;
int rc;
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
data = &graph->rx_data;
else
data = &graph->tx_data;
mutex_lock(&graph->lock);
if (data->buf) {
mutex_unlock(&graph->lock);
return 0;
}
buf = kzalloc(((sizeof(struct audio_buffer)) * periods), GFP_KERNEL);
if (!buf) {
mutex_unlock(&graph->lock);
return -ENOMEM;
}
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
data = &graph->rx_data;
else
data = &graph->tx_data;
data->buf = buf;
buf[0].phys = phys;
buf[0].size = period_sz;
for (cnt = 1; cnt < periods; cnt++) {
if (period_sz > 0) {
buf[cnt].phys = buf[0].phys + (cnt * period_sz);
buf[cnt].size = period_sz;
}
}
data->num_periods = periods;
mutex_unlock(&graph->lock);
rc = audioreach_map_memory_regions(graph, dir, period_sz, periods, 1);
if (rc < 0) {
dev_err(graph->dev, "Memory_map_regions failed\n");
audioreach_graph_free_buf(graph);
}
return rc;
}
EXPORT_SYMBOL_GPL(q6apm_map_memory_regions);
int q6apm_unmap_memory_regions(struct q6apm_graph *graph, unsigned int dir)
{
struct apm_cmd_shared_mem_unmap_regions *cmd;
struct audioreach_graph_data *data;
struct gpr_pkt *pkt;
int rc;
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
data = &graph->rx_data;
else
data = &graph->tx_data;
if (!data->mem_map_handle)
return 0;
pkt = audioreach_alloc_apm_pkt(sizeof(*cmd), APM_CMD_SHARED_MEM_UNMAP_REGIONS, dir,
graph->port->id);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
cmd = (void *)pkt + GPR_HDR_SIZE;
cmd->mem_map_handle = data->mem_map_handle;
rc = audioreach_graph_send_cmd_sync(graph, pkt, APM_CMD_SHARED_MEM_UNMAP_REGIONS);
kfree(pkt);
audioreach_graph_free_buf(graph);
return rc;
}
EXPORT_SYMBOL_GPL(q6apm_unmap_memory_regions);
int q6apm_graph_media_format_pcm(struct q6apm_graph *graph, struct audioreach_module_config *cfg)
{
struct audioreach_graph_info *info = graph->info;
struct audioreach_sub_graph *sgs;
struct audioreach_container *container;
struct audioreach_module *module;
list_for_each_entry(sgs, &info->sg_list, node) {
list_for_each_entry(container, &sgs->container_list, node) {
list_for_each_entry(module, &container->modules_list, node) {
if ((module->module_id == MODULE_ID_WR_SHARED_MEM_EP) ||
(module->module_id == MODULE_ID_RD_SHARED_MEM_EP))
continue;
audioreach_set_media_format(graph, module, cfg);
}
}
}
return 0;
}
EXPORT_SYMBOL_GPL(q6apm_graph_media_format_pcm);
static int q6apm_graph_get_tx_shmem_module_iid(struct q6apm_graph *graph)
{
struct audioreach_module *module;
module = q6apm_find_module_by_mid(graph, MODULE_ID_RD_SHARED_MEM_EP);
if (!module)
return -ENODEV;
return module->instance_id;
}
int q6apm_graph_get_rx_shmem_module_iid(struct q6apm_graph *graph)
{
struct audioreach_module *module;
module = q6apm_find_module_by_mid(graph, MODULE_ID_WR_SHARED_MEM_EP);
if (!module)
return -ENODEV;
return module->instance_id;
}
EXPORT_SYMBOL_GPL(q6apm_graph_get_rx_shmem_module_iid);
int q6apm_write_async(struct q6apm_graph *graph, uint32_t len, uint32_t msw_ts,
uint32_t lsw_ts, uint32_t wflags)
{
struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 *write_buffer;
struct audio_buffer *ab;
struct gpr_pkt *pkt;
int rc, iid;
iid = q6apm_graph_get_rx_shmem_module_iid(graph);
pkt = audioreach_alloc_pkt(sizeof(*write_buffer), DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2,
graph->rx_data.dsp_buf | (len << APM_WRITE_TOKEN_LEN_SHIFT),
graph->port->id, iid);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
write_buffer = (void *)pkt + GPR_HDR_SIZE;
mutex_lock(&graph->lock);
ab = &graph->rx_data.buf[graph->rx_data.dsp_buf];
write_buffer->buf_addr_lsw = lower_32_bits(ab->phys);
write_buffer->buf_addr_msw = upper_32_bits(ab->phys);
write_buffer->buf_size = len;
write_buffer->timestamp_lsw = lsw_ts;
write_buffer->timestamp_msw = msw_ts;
write_buffer->mem_map_handle = graph->rx_data.mem_map_handle;
write_buffer->flags = wflags;
graph->rx_data.dsp_buf++;
if (graph->rx_data.dsp_buf >= graph->rx_data.num_periods)
graph->rx_data.dsp_buf = 0;
mutex_unlock(&graph->lock);
rc = gpr_send_port_pkt(graph->port, pkt);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6apm_write_async);
int q6apm_read(struct q6apm_graph *graph)
{
struct data_cmd_rd_sh_mem_ep_data_buffer_v2 *read_buffer;
struct audioreach_graph_data *port;
struct audio_buffer *ab;
struct gpr_pkt *pkt;
int rc, iid;
iid = q6apm_graph_get_tx_shmem_module_iid(graph);
pkt = audioreach_alloc_pkt(sizeof(*read_buffer), DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2,
graph->tx_data.dsp_buf, graph->port->id, iid);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
read_buffer = (void *)pkt + GPR_HDR_SIZE;
mutex_lock(&graph->lock);
port = &graph->tx_data;
ab = &port->buf[port->dsp_buf];
read_buffer->buf_addr_lsw = lower_32_bits(ab->phys);
read_buffer->buf_addr_msw = upper_32_bits(ab->phys);
read_buffer->mem_map_handle = port->mem_map_handle;
read_buffer->buf_size = ab->size;
port->dsp_buf++;
if (port->dsp_buf >= port->num_periods)
port->dsp_buf = 0;
mutex_unlock(&graph->lock);
rc = gpr_send_port_pkt(graph->port, pkt);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6apm_read);
static int graph_callback(struct gpr_resp_pkt *data, void *priv, int op)
{
struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 *rd_done;
struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 *done;
struct apm_cmd_rsp_shared_mem_map_regions *rsp;
struct gpr_ibasic_rsp_result_t *result;
struct q6apm_graph *graph = priv;
struct gpr_hdr *hdr = &data->hdr;
struct device *dev = graph->dev;
uint32_t client_event;
phys_addr_t phys;
int token;
result = data->payload;
switch (hdr->opcode) {
case DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2:
client_event = APM_CLIENT_EVENT_DATA_WRITE_DONE;
mutex_lock(&graph->lock);
token = hdr->token & APM_WRITE_TOKEN_MASK;
done = data->payload;
phys = graph->rx_data.buf[token].phys;
mutex_unlock(&graph->lock);
if (lower_32_bits(phys) == done->buf_addr_lsw &&
upper_32_bits(phys) == done->buf_addr_msw) {
graph->result.opcode = hdr->opcode;
graph->result.status = done->status;
if (graph->cb)
graph->cb(client_event, hdr->token, data->payload, graph->priv);
} else {
dev_err(dev, "WR BUFF Unexpected addr %08x-%08x\n", done->buf_addr_lsw,
done->buf_addr_msw);
}
break;
case APM_CMD_RSP_SHARED_MEM_MAP_REGIONS:
graph->result.opcode = hdr->opcode;
graph->result.status = 0;
rsp = data->payload;
if (hdr->token == SNDRV_PCM_STREAM_PLAYBACK)
graph->rx_data.mem_map_handle = rsp->mem_map_handle;
else
graph->tx_data.mem_map_handle = rsp->mem_map_handle;
wake_up(&graph->cmd_wait);
break;
case DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2:
client_event = APM_CLIENT_EVENT_DATA_READ_DONE;
mutex_lock(&graph->lock);
rd_done = data->payload;
phys = graph->tx_data.buf[hdr->token].phys;
mutex_unlock(&graph->lock);
if (upper_32_bits(phys) == rd_done->buf_addr_msw &&
lower_32_bits(phys) == rd_done->buf_addr_lsw) {
graph->result.opcode = hdr->opcode;
graph->result.status = rd_done->status;
if (graph->cb)
graph->cb(client_event, hdr->token, data->payload, graph->priv);
} else {
dev_err(dev, "RD BUFF Unexpected addr %08x-%08x\n", rd_done->buf_addr_lsw,
rd_done->buf_addr_msw);
}
break;
case DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED:
break;
case GPR_BASIC_RSP_RESULT:
switch (result->opcode) {
case APM_CMD_SHARED_MEM_UNMAP_REGIONS:
graph->result.opcode = result->opcode;
graph->result.status = 0;
if (hdr->token == SNDRV_PCM_STREAM_PLAYBACK)
graph->rx_data.mem_map_handle = 0;
else
graph->tx_data.mem_map_handle = 0;
wake_up(&graph->cmd_wait);
break;
case APM_CMD_SHARED_MEM_MAP_REGIONS:
case DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT:
case APM_CMD_SET_CFG:
graph->result.opcode = result->opcode;
graph->result.status = result->status;
if (result->status)
dev_err(dev, "Error (%d) Processing 0x%08x cmd\n",
result->status, result->opcode);
wake_up(&graph->cmd_wait);
break;
default:
break;
}
break;
default:
break;
}
return 0;
}
struct q6apm_graph *q6apm_graph_open(struct device *dev, q6apm_cb cb,
void *priv, int graph_id)
{
struct q6apm *apm = dev_get_drvdata(dev->parent);
struct audioreach_graph *ar_graph;
struct q6apm_graph *graph;
int ret;
ar_graph = q6apm_get_audioreach_graph(apm, graph_id);
if (IS_ERR(ar_graph)) {
dev_err(dev, "No graph found with id %d\n", graph_id);
return ERR_CAST(ar_graph);
}
graph = kzalloc(sizeof(*graph), GFP_KERNEL);
if (!graph) {
ret = -ENOMEM;
goto err;
}
graph->apm = apm;
graph->priv = priv;
graph->cb = cb;
graph->info = ar_graph->info;
graph->ar_graph = ar_graph;
graph->id = ar_graph->id;
graph->dev = dev;
mutex_init(&graph->lock);
init_waitqueue_head(&graph->cmd_wait);
graph->port = gpr_alloc_port(apm->gdev, dev, graph_callback, graph);
if (!graph->port) {
kfree(graph);
ret = -ENOMEM;
goto err;
}
return graph;
err:
kref_put(&ar_graph->refcount, q6apm_put_audioreach_graph);
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(q6apm_graph_open);
int q6apm_graph_close(struct q6apm_graph *graph)
{
struct audioreach_graph *ar_graph = graph->ar_graph;
gpr_free_port(graph->port);
kref_put(&ar_graph->refcount, q6apm_put_audioreach_graph);
kfree(graph);
return 0;
}
EXPORT_SYMBOL_GPL(q6apm_graph_close);
int q6apm_graph_prepare(struct q6apm_graph *graph)
{
return audioreach_graph_mgmt_cmd(graph->ar_graph, APM_CMD_GRAPH_PREPARE);
}
EXPORT_SYMBOL_GPL(q6apm_graph_prepare);
int q6apm_graph_start(struct q6apm_graph *graph)
{
struct audioreach_graph *ar_graph = graph->ar_graph;
int ret = 0;
if (ar_graph->start_count == 0)
ret = audioreach_graph_mgmt_cmd(ar_graph, APM_CMD_GRAPH_START);
ar_graph->start_count++;
return ret;
}
EXPORT_SYMBOL_GPL(q6apm_graph_start);
int q6apm_graph_stop(struct q6apm_graph *graph)
{
struct audioreach_graph *ar_graph = graph->ar_graph;
if (--ar_graph->start_count > 0)
return 0;
return audioreach_graph_mgmt_cmd(ar_graph, APM_CMD_GRAPH_STOP);
}
EXPORT_SYMBOL_GPL(q6apm_graph_stop);
int q6apm_graph_flush(struct q6apm_graph *graph)
{
return audioreach_graph_mgmt_cmd(graph->ar_graph, APM_CMD_GRAPH_FLUSH);
}
EXPORT_SYMBOL_GPL(q6apm_graph_flush);
static int q6apm_audio_probe(struct snd_soc_component *component)
{
return audioreach_tplg_init(component);
}
static void q6apm_audio_remove(struct snd_soc_component *component)
{
/* remove topology */
snd_soc_tplg_component_remove(component);
}
#define APM_AUDIO_DRV_NAME "q6apm-audio"
static const struct snd_soc_component_driver q6apm_audio_component = {
.name = APM_AUDIO_DRV_NAME,
.probe = q6apm_audio_probe,
.remove = q6apm_audio_remove,
};
static int apm_probe(gpr_device_t *gdev)
{
struct device *dev = &gdev->dev;
struct q6apm *apm;
int ret;
apm = devm_kzalloc(dev, sizeof(*apm), GFP_KERNEL);
if (!apm)
return -ENOMEM;
dev_set_drvdata(dev, apm);
mutex_init(&apm->lock);
apm->dev = dev;
apm->gdev = gdev;
init_waitqueue_head(&apm->wait);
idr_init(&apm->graph_idr);
idr_init(&apm->graph_info_idr);
idr_init(&apm->sub_graphs_idr);
idr_init(&apm->containers_idr);
idr_init(&apm->modules_idr);
q6apm_get_apm_state(apm);
ret = devm_snd_soc_register_component(dev, &q6apm_audio_component, NULL, 0);
if (ret < 0) {
dev_err(dev, "failed to get register q6apm: %d\n", ret);
return ret;
}
return of_platform_populate(dev->of_node, NULL, NULL, dev);
}
struct audioreach_module *q6apm_find_module_by_mid(struct q6apm_graph *graph, uint32_t mid)
{
struct audioreach_graph_info *info = graph->info;
struct q6apm *apm = graph->apm;
return __q6apm_find_module_by_mid(apm, info, mid);
}
static int apm_callback(struct gpr_resp_pkt *data, void *priv, int op)
{
gpr_device_t *gdev = priv;
struct q6apm *apm = dev_get_drvdata(&gdev->dev);
struct device *dev = &gdev->dev;
struct gpr_ibasic_rsp_result_t *result;
struct gpr_hdr *hdr = &data->hdr;
result = data->payload;
switch (hdr->opcode) {
case APM_CMD_RSP_GET_SPF_STATE:
apm->result.opcode = hdr->opcode;
apm->result.status = 0;
/* First word of result it state */
apm->state = result->opcode;
wake_up(&apm->wait);
break;
case GPR_BASIC_RSP_RESULT:
switch (result->opcode) {
case APM_CMD_GRAPH_START:
case APM_CMD_GRAPH_OPEN:
case APM_CMD_GRAPH_PREPARE:
case APM_CMD_GRAPH_CLOSE:
case APM_CMD_GRAPH_FLUSH:
case APM_CMD_GRAPH_STOP:
case APM_CMD_SET_CFG:
apm->result.opcode = result->opcode;
apm->result.status = result->status;
if (result->status)
dev_err(dev, "Error (%d) Processing 0x%08x cmd\n", result->status,
result->opcode);
wake_up(&apm->wait);
break;
default:
break;
}
break;
default:
break;
}
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id apm_device_id[] = {
{ .compatible = "qcom,q6apm" },
{},
};
MODULE_DEVICE_TABLE(of, apm_device_id);
#endif
static gpr_driver_t apm_driver = {
.probe = apm_probe,
.gpr_callback = apm_callback,
.driver = {
.name = "qcom-apm",
.of_match_table = of_match_ptr(apm_device_id),
},
};
module_gpr_driver(apm_driver);
MODULE_DESCRIPTION("Audio Process Manager");
MODULE_LICENSE("GPL");

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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6APM_H__
#define __Q6APM_H__
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <sound/soc.h>
#include <linux/of_platform.h>
#include <linux/jiffies.h>
#include <linux/soc/qcom/apr.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "audioreach.h"
#define APM_PORT_MAX 127
#define APM_PORT_MAX_AUDIO_CHAN_CNT 8
#define PCM_CHANNEL_NULL 0
#define PCM_CHANNEL_FL 1 /* Front left channel. */
#define PCM_CHANNEL_FR 2 /* Front right channel. */
#define PCM_CHANNEL_FC 3 /* Front center channel. */
#define PCM_CHANNEL_LS 4 /* Left surround channel. */
#define PCM_CHANNEL_RS 5 /* Right surround channel. */
#define PCM_CHANNEL_LFE 6 /* Low frequency effect channel. */
#define PCM_CHANNEL_CS 7 /* Center surround channel; Rear center ch */
#define PCM_CHANNEL_LB 8 /* Left back channel; Rear left channel. */
#define PCM_CHANNEL_RB 9 /* Right back channel; Rear right channel. */
#define PCM_CHANNELS 10 /* Top surround channel. */
#define APM_TIMESTAMP_FLAG 0x80000000
#define FORMAT_LINEAR_PCM 0x0000
/* APM client callback events */
#define APM_CMD_EOS 0x0003
#define APM_CLIENT_EVENT_CMD_EOS_DONE 0x1003
#define APM_CMD_CLOSE 0x0004
#define APM_CLIENT_EVENT_CMD_CLOSE_DONE 0x1004
#define APM_CLIENT_EVENT_CMD_RUN_DONE 0x1008
#define APM_CLIENT_EVENT_DATA_WRITE_DONE 0x1009
#define APM_CLIENT_EVENT_DATA_READ_DONE 0x100a
#define APM_WRITE_TOKEN_MASK GENMASK(15, 0)
#define APM_WRITE_TOKEN_LEN_MASK GENMASK(31, 16)
#define APM_WRITE_TOKEN_LEN_SHIFT 16
#define APM_MAX_SESSIONS 8
struct q6apm {
struct device *dev;
gpr_port_t *port;
gpr_device_t *gdev;
/* For Graph OPEN/START/STOP/CLOSE operations */
wait_queue_head_t wait;
struct gpr_ibasic_rsp_result_t result;
struct mutex cmd_lock;
struct mutex lock;
uint32_t state;
struct idr graph_idr;
struct idr graph_info_idr;
struct idr sub_graphs_idr;
struct idr containers_idr;
struct idr modules_idr;
};
struct audio_buffer {
phys_addr_t phys;
uint32_t size; /* size of buffer */
};
struct audioreach_graph_data {
struct audio_buffer *buf;
uint32_t num_periods;
uint32_t dsp_buf;
uint32_t mem_map_handle;
};
struct audioreach_graph {
struct audioreach_graph_info *info;
uint32_t id;
int state;
int start_count;
/* Cached Graph data */
void *graph;
struct kref refcount;
struct q6apm *apm;
};
typedef void (*q6apm_cb) (uint32_t opcode, uint32_t token,
void *payload, void *priv);
struct q6apm_graph {
void *priv;
q6apm_cb cb;
uint32_t id;
struct device *dev;
struct q6apm *apm;
gpr_port_t *port;
struct audioreach_graph_data rx_data;
struct audioreach_graph_data tx_data;
struct gpr_ibasic_rsp_result_t result;
wait_queue_head_t cmd_wait;
struct mutex lock;
struct audioreach_graph *ar_graph;
struct audioreach_graph_info *info;
};
/* Graph Operations */
struct q6apm_graph *q6apm_graph_open(struct device *dev, q6apm_cb cb,
void *priv, int graph_id);
int q6apm_graph_close(struct q6apm_graph *graph);
int q6apm_graph_prepare(struct q6apm_graph *graph);
int q6apm_graph_start(struct q6apm_graph *graph);
int q6apm_graph_stop(struct q6apm_graph *graph);
int q6apm_graph_flush(struct q6apm_graph *graph);
/* Media Format */
int q6apm_graph_media_format_pcm(struct q6apm_graph *graph,
struct audioreach_module_config *cfg);
int q6apm_graph_media_format_shmem(struct q6apm_graph *graph,
struct audioreach_module_config *cfg);
/* read/write related */
int q6apm_send_eos_nowait(struct q6apm_graph *graph);
int q6apm_read(struct q6apm_graph *graph);
int q6apm_write_async(struct q6apm_graph *graph, uint32_t len, uint32_t msw_ts,
uint32_t lsw_ts, uint32_t wflags);
/* Memory Map related */
int q6apm_map_memory_regions(struct q6apm_graph *graph,
unsigned int dir, phys_addr_t phys,
size_t period_sz, unsigned int periods);
int q6apm_unmap_memory_regions(struct q6apm_graph *graph,
unsigned int dir);
/* Helpers */
int q6apm_send_cmd_sync(struct q6apm *apm, struct gpr_pkt *pkt,
uint32_t rsp_opcode);
/* Callback for graph specific */
struct audioreach_module *q6apm_find_module_by_mid(struct q6apm_graph *graph,
uint32_t mid);
void q6apm_set_fe_dai_ops(struct snd_soc_dai_driver *dai_drv);
int q6apm_connect_sub_graphs(struct q6apm *apm, u32 src_sgid, u32 dst_sgid,
bool connect);
bool q6apm_is_sub_graphs_connected(struct q6apm *apm, u32 src_sgid,
u32 dst_sgid);
int q6apm_graph_get_rx_shmem_module_iid(struct q6apm_graph *graph);
#endif /* __APM_GRAPH_ */

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// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <linux/err.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "q6dsp-lpass-clocks.h"
#define Q6DSP_MAX_CLK_ID 104
#define Q6DSP_LPASS_CLK_ROOT_DEFAULT 0
struct q6dsp_clk {
struct device *dev;
int q6dsp_clk_id;
int attributes;
int rate;
uint32_t handle;
struct clk_hw hw;
};
#define to_q6dsp_clk(_hw) container_of(_hw, struct q6dsp_clk, hw)
struct q6dsp_cc {
struct device *dev;
struct q6dsp_clk *clks[Q6DSP_MAX_CLK_ID];
const struct q6dsp_clk_desc *desc;
};
static int clk_q6dsp_prepare(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
return cc->desc->lpass_set_clk(clk->dev, clk->q6dsp_clk_id, clk->attributes,
Q6DSP_LPASS_CLK_ROOT_DEFAULT, clk->rate);
}
static void clk_q6dsp_unprepare(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
cc->desc->lpass_set_clk(clk->dev, clk->q6dsp_clk_id, clk->attributes,
Q6DSP_LPASS_CLK_ROOT_DEFAULT, 0);
}
static int clk_q6dsp_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
clk->rate = rate;
return 0;
}
static unsigned long clk_q6dsp_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
return clk->rate;
}
static long clk_q6dsp_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
return rate;
}
static const struct clk_ops clk_q6dsp_ops = {
.prepare = clk_q6dsp_prepare,
.unprepare = clk_q6dsp_unprepare,
.set_rate = clk_q6dsp_set_rate,
.round_rate = clk_q6dsp_round_rate,
.recalc_rate = clk_q6dsp_recalc_rate,
};
static int clk_vote_q6dsp_block(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
return cc->desc->lpass_vote_clk(clk->dev, clk->q6dsp_clk_id,
clk_hw_get_name(&clk->hw), &clk->handle);
}
static void clk_unvote_q6dsp_block(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
cc->desc->lpass_unvote_clk(clk->dev, clk->q6dsp_clk_id, clk->handle);
}
static const struct clk_ops clk_vote_q6dsp_ops = {
.prepare = clk_vote_q6dsp_block,
.unprepare = clk_unvote_q6dsp_block,
};
static struct clk_hw *q6dsp_of_clk_hw_get(struct of_phandle_args *clkspec,
void *data)
{
struct q6dsp_cc *cc = data;
unsigned int idx = clkspec->args[0];
unsigned int attr = clkspec->args[1];
if (idx >= Q6DSP_MAX_CLK_ID || attr > LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR) {
dev_err(cc->dev, "Invalid clk specifier (%d, %d)\n", idx, attr);
return ERR_PTR(-EINVAL);
}
if (cc->clks[idx]) {
cc->clks[idx]->attributes = attr;
return &cc->clks[idx]->hw;
}
return ERR_PTR(-ENOENT);
}
int q6dsp_clock_dev_probe(struct platform_device *pdev)
{
struct q6dsp_cc *cc;
struct device *dev = &pdev->dev;
const struct q6dsp_clk_init *q6dsp_clks;
const struct q6dsp_clk_desc *desc;
int i, ret;
cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
if (!cc)
return -ENOMEM;
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
cc->desc = desc;
cc->dev = dev;
q6dsp_clks = desc->clks;
for (i = 0; i < desc->num_clks; i++) {
unsigned int id = q6dsp_clks[i].clk_id;
struct clk_init_data init = {
.name = q6dsp_clks[i].name,
};
struct q6dsp_clk *clk;
clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
if (!clk)
return -ENOMEM;
clk->dev = dev;
clk->q6dsp_clk_id = q6dsp_clks[i].q6dsp_clk_id;
clk->rate = q6dsp_clks[i].rate;
clk->hw.init = &init;
if (clk->rate)
init.ops = &clk_q6dsp_ops;
else
init.ops = &clk_vote_q6dsp_ops;
cc->clks[id] = clk;
ret = devm_clk_hw_register(dev, &clk->hw);
if (ret)
return ret;
}
ret = devm_of_clk_add_hw_provider(dev, q6dsp_of_clk_hw_get, cc);
if (ret)
return ret;
dev_set_drvdata(dev, cc);
return 0;
}
EXPORT_SYMBOL_GPL(q6dsp_clock_dev_probe);

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sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6DSP_AUDIO_CLOCKS_H__
#define __Q6DSP_AUDIO_CLOCKS_H__
struct q6dsp_clk_init {
int clk_id;
int q6dsp_clk_id;
char *name;
int rate;
};
#define Q6DSP_VOTE_CLK(id, blkid, n) { \
.clk_id = id, \
.q6dsp_clk_id = blkid, \
.name = n, \
}
struct q6dsp_clk_desc {
const struct q6dsp_clk_init *clks;
size_t num_clks;
int (*lpass_set_clk)(struct device *dev, int clk_id, int attr,
int root_clk, unsigned int freq);
int (*lpass_vote_clk)(struct device *dev, uint32_t hid, const char *n, uint32_t *h);
int (*lpass_unvote_clk)(struct device *dev, uint32_t hid, uint32_t h);
};
int q6dsp_clock_dev_probe(struct platform_device *pdev);
#endif /* __Q6DSP_AUDIO_CLOCKS_H__ */

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sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c Normal file
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// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include "q6dsp-lpass-ports.h"
#define Q6AFE_TDM_PB_DAI(pre, num, did) { \
.playback = { \
.stream_name = pre" TDM"#num" Playback", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_TDM_CAP_DAI(pre, num, did) { \
.capture = { \
.stream_name = pre" TDM"#num" Capture", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_CDC_DMA_RX_DAI(did) { \
.playback = { \
.stream_name = #did" Playback", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_CDC_DMA_TX_DAI(did) { \
.capture = { \
.stream_name = #did" Capture", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = {
{
.playback = {
.stream_name = "HDMI Playback",
.rates = SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 2,
.channels_max = 8,
.rate_max = 192000,
.rate_min = 48000,
},
.id = HDMI_RX,
.name = "HDMI",
}, {
.name = "SLIMBUS_0_RX",
.id = SLIMBUS_0_RX,
.playback = {
.stream_name = "Slimbus Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.name = "SLIMBUS_0_TX",
.id = SLIMBUS_0_TX,
.capture = {
.stream_name = "Slimbus Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus1 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_1_RX",
.id = SLIMBUS_1_RX,
}, {
.name = "SLIMBUS_1_TX",
.id = SLIMBUS_1_TX,
.capture = {
.stream_name = "Slimbus1 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus2 Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_2_RX",
.id = SLIMBUS_2_RX,
}, {
.name = "SLIMBUS_2_TX",
.id = SLIMBUS_2_TX,
.capture = {
.stream_name = "Slimbus2 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus3 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_3_RX",
.id = SLIMBUS_3_RX,
}, {
.name = "SLIMBUS_3_TX",
.id = SLIMBUS_3_TX,
.capture = {
.stream_name = "Slimbus3 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus4 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_4_RX",
.id = SLIMBUS_4_RX,
}, {
.name = "SLIMBUS_4_TX",
.id = SLIMBUS_4_TX,
.capture = {
.stream_name = "Slimbus4 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus5 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_5_RX",
.id = SLIMBUS_5_RX,
}, {
.name = "SLIMBUS_5_TX",
.id = SLIMBUS_5_TX,
.capture = {
.stream_name = "Slimbus5 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus6 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_6_RX",
.id = SLIMBUS_6_RX,
}, {
.name = "SLIMBUS_6_TX",
.id = SLIMBUS_6_TX,
.capture = {
.stream_name = "Slimbus6 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Primary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = PRIMARY_MI2S_RX,
.name = "PRI_MI2S_RX",
}, {
.capture = {
.stream_name = "Primary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = PRIMARY_MI2S_TX,
.name = "PRI_MI2S_TX",
}, {
.playback = {
.stream_name = "Secondary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "SEC_MI2S_RX",
.id = SECONDARY_MI2S_RX,
}, {
.capture = {
.stream_name = "Secondary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = SECONDARY_MI2S_TX,
.name = "SEC_MI2S_TX",
}, {
.playback = {
.stream_name = "Tertiary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "TERT_MI2S_RX",
.id = TERTIARY_MI2S_RX,
}, {
.capture = {
.stream_name = "Tertiary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = TERTIARY_MI2S_TX,
.name = "TERT_MI2S_TX",
}, {
.playback = {
.stream_name = "Quaternary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "QUAT_MI2S_RX",
.id = QUATERNARY_MI2S_RX,
}, {
.capture = {
.stream_name = "Quaternary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = QUATERNARY_MI2S_TX,
.name = "QUAT_MI2S_TX",
}, {
.playback = {
.stream_name = "Quinary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
.id = QUINARY_MI2S_RX,
.name = "QUIN_MI2S_RX",
}, {
.capture = {
.stream_name = "Quinary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = QUINARY_MI2S_TX,
.name = "QUIN_MI2S_TX",
},
Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Primary", 2, PRIMARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Primary", 3, PRIMARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Primary", 4, PRIMARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Primary", 5, PRIMARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Primary", 6, PRIMARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Primary", 7, PRIMARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Primary", 0, PRIMARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Primary", 1, PRIMARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Primary", 2, PRIMARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Primary", 3, PRIMARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Primary", 4, PRIMARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Primary", 5, PRIMARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Primary", 6, PRIMARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Primary", 7, PRIMARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Secondary", 0, SECONDARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Secondary", 1, SECONDARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Secondary", 2, SECONDARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Secondary", 3, SECONDARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Secondary", 4, SECONDARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Secondary", 5, SECONDARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Secondary", 6, SECONDARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Secondary", 7, SECONDARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Secondary", 0, SECONDARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Secondary", 1, SECONDARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Secondary", 2, SECONDARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Secondary", 3, SECONDARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Secondary", 4, SECONDARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Secondary", 5, SECONDARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Secondary", 6, SECONDARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Secondary", 7, SECONDARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Tertiary", 0, TERTIARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Tertiary", 1, TERTIARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Tertiary", 2, TERTIARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Tertiary", 3, TERTIARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Tertiary", 4, TERTIARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Tertiary", 5, TERTIARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Tertiary", 6, TERTIARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Tertiary", 7, TERTIARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Tertiary", 0, TERTIARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Tertiary", 1, TERTIARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Tertiary", 2, TERTIARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Tertiary", 3, TERTIARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Tertiary", 4, TERTIARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Tertiary", 5, TERTIARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Tertiary", 6, TERTIARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Tertiary", 7, TERTIARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Quaternary", 0, QUATERNARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Quaternary", 1, QUATERNARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Quaternary", 2, QUATERNARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Quaternary", 3, QUATERNARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Quaternary", 4, QUATERNARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Quaternary", 5, QUATERNARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Quaternary", 6, QUATERNARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Quaternary", 7, QUATERNARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Quaternary", 0, QUATERNARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Quaternary", 1, QUATERNARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Quaternary", 2, QUATERNARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Quaternary", 3, QUATERNARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Quaternary", 4, QUATERNARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Quaternary", 5, QUATERNARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Quaternary", 6, QUATERNARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Quaternary", 7, QUATERNARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Quinary", 0, QUINARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Quinary", 1, QUINARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Quinary", 2, QUINARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Quinary", 3, QUINARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Quinary", 4, QUINARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Quinary", 5, QUINARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Quinary", 6, QUINARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Quinary", 7, QUINARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Quinary", 0, QUINARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Quinary", 1, QUINARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Quinary", 2, QUINARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Quinary", 3, QUINARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Quinary", 4, QUINARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Quinary", 5, QUINARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Quinary", 6, QUINARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Quinary", 7, QUINARY_TDM_TX_7),
{
.playback = {
.stream_name = "Display Port Playback",
.rates = SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 2,
.channels_max = 8,
.rate_max = 192000,
.rate_min = 48000,
},
.id = DISPLAY_PORT_RX,
.name = "DISPLAY_PORT",
},
Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_0),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_1),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_0),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_1),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_2),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_3),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_3),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_4),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_4),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_5),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_5),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_6),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_7),
};
int q6dsp_audio_ports_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name)
{
int id = args->args[0];
int ret = -EINVAL;
int i;
for (i = 0; i < ARRAY_SIZE(q6dsp_audio_fe_dais); i++) {
if (q6dsp_audio_fe_dais[i].id == id) {
*dai_name = q6dsp_audio_fe_dais[i].name;
ret = 0;
break;
}
}
return ret;
}
EXPORT_SYMBOL_GPL(q6dsp_audio_ports_of_xlate_dai_name);
struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev,
struct q6dsp_audio_port_dai_driver_config *cfg,
int *num_dais)
{
int i;
for (i = 0; i < ARRAY_SIZE(q6dsp_audio_fe_dais); i++) {
q6dsp_audio_fe_dais[i].probe = cfg->probe;
q6dsp_audio_fe_dais[i].remove = cfg->remove;
switch (q6dsp_audio_fe_dais[i].id) {
case HDMI_RX:
case DISPLAY_PORT_RX:
q6dsp_audio_fe_dais[i].ops = cfg->q6hdmi_ops;
break;
case SLIMBUS_0_RX ... SLIMBUS_6_TX:
q6dsp_audio_fe_dais[i].ops = cfg->q6slim_ops;
break;
case QUINARY_MI2S_RX ... QUINARY_MI2S_TX:
case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX:
q6dsp_audio_fe_dais[i].ops = cfg->q6i2s_ops;
break;
case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7:
q6dsp_audio_fe_dais[i].ops = cfg->q6tdm_ops;
break;
case WSA_CODEC_DMA_RX_0 ... RX_CODEC_DMA_RX_7:
q6dsp_audio_fe_dais[i].ops = cfg->q6dma_ops;
break;
default:
break;
}
}
*num_dais = ARRAY_SIZE(q6dsp_audio_fe_dais);
return q6dsp_audio_fe_dais;
}
EXPORT_SYMBOL_GPL(q6dsp_audio_ports_set_config);

22
sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h Normal file
View File

@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6DSP_AUDIO_PORTS_H__
#define __Q6DSP_AUDIO_PORTS_H__
struct q6dsp_audio_port_dai_driver_config {
int (*probe)(struct snd_soc_dai *dai);
int (*remove)(struct snd_soc_dai *dai);
const struct snd_soc_dai_ops *q6hdmi_ops;
const struct snd_soc_dai_ops *q6slim_ops;
const struct snd_soc_dai_ops *q6i2s_ops;
const struct snd_soc_dai_ops *q6tdm_ops;
const struct snd_soc_dai_ops *q6dma_ops;
};
struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev,
struct q6dsp_audio_port_dai_driver_config *cfg,
int *num_dais);
int q6dsp_audio_ports_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name);
#endif /* __Q6DSP_AUDIO_PORTS_H__ */

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// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <linux/err.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "q6dsp-lpass-clocks.h"
#include "q6prm.h"
#define Q6PRM_CLK(id) { \
.clk_id = id, \
.q6dsp_clk_id = Q6PRM_##id, \
.name = #id, \
.rate = 19200000, \
}
static const struct q6dsp_clk_init q6prm_clks[] = {
Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS,
"LPASS_HW_MACRO"),
Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,
"LPASS_HW_DCODEC"),
};
static const struct q6dsp_clk_desc q6dsp_clk_q6prm __maybe_unused = {
.clks = q6prm_clks,
.num_clks = ARRAY_SIZE(q6prm_clks),
.lpass_set_clk = q6prm_set_lpass_clock,
.lpass_vote_clk = q6prm_vote_lpass_core_hw,
.lpass_unvote_clk = q6prm_unvote_lpass_core_hw,
};
#ifdef CONFIG_OF
static const struct of_device_id q6prm_clock_device_id[] = {
{ .compatible = "qcom,q6prm-lpass-clocks", .data = &q6dsp_clk_q6prm },
{},
};
MODULE_DEVICE_TABLE(of, q6prm_clock_device_id);
#endif
static struct platform_driver q6prm_clock_platform_driver = {
.driver = {
.name = "q6prm-lpass-clock",
.of_match_table = of_match_ptr(q6prm_clock_device_id),
},
.probe = q6dsp_clock_dev_probe,
};
module_platform_driver(q6prm_clock_platform_driver);
MODULE_DESCRIPTION("Q6 Proxy Resource Manager LPASS clock driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/of_platform.h>
#include <linux/jiffies.h>
#include <linux/soc/qcom/apr.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "q6prm.h"
#include "audioreach.h"
struct q6prm {
struct device *dev;
gpr_device_t *gdev;
wait_queue_head_t wait;
struct gpr_ibasic_rsp_result_t result;
struct mutex lock;
};
#define PRM_CMD_REQUEST_HW_RSC 0x0100100F
#define PRM_CMD_RSP_REQUEST_HW_RSC 0x02001002
#define PRM_CMD_RELEASE_HW_RSC 0x01001010
#define PRM_CMD_RSP_RELEASE_HW_RSC 0x02001003
#define PARAM_ID_RSC_HW_CORE 0x08001032
#define PARAM_ID_RSC_LPASS_CORE 0x0800102B
#define PARAM_ID_RSC_AUDIO_HW_CLK 0x0800102C
struct prm_cmd_request_hw_core {
struct apm_module_param_data param_data;
uint32_t hw_clk_id;
} __packed;
struct prm_cmd_request_rsc {
struct apm_module_param_data param_data;
uint32_t num_clk_id;
struct audio_hw_clk_cfg clock_id;
} __packed;
static int q6prm_send_cmd_sync(struct q6prm *prm, struct gpr_pkt *pkt, uint32_t rsp_opcode)
{
return audioreach_send_cmd_sync(prm->dev, prm->gdev, &prm->result, &prm->lock,
NULL, &prm->wait, pkt, rsp_opcode);
}
static int q6prm_set_hw_core_req(struct device *dev, uint32_t hw_block_id, bool enable)
{
struct q6prm *prm = dev_get_drvdata(dev->parent);
struct apm_module_param_data *param_data;
struct prm_cmd_request_hw_core *req;
gpr_device_t *gdev = prm->gdev;
uint32_t opcode, rsp_opcode;
struct gpr_pkt *pkt;
int rc;
if (enable) {
opcode = PRM_CMD_REQUEST_HW_RSC;
rsp_opcode = PRM_CMD_RSP_REQUEST_HW_RSC;
} else {
opcode = PRM_CMD_RELEASE_HW_RSC;
rsp_opcode = PRM_CMD_RSP_RELEASE_HW_RSC;
}
pkt = audioreach_alloc_cmd_pkt(sizeof(*req), opcode, 0, gdev->svc.id, GPR_PRM_MODULE_IID);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
req = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = &req->param_data;
param_data->module_instance_id = GPR_PRM_MODULE_IID;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_RSC_HW_CORE;
param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;
req->hw_clk_id = hw_block_id;
rc = q6prm_send_cmd_sync(prm, pkt, rsp_opcode);
kfree(pkt);
return rc;
}
int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
const char *client_name, uint32_t *client_handle)
{
return q6prm_set_hw_core_req(dev, hw_block_id, true);
}
EXPORT_SYMBOL_GPL(q6prm_vote_lpass_core_hw);
int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, uint32_t client_handle)
{
return q6prm_set_hw_core_req(dev, hw_block_id, false);
}
EXPORT_SYMBOL_GPL(q6prm_unvote_lpass_core_hw);
int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root,
unsigned int freq)
{
struct q6prm *prm = dev_get_drvdata(dev->parent);
struct apm_module_param_data *param_data;
struct prm_cmd_request_rsc *req;
gpr_device_t *gdev = prm->gdev;
struct gpr_pkt *pkt;
int rc;
pkt = audioreach_alloc_cmd_pkt(sizeof(*req), PRM_CMD_REQUEST_HW_RSC, 0, gdev->svc.id,
GPR_PRM_MODULE_IID);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
req = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = &req->param_data;
param_data->module_instance_id = GPR_PRM_MODULE_IID;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_RSC_AUDIO_HW_CLK;
param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;
req->num_clk_id = 1;
req->clock_id.clock_id = clk_id;
req->clock_id.clock_freq = freq;
req->clock_id.clock_attri = clk_attr;
req->clock_id.clock_root = clk_root;
rc = q6prm_send_cmd_sync(prm, pkt, PRM_CMD_RSP_REQUEST_HW_RSC);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6prm_set_lpass_clock);
static int prm_callback(struct gpr_resp_pkt *data, void *priv, int op)
{
gpr_device_t *gdev = priv;
struct q6prm *prm = dev_get_drvdata(&gdev->dev);
struct gpr_ibasic_rsp_result_t *result;
struct gpr_hdr *hdr = &data->hdr;
switch (hdr->opcode) {
case PRM_CMD_RSP_REQUEST_HW_RSC:
case PRM_CMD_RSP_RELEASE_HW_RSC:
result = data->payload;
prm->result.opcode = hdr->opcode;
prm->result.status = result->status;
wake_up(&prm->wait);
break;
default:
break;
}
return 0;
}
static int prm_probe(gpr_device_t *gdev)
{
struct device *dev = &gdev->dev;
struct q6prm *cc;
cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
if (!cc)
return -ENOMEM;
cc->dev = dev;
cc->gdev = gdev;
mutex_init(&cc->lock);
init_waitqueue_head(&cc->wait);
dev_set_drvdata(dev, cc);
return devm_of_platform_populate(dev);
}
#ifdef CONFIG_OF
static const struct of_device_id prm_device_id[] = {
{ .compatible = "qcom,q6prm" },
{},
};
MODULE_DEVICE_TABLE(of, prm_device_id);
#endif
static gpr_driver_t prm_driver = {
.probe = prm_probe,
.gpr_callback = prm_callback,
.driver = {
.name = "qcom-prm",
.of_match_table = of_match_ptr(prm_device_id),
},
};
module_gpr_driver(prm_driver);
MODULE_DESCRIPTION("Audio Process Manager");
MODULE_LICENSE("GPL");

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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __Q6PRM_H__
#define __Q6PRM_H__
/* Clock ID for Primary I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
/* Clock ID for Primary I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
/* Clock ID for Secondary I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
/* Clock ID for Secondary I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
/* Clock ID for Tertiary I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
/* Clock ID for Tertiary I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
/* Clock ID for Quartnery I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
/* Clock ID for Quartnery I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
/* Clock ID for Speaker I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
/* Clock ID for Speaker I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
/* Clock ID for Speaker I2S OSR */
#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
/* Clock ID for QUINARY I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
/* Clock ID for QUINARY I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
/* Clock ID for SENARY I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
/* Clock ID for SENARY I2S EBIT */
#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
/* Clock ID for INT0 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
/* Clock ID for INT1 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
/* Clock ID for INT2 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
/* Clock ID for INT3 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
/* Clock ID for INT4 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
/* Clock ID for INT5 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
/* Clock ID for INT6 I2S IBIT */
#define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
/* Clock ID for QUINARY MI2S OSR CLK */
#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
#define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305
#define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306
#define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK 0x307
#define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x308
#define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK 0x30c
#define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d
#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
#define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
#define Q6PRM_LPASS_CLK_SRC_INTERNAL 1
#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0
#define Q6PRM_HW_CORE_ID_LPASS 1
#define Q6PRM_HW_CORE_ID_DCODEC 2
int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr,
int clk_root, unsigned int freq);
int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
const char *client_name, uint32_t *client_handle);
int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
uint32_t client_handle);
#endif /* __Q6PRM_H__ */

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