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ARM: sun6i: Enable the I2C controllers
The A31 has 4 I2C controllers that are the same than the one in the other Allwinner SoCs, except for the fact that they are asserted in reset by the reset unit. Add these i2c controllers to the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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e2315012c6
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@ -359,6 +359,46 @@
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status = "disabled";
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};
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i2c0: i2c@01c2ac00 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2ac00 0x400>;
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interrupts = <0 6 4>;
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clocks = <&apb2_gates 0>;
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clock-frequency = <100000>;
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resets = <&apb2_rst 0>;
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status = "disabled";
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};
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i2c1: i2c@01c2b000 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b000 0x400>;
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interrupts = <0 7 4>;
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clocks = <&apb2_gates 1>;
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clock-frequency = <100000>;
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resets = <&apb2_rst 1>;
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status = "disabled";
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};
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i2c2: i2c@01c2b400 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b400 0x400>;
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interrupts = <0 8 4>;
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clocks = <&apb2_gates 2>;
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clock-frequency = <100000>;
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resets = <&apb2_rst 2>;
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status = "disabled";
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};
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i2c3: i2c@01c2b800 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b800 0x400>;
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interrupts = <0 9 4>;
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clocks = <&apb2_gates 3>;
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clock-frequency = <100000>;
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resets = <&apb2_rst 3>;
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status = "disabled";
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};
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spi0: spi@01c68000 {
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compatible = "allwinner,sun6i-a31-spi";
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reg = <0x01c68000 0x1000>;
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