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mmc: sh_mmcif: revision-specific Command Completion Signal handling
Some earlier MMCIF IP revisions contained Command Completion Signal support, which has been dropped again in modern versions. Sopport for this feature is added in a way to preserve the current behaviour by default, i.e. when it is not enabled in platform data. Patch is based on work by Nobuyuki HIRAI. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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@ -134,6 +134,8 @@
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INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \
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INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE)
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#define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE)
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/* CE_INT_MASK */
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#define MASK_ALL 0x00000000
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#define MASK_MCCSDE (1 << 29)
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@ -162,7 +164,7 @@
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#define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
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MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
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MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
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MASK_MCRCSTO | MASK_MWDATTO | \
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MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
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#define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \
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@ -244,6 +246,7 @@ struct sh_mmcif_host {
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int sg_blkidx;
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bool power;
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bool card_present;
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bool ccs_enable; /* Command Completion Signal support */
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struct mutex thread_lock;
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/* DMA support */
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@ -492,8 +495,10 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
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sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
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sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
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if (host->ccs_enable)
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tmp |= SCCSTO_29;
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sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
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SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
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SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
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/* byte swap on */
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sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
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}
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@ -873,6 +878,9 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
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break;
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}
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if (host->ccs_enable)
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mask |= MASK_MCCSTO;
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if (mrq->data) {
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sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
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sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
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@ -880,7 +888,10 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
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}
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opc = sh_mmcif_set_cmd(host, mrq);
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
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if (host->ccs_enable)
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
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else
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS);
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sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
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/* set arg */
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sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
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@ -1245,11 +1256,14 @@ static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
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static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
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{
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struct sh_mmcif_host *host = dev_id;
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u32 state;
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u32 state, mask;
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state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
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sh_mmcif_writel(host->addr, MMCIF_CE_INT,
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~(state & sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK)));
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mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK);
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if (host->ccs_enable)
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask));
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else
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask));
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);
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if (state & ~MASK_CLEAN)
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@ -1383,6 +1397,7 @@ static int sh_mmcif_probe(struct platform_device *pdev)
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host->mmc = mmc;
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host->addr = reg;
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host->timeout = msecs_to_jiffies(1000);
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host->ccs_enable = !pd || !pd->ccs_unsupported;
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host->pd = pdev;
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@ -36,6 +36,7 @@ struct sh_mmcif_plat_data {
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unsigned int slave_id_tx; /* embedded slave_id_[tr]x */
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unsigned int slave_id_rx;
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bool use_cd_gpio : 1;
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bool ccs_unsupported : 1;
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unsigned int cd_gpio;
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u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
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unsigned long caps;
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