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drm/radeon: Add a rmb() in IH processing

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We should have a read memory barrier between reading the WPTR from
memory and reading ring entries based on that value (ie, we need to
ensure both loads are done in order by the CPU).

It could be argued that the MMIO reads in r600_ack_irq() might be
enough to get that barrier but I prefer keeping an explicit one just
in case.

[airlied: fix evergreen + r/w mixup]

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Benjamin Herrenschmidt 2011-07-13 16:28:19 +10:00 committed by Dave Airlie
parent f1bece7fde
commit 964f664520
2 changed files with 6 additions and 0 deletions
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3
drivers/gpu/drm/radeon/evergreen.c
View File

@ -2759,6 +2759,9 @@ int evergreen_irq_process(struct radeon_device *rdev)
return IRQ_NONE; return IRQ_NONE;
} }
restart_ih: restart_ih:
/* Order reading of wptr vs. reading of IH ring data */
rmb();
/* display interrupts */ /* display interrupts */
evergreen_irq_ack(rdev); evergreen_irq_ack(rdev);

3
drivers/gpu/drm/radeon/r600.c
View File

@ -3318,6 +3318,9 @@ int r600_irq_process(struct radeon_device *rdev)
} }
restart_ih: restart_ih:
/* Order reading of wptr vs. reading of IH ring data */
rmb();
/* display interrupts */ /* display interrupts */
r600_irq_ack(rdev); r600_irq_ack(rdev);