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x86/cpu: Add a "tsx=" cmdline option with TSX disabled by default
Add a kernel cmdline parameter "tsx" to control the Transactional Synchronization Extensions (TSX) feature. On CPUs that support TSX control, use "tsx=on|off" to enable or disable TSX. Not specifying this option is equivalent to "tsx=off". This is because on certain processors TSX may be used as a part of a speculative side channel attack. Carve out the TSX controlling functionality into a separate compilation unit because TSX is a CPU feature while the TSX async abort control machinery will go to cpu/bugs.c. [ bp: - Massage, shorten and clear the arg buffer. - Clarifications of the tsx= possible options - Josh. - Expand on TSX_CTRL availability - Pawan. ] Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
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@ -4848,6 +4848,32 @@
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interruptions from clocksource watchdog are not
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acceptable).
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tsx= [X86] Control Transactional Synchronization
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Extensions (TSX) feature in Intel processors that
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support TSX control.
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This parameter controls the TSX feature. The options are:
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on - Enable TSX on the system. Although there are
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mitigations for all known security vulnerabilities,
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TSX has been known to be an accelerator for
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several previous speculation-related CVEs, and
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so there may be unknown security risks associated
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with leaving it enabled.
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off - Disable TSX on the system. (Note that this
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option takes effect only on newer CPUs which are
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not vulnerable to MDS, i.e., have
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MSR_IA32_ARCH_CAPABILITIES.MDS_NO=1 and which get
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the new IA32_TSX_CTRL MSR through a microcode
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update. This new MSR allows for the reliable
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deactivation of the TSX functionality.)
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Not specifying this option is equivalent to tsx=off.
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See Documentation/admin-guide/hw-vuln/tsx_async_abort.rst
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for more details.
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turbografx.map[2|3]= [HW,JOY]
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TurboGraFX parallel port interface
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Format:
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@ -30,7 +30,7 @@ obj-$(CONFIG_PROC_FS) += proc.o
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obj-$(CONFIG_X86_FEATURE_NAMES) += capflags.o powerflags.o
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ifdef CONFIG_CPU_SUP_INTEL
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obj-y += intel.o intel_pconfig.o
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obj-y += intel.o intel_pconfig.o tsx.o
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obj-$(CONFIG_PM) += intel_epb.o
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endif
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obj-$(CONFIG_CPU_SUP_AMD) += amd.o
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@ -1561,6 +1561,8 @@ void __init identify_boot_cpu(void)
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#endif
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cpu_detect_tlb(&boot_cpu_data);
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setup_cr_pinning();
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tsx_init();
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}
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void identify_secondary_cpu(struct cpuinfo_x86 *c)
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@ -44,6 +44,22 @@ struct _tlb_table {
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extern const struct cpu_dev *const __x86_cpu_dev_start[],
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*const __x86_cpu_dev_end[];
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#ifdef CONFIG_CPU_SUP_INTEL
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enum tsx_ctrl_states {
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TSX_CTRL_ENABLE,
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TSX_CTRL_DISABLE,
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TSX_CTRL_NOT_SUPPORTED,
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};
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extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;
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extern void __init tsx_init(void);
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extern void tsx_enable(void);
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extern void tsx_disable(void);
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#else
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static inline void tsx_init(void) { }
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#endif /* CONFIG_CPU_SUP_INTEL */
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extern void get_cpu_cap(struct cpuinfo_x86 *c);
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extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
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extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
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@ -762,6 +762,11 @@ static void init_intel(struct cpuinfo_x86 *c)
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detect_tme(c);
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init_intel_misc_features(c);
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if (tsx_ctrl_state == TSX_CTRL_ENABLE)
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tsx_enable();
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if (tsx_ctrl_state == TSX_CTRL_DISABLE)
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tsx_disable();
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}
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#ifdef CONFIG_X86_32
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125
arch/x86/kernel/cpu/tsx.c
Normal file
125
arch/x86/kernel/cpu/tsx.c
Normal file
@ -0,0 +1,125 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Transactional Synchronization Extensions (TSX) control.
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*
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* Copyright (C) 2019 Intel Corporation
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*
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* Author:
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* Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
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*/
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#include <linux/cpufeature.h>
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#include <asm/cmdline.h>
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#include "cpu.h"
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enum tsx_ctrl_states tsx_ctrl_state __ro_after_init = TSX_CTRL_NOT_SUPPORTED;
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void tsx_disable(void)
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{
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u64 tsx;
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rdmsrl(MSR_IA32_TSX_CTRL, tsx);
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/* Force all transactions to immediately abort */
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tsx |= TSX_CTRL_RTM_DISABLE;
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/*
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* Ensure TSX support is not enumerated in CPUID.
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* This is visible to userspace and will ensure they
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* do not waste resources trying TSX transactions that
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* will always abort.
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*/
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tsx |= TSX_CTRL_CPUID_CLEAR;
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wrmsrl(MSR_IA32_TSX_CTRL, tsx);
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}
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void tsx_enable(void)
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{
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u64 tsx;
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rdmsrl(MSR_IA32_TSX_CTRL, tsx);
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/* Enable the RTM feature in the cpu */
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tsx &= ~TSX_CTRL_RTM_DISABLE;
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/*
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* Ensure TSX support is enumerated in CPUID.
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* This is visible to userspace and will ensure they
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* can enumerate and use the TSX feature.
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*/
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tsx &= ~TSX_CTRL_CPUID_CLEAR;
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wrmsrl(MSR_IA32_TSX_CTRL, tsx);
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}
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static bool __init tsx_ctrl_is_supported(void)
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{
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u64 ia32_cap = x86_read_arch_cap_msr();
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/*
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* TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
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* MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
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*
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* TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
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* microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
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* bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
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* MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
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* tsx= cmdline requests will do nothing on CPUs without
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* MSR_IA32_TSX_CTRL support.
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*/
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return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR);
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}
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void __init tsx_init(void)
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{
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char arg[4] = {};
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int ret;
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if (!tsx_ctrl_is_supported())
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return;
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ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));
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if (ret >= 0) {
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if (!strcmp(arg, "on")) {
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tsx_ctrl_state = TSX_CTRL_ENABLE;
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} else if (!strcmp(arg, "off")) {
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tsx_ctrl_state = TSX_CTRL_DISABLE;
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} else {
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tsx_ctrl_state = TSX_CTRL_DISABLE;
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pr_err("tsx: invalid option, defaulting to off\n");
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}
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} else {
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/* tsx= not provided, defaulting to off */
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tsx_ctrl_state = TSX_CTRL_DISABLE;
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}
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if (tsx_ctrl_state == TSX_CTRL_DISABLE) {
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tsx_disable();
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/*
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* tsx_disable() will change the state of the
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* RTM CPUID bit. Clear it here since it is now
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* expected to be not set.
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*/
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setup_clear_cpu_cap(X86_FEATURE_RTM);
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} else if (tsx_ctrl_state == TSX_CTRL_ENABLE) {
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/*
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* HW defaults TSX to be enabled at bootup.
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* We may still need the TSX enable support
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* during init for special cases like
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* kexec after TSX is disabled.
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*/
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tsx_enable();
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/*
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* tsx_enable() will change the state of the
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* RTM CPUID bit. Force it here since it is now
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* expected to be set.
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*/
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setup_force_cpu_cap(X86_FEATURE_RTM);
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}
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}
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