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[media] lirc: lirc_ene0100.h is not referenced anywhere
There is a proper ene0100 driver anyway. Signed-off-by: Sean Young <sean@mess.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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Sean Young
Mauro Carvalho Chehab
parent
a79bc3c592
commit
95aeead28a
@ -1,169 +0,0 @@
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/*
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* driver for ENE KB3926 B/C/D CIR (also known as ENE0100)
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*
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* Copyright (C) 2009 Maxim Levitsky <maximlevitsky@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#include <media/lirc.h>
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#include <media/lirc_dev.h>
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/* hardware address */
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#define ENE_STATUS 0 /* hardware status - unused */
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#define ENE_ADDR_HI 1 /* hi byte of register address */
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#define ENE_ADDR_LO 2 /* low byte of register address */
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#define ENE_IO 3 /* read/write window */
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#define ENE_MAX_IO 4
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/* 8 bytes of samples, divided in 2 halfs*/
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#define ENE_SAMPLE_BUFFER 0xF8F0 /* regular sample buffer */
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#define ENE_SAMPLE_SPC_MASK (1 << 7) /* sample is space */
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#define ENE_SAMPLE_VALUE_MASK 0x7F
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#define ENE_SAMPLE_OVERFLOW 0x7F
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#define ENE_SAMPLES_SIZE 4
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/* fan input sample buffer */
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#define ENE_SAMPLE_BUFFER_FAN 0xF8FB /* this buffer holds high byte of */
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/* each sample of normal buffer */
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#define ENE_FAN_SMPL_PULS_MSK 0x8000 /* this bit of combined sample */
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/* if set, says that sample is pulse */
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#define ENE_FAN_VALUE_MASK 0x0FFF /* mask for valid bits of the value */
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/* first firmware register */
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#define ENE_FW1 0xF8F8
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#define ENE_FW1_ENABLE (1 << 0) /* enable fw processing */
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#define ENE_FW1_TXIRQ (1 << 1) /* TX interrupt pending */
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#define ENE_FW1_WAKE (1 << 6) /* enable wake from S3 */
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#define ENE_FW1_IRQ (1 << 7) /* enable interrupt */
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/* second firmware register */
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#define ENE_FW2 0xF8F9
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#define ENE_FW2_BUF_HIGH (1 << 0) /* which half of the buffer to read */
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#define ENE_FW2_IRQ_CLR (1 << 2) /* clear this on IRQ */
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#define ENE_FW2_GP40_AS_LEARN (1 << 4) /* normal input is used as */
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/* learning input */
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#define ENE_FW2_FAN_AS_NRML_IN (1 << 6) /* fan is used as normal input */
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#define ENE_FW2_LEARNING (1 << 7) /* hardware supports learning and TX */
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/* fan as input settings - only if learning capable */
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#define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */
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#define ENE_FAN_AS_IN1_EN 0xCD
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#define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */
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#define ENE_FAN_AS_IN2_EN 0x03
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#define ENE_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
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/* IRQ registers block (for revision B) */
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#define ENEB_IRQ 0xFD09 /* IRQ number */
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#define ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */
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#define ENEB_IRQ_STATUS 0xFD80 /* irq status */
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#define ENEB_IRQ_STATUS_IR (1 << 5) /* IR irq */
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/* IRQ registers block (for revision C,D) */
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#define ENEC_IRQ 0xFE9B /* new irq settings register */
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#define ENEC_IRQ_MASK 0x0F /* irq number mask */
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#define ENEC_IRQ_UNK_EN (1 << 4) /* always enabled */
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#define ENEC_IRQ_STATUS (1 << 5) /* irq status and ACK */
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/* CIR block settings */
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#define ENE_CIR_CONF1 0xFEC0
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#define ENE_CIR_CONF1_ADC_ON 0x7 /* receiver on gpio40 enabled */
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#define ENE_CIR_CONF1_LEARN1 (1 << 3) /* enabled on learning mode */
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#define ENE_CIR_CONF1_TX_ON 0x30 /* enabled on transmit */
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#define ENE_CIR_CONF1_TX_CARR (1 << 7) /* send TX carrier or not */
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#define ENE_CIR_CONF2 0xFEC1 /* unknown setting = 0 */
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#define ENE_CIR_CONF2_LEARN2 (1 << 4) /* set on enable learning */
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#define ENE_CIR_CONF2_GPIO40DIS (1 << 5) /* disable normal input via gpio40 */
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#define ENE_CIR_SAMPLE_PERIOD 0xFEC8 /* sample period in us */
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#define ENE_CIR_SAMPLE_OVERFLOW (1 << 7) /* interrupt on overflows if set */
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/* transmitter - not implemented yet */
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/* KB3926C and higher */
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/* transmission is very similar to receiving, a byte is written to */
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/* ENE_TX_INPUT, in same manner as it is read from sample buffer */
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/* sample period is fixed*/
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/* transmitter ports */
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#define ENE_TX_PORT1 0xFC01 /* this enables one or both */
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#define ENE_TX_PORT1_EN (1 << 5) /* TX ports */
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#define ENE_TX_PORT2 0xFC08
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#define ENE_TX_PORT2_EN (1 << 1)
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#define ENE_TX_INPUT 0xFEC9 /* next byte to transmit */
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#define ENE_TX_SPC_MASK (1 << 7) /* Transmitted sample is space */
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#define ENE_TX_UNK1 0xFECB /* set to 0x63 */
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#define ENE_TX_SMPL_PERIOD 50 /* transmit sample period */
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#define ENE_TX_CARRIER 0xFECE /* TX carrier * 2 (khz) */
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#define ENE_TX_CARRIER_UNKBIT 0x80 /* This bit set on transmit */
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#define ENE_TX_CARRIER_LOW 0xFECF /* TX carrier / 2 */
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/* Hardware versions */
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#define ENE_HW_VERSION 0xFF00 /* hardware revision */
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#define ENE_HW_UNK 0xFF1D
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#define ENE_HW_UNK_CLR (1 << 2)
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#define ENE_HW_VER_MAJOR 0xFF1E /* chip version */
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#define ENE_HW_VER_MINOR 0xFF1F
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#define ENE_HW_VER_OLD 0xFD00
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#define same_sign(a, b) ((((a) > 0) && (b) > 0) || ((a) < 0 && (b) < 0))
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#define ENE_DRIVER_NAME "enecir"
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#define ENE_MAXGAP 250000 /* this is amount of time we wait
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before turning the sampler, chosen
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arbitry */
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#define space(len) (-(len)) /* add a space */
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/* software defines */
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#define ENE_IRQ_RX 1
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#define ENE_IRQ_TX 2
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#define ENE_HW_B 1 /* 3926B */
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#define ENE_HW_C 2 /* 3926C */
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#define ENE_HW_D 3 /* 3926D */
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#define ene_printk(level, text, ...) \
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printk(level ENE_DRIVER_NAME ": " text, ## __VA_ARGS__)
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struct ene_device {
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struct pnp_dev *pnp_dev;
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struct lirc_driver *lirc_driver;
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/* hw settings */
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unsigned long hw_io;
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int irq;
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int hw_revision; /* hardware revision */
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int hw_learning_and_tx_capable; /* learning capable */
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int hw_gpio40_learning; /* gpio40 is learning */
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int hw_fan_as_normal_input; /* fan input is used as regular input */
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/* device data */
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int idle;
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int fan_input_inuse;
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int sample;
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int in_use;
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struct timeval gap_start;
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};
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