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RISC-V Devicetrees for v6.11

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Sopgho:
 Add clock support for SG2042.
 
 Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
 -----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEdoBX2jyDC9ZCTwZjDCzASqG0i0IFAmaMg3wACgkQDCzASqG0
 i0Jh1wv/SVACZmbHdQ0ldCrjdPeSDQ5cN+TP2NHihFfE8+H7rzP/baHv9EnezGVQ
 Jcjw4Qj8uYqggN0wpWbWvuHC8tNPSrYIoQgbtnjyLBEjtwFINSOx7vwvldBszN1g
 ZXQuAf5KRyuBAcqUTVUBqX9bsZ9BvNvrV3xcLL9PZzH05tQiQG4J5ix9DF6wfkNW
 7O0Ibz88EnTAUOhqLWiR+tOB6Us/fN2lZPgyVHjqy3L3OqwsDOtGjMlfDuCW2SJk
 Yw9Yi1tjSCr3Vipvz5RgJfuCElgOTgJCcyW6EkR9aBmVflpBQpFFYsw88EFA7qeO
 sKWKdln2+DuX9xqneDmpVLr7uEBP3QDdI+lr+gjC07k3lVO778meOqYa+NHIFhRL
 zT+VZ9NPD311/mNXt67yUoBntA7SgeaE6hPpcYeXEpl05T4nN9rdyFFNWm/IF3qH
 7gd07Z78e8Cl02fz4V2rMdK61+2vfDbCITrCmbCChaWAdiPgI2Glo6ejGns+xzcw
 dPzLpga/
 =NA9d
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmaM+eMACgkQYKtH/8kJ
 UicYiw//ZH53sAC+TS2NiaW6GeqcXf5FOyt5uJpjG/Sga+OJvWqlL4rd9068aTGv
 Jvx0ZbFm0pml3OaVH7k23xyyGQN74v12Wnj9mZvKaTXTv2MKJfUMN+v3HkbUcju8
 OBGrQcYdxWCg7ZYSDVYdm+ni6HwxiEripjRaVLbBIiAog+HkDtFs0ynpMLDv38MN
 0rdFT5v7Zmfcz226De4zmhA2HK/1eP+vhsl3A/BqozUOk4z6J2eJQ8dUIwri8Cn3
 YAttT0DPasdi3C8DBW0YZpwRIPYcpmPpjgtUyuc6LnqwWnsw+2HPCZsvpT0P336F
 67ZHjYcKPQSPwqCicIgY94s2oqCWuDftD5kUfiQR7y6qfmQB/g0G3PCStH+DHBCC
 SXWOlRjIiACCycMVa1b7CKxCbo524/TjKd6Buf9RpxxrYV6IFaCMx6KH+rQMMa+f
 UV8yXJ7bP0OttvX4jpMelZpdH52Zk6SciJ2MHI7Ca2PHWBKeIPsWmMQeMqEHJ4hi
 ecEZIHMJ3iuhZ1aCv11LMtvFIDUVRyzgPybp241MXiCeSE0pg8QfiQazfnqidwsw
 a7hYb7ic+sCRhNx0QoFnGWQf4Y8PCf/8/oVHXyHFUGtTDM25Z4a1Prp5ax9JW0xx
 FTt7TRIxCTVTrCHWliEk2SiUbje9PWl3lCIPITOt7B9ZW5jYazA=
 =kAb0
 -----END PGP SIGNATURE-----

Merge tag 'riscv-sophgo-dt-for-v6.11' of https://github.com/sophgo/linux into soc/dt

RISC-V Devicetrees for v6.11

Sopgho:
Add clock support for SG2042.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* tag 'riscv-sophgo-dt-for-v6.11' of https://github.com/sophgo/linux:
  riscv: dts: add clock generator for Sophgo SG2042 SoC

Link: https://lore.kernel.org/r/PN1P287MB281861EA2B1706B430D2FA3EFEDB2@PN1P287MB2818.INDP287.PROD.OUTLOOK.COM
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-07-09 10:50:42 +02:00
commit 95ab7b209b
2 changed files with 66 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
View File

@ -14,6 +14,18 @@
};
};
&cgi_main {
clock-frequency = <25000000>;
};
&cgi_dpll0 {
clock-frequency = <25000000>;
};
&cgi_dpll1 {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};

55
arch/riscv/boot/dts/sophgo/sg2042.dtsi
View File

@ -4,8 +4,10 @@
*/
/dts-v1/;
#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
#include <dt-bindings/clock/sophgo,sg2042-pll.h>
#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/sophgo,sg2042-reset.h>
#include "sg2042-cpus.dtsi"
@ -20,12 +22,60 @@
serial0 = &uart0;
};
cgi_main: oscillator0 {
compatible = "fixed-clock";
clock-output-names = "cgi_main";
#clock-cells = <0>;
};
cgi_dpll0: oscillator1 {
compatible = "fixed-clock";
clock-output-names = "cgi_dpll0";
#clock-cells = <0>;
};
cgi_dpll1: oscillator2 {
compatible = "fixed-clock";
clock-output-names = "cgi_dpll1";
#clock-cells = <0>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
pllclk: clock-controller@70300100c0 {
compatible = "sophgo,sg2042-pll";
reg = <0x70 0x300100c0 0x0 0x40>;
clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
#clock-cells = <1>;
};
rpgate: clock-controller@7030010368 {
compatible = "sophgo,sg2042-rpgate";
reg = <0x70 0x30010368 0x0 0x98>;
clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
clock-names = "rpgate";
#clock-cells = <1>;
};
clkgen: clock-controller@7030012000 {
compatible = "sophgo,sg2042-clkgen";
reg = <0x70 0x30012000 0x0 0x1000>;
clocks = <&pllclk MPLL_CLK>,
<&pllclk FPLL_CLK>,
<&pllclk DPLL0_CLK>,
<&pllclk DPLL1_CLK>;
clock-names = "mpll",
"fpll",
"dpll0",
"dpll1";
#clock-cells = <1>;
};
clint_mswi: interrupt-controller@7094000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
@ -341,6 +391,9 @@
interrupt-parent = <&intc>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clocks = <&clkgen GATE_CLK_UART_500M>,
<&clkgen GATE_CLK_APB_UART>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rstgen RST_UART0>;