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MIPS: Netlogic: Split reset code out of smpboot.S
The reset and core initialization code should be available for uniprocessor as well. This changes is just to take out the code into a different file, without any change to the logic. The change for uniprocessor initialization code is in a later patch. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5423/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jayachandran C
Ralf Baechle
parent
aceee09d4f
commit
9584c55a5c
@ -71,6 +71,7 @@ nlm_set_nmi_handler(void *handler)
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/*
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* Misc.
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*/
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void nlm_init_boot_cpu(void);
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unsigned int nlm_get_cpu_frequency(void);
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void nlm_node_init(int node);
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extern struct plat_smp_ops nlm_smp_ops;
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@ -1,4 +1,4 @@
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obj-y += irq.o time.o
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obj-y += nlm-dma.o
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obj-$(CONFIG_SMP) += smp.o smpboot.o
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obj-$(CONFIG_SMP) += smp.o smpboot.o reset.o
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obj-$(CONFIG_EARLY_PRINTK) += earlycons.o
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249
arch/mips/netlogic/common/reset.S
Normal file
249
arch/mips/netlogic/common/reset.S
Normal file
@ -0,0 +1,249 @@
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/*
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* Copyright 2003-2013 Broadcom Corporation.
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* All Rights Reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/init.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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#include <asm/asmmacro.h>
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#include <asm/addrspace.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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#include <asm/netlogic/xlp-hal/cpucontrol.h>
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#define CP0_EBASE $15
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#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
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XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
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SYS_CPU_NONCOHERENT_MODE * 4
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#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */
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/* Enable XLP features and workarounds in the LSU */
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.macro xlp_config_lsu
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li t0, LSU_DEFEATURE
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mfcr t1, t0
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lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */
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or t1, t1, t2
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#ifdef XLP_AX_WORKAROUND
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li t2, ~0xe /* S1RCM */
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and t1, t1, t2
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#endif
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mtcr t1, t0
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li t0, ICU_DEFEATURE
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mfcr t1, t0
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ori t1, 0x1000 /* Enable Icache partitioning */
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mtcr t1, t0
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#ifdef XLP_AX_WORKAROUND
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li t0, SCHED_DEFEATURE
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lui t1, 0x0100 /* Disable BRU accepting ALU ops */
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mtcr t1, t0
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#endif
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.endm
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/*
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* Low level flush for L1D cache on XLP, the normal cache ops does
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* not do the complete and correct cache flush.
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*/
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.macro xlp_flush_l1_dcache
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li t0, LSU_DEBUG_DATA0
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li t1, LSU_DEBUG_ADDR
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li t2, 0 /* index */
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li t3, 0x1000 /* loop count */
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1:
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sll v0, t2, 5
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mtcr zero, t0
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ori v1, v0, 0x3 /* way0 | write_enable | write_active */
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mtcr v1, t1
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2:
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mfcr v1, t1
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andi v1, 0x1 /* wait for write_active == 0 */
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bnez v1, 2b
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nop
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mtcr zero, t0
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ori v1, v0, 0x7 /* way1 | write_enable | write_active */
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mtcr v1, t1
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3:
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mfcr v1, t1
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andi v1, 0x1 /* wait for write_active == 0 */
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bnez v1, 3b
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nop
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addi t2, 1
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bne t3, t2, 1b
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nop
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.endm
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/*
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* nlm_reset_entry will be copied to the reset entry point for
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* XLR and XLP. The XLP cores start here when they are woken up. This
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* is also the NMI entry point.
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*
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* We use scratch reg 6/7 to save k0/k1 and check for NMI first.
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*
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* The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
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* location, this will have the thread mask (used when core is woken up)
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* and the current NMI handler in case we reached here for an NMI.
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*
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* When a core or thread is newly woken up, it marks itself ready and
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* loops in a 'wait'. When the CPU really needs waking up, we send an NMI
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* IPI to it, with the NMI handler set to prom_boot_secondary_cpus
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*/
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.set noreorder
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.set noat
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.set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
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FEXPORT(nlm_reset_entry)
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dmtc0 k0, $22, 6
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dmtc0 k1, $22, 7
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mfc0 k0, CP0_STATUS
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li k1, 0x80000
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and k1, k0, k1
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beqz k1, 1f /* go to real reset entry */
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nop
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li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
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ld k0, BOOT_NMI_HANDLER(k1)
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jr k0
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nop
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1: /* Entry point on core wakeup */
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mfc0 t0, CP0_EBASE, 1
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mfc0 t1, CP0_EBASE, 1
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srl t1, 5
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andi t1, 0x3 /* t1 <- node */
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li t2, 0x40000
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mul t3, t2, t1 /* t3 = node * 0x40000 */
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srl t0, t0, 2
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and t0, t0, 0x7 /* t0 <- core */
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li t1, 0x1
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sll t0, t1, t0
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nor t0, t0, zero /* t0 <- ~(1 << core) */
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li t2, SYS_CPU_COHERENT_BASE(0)
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add t2, t2, t3 /* t2 <- SYS offset for node */
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lw t1, 0(t2)
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and t1, t1, t0
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sw t1, 0(t2)
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/* read back to ensure complete */
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lw t1, 0(t2)
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sync
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/* Configure LSU on Non-0 Cores. */
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xlp_config_lsu
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/* FALL THROUGH */
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/*
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* Wake up sibling threads from the initial thread in
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* a core.
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*/
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EXPORT(nlm_boot_siblings)
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/* core L1D flush before enable threads */
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xlp_flush_l1_dcache
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/* Enable hw threads by writing to MAP_THREADMODE of the core */
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li t0, CKSEG1ADDR(RESET_DATA_PHYS)
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lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
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li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
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mfcr t2, t0
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or t2, t2, t1
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mtcr t2, t0
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/*
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* The new hardware thread starts at the next instruction
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* For all the cases other than core 0 thread 0, we will
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* jump to the secondary wait function.
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*/
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mfc0 v0, CP0_EBASE, 1
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andi v0, 0x3ff /* v0 <- node/core */
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/* Init MMU in the first thread after changing THREAD_MODE
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* register (Ax Errata?)
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*/
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andi v1, v0, 0x3 /* v1 <- thread id */
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bnez v1, 2f
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nop
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li t0, MMU_SETUP
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li t1, 0
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mtcr t1, t0
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_ehb
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2: beqz v0, 4f /* boot cpu (cpuid == 0)? */
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nop
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/* setup status reg */
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move t1, zero
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#ifdef CONFIG_64BIT
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ori t1, ST0_KX
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#endif
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mtc0 t1, CP0_STATUS
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/* mark CPU ready */
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PTR_LA t1, nlm_cpu_ready
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sll v1, v0, 2
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PTR_ADDU t1, v1
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li t2, 1
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sw t2, 0(t1)
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/* Wait until NMI hits */
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3: wait
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j 3b
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nop
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/*
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* For the boot CPU, we have to restore registers and
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* return
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*/
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4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
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li t1, 0xfadebeef
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dmtc0 t1, $4, 2 /* restore SP from UserLocal */
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PTR_SUBU sp, t0, PT_SIZE
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RESTORE_ALL
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jr ra
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nop
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EXPORT(nlm_reset_entry_end)
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LEAF(nlm_init_boot_cpu)
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#ifdef CONFIG_CPU_XLP
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xlp_config_lsu
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#endif
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jr ra
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nop
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END(nlm_init_boot_cpu)
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@ -50,197 +50,12 @@
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#include <asm/netlogic/xlp-hal/cpucontrol.h>
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#define CP0_EBASE $15
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#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
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XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
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SYS_CPU_NONCOHERENT_MODE * 4
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#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */
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/* Enable XLP features and workarounds in the LSU */
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.macro xlp_config_lsu
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li t0, LSU_DEFEATURE
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mfcr t1, t0
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lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */
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or t1, t1, t2
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#ifdef XLP_AX_WORKAROUND
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li t2, ~0xe /* S1RCM */
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and t1, t1, t2
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#endif
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mtcr t1, t0
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li t0, ICU_DEFEATURE
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mfcr t1, t0
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ori t1, 0x1000 /* Enable Icache partitioning */
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mtcr t1, t0
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#ifdef XLP_AX_WORKAROUND
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li t0, SCHED_DEFEATURE
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lui t1, 0x0100 /* Disable BRU accepting ALU ops */
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mtcr t1, t0
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#endif
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.endm
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/*
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* This is the code that will be copied to the reset entry point for
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* XLR and XLP. The XLP cores start here when they are woken up. This
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* is also the NMI entry point.
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*/
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.macro xlp_flush_l1_dcache
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li t0, LSU_DEBUG_DATA0
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li t1, LSU_DEBUG_ADDR
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li t2, 0 /* index */
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li t3, 0x1000 /* loop count */
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1:
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sll v0, t2, 5
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mtcr zero, t0
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ori v1, v0, 0x3 /* way0 | write_enable | write_active */
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mtcr v1, t1
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2:
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mfcr v1, t1
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andi v1, 0x1 /* wait for write_active == 0 */
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bnez v1, 2b
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nop
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mtcr zero, t0
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ori v1, v0, 0x7 /* way1 | write_enable | write_active */
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mtcr v1, t1
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3:
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mfcr v1, t1
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andi v1, 0x1 /* wait for write_active == 0 */
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bnez v1, 3b
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nop
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addi t2, 1
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bne t3, t2, 1b
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nop
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.endm
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/*
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* The cores can come start when they are woken up. This is also the NMI
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* entry, so check that first.
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*
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* The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
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* location, this will have the thread mask (used when core is woken up)
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* and the current NMI handler in case we reached here for an NMI.
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*
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* When a core or thread is newly woken up, it loops in a 'wait'. When
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* the CPU really needs waking up, we send an NMI to it, with the NMI
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* handler set to prom_boot_secondary_cpus
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*/
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.set noreorder
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.set noat
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.set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
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FEXPORT(nlm_reset_entry)
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dmtc0 k0, $22, 6
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dmtc0 k1, $22, 7
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mfc0 k0, CP0_STATUS
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li k1, 0x80000
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and k1, k0, k1
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beqz k1, 1f /* go to real reset entry */
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nop
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li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
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ld k0, BOOT_NMI_HANDLER(k1)
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jr k0
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nop
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1: /* Entry point on core wakeup */
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mfc0 t0, CP0_EBASE, 1
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mfc0 t1, CP0_EBASE, 1
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srl t1, 5
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andi t1, 0x3 /* t1 <- node */
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li t2, 0x40000
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mul t3, t2, t1 /* t3 = node * 0x40000 */
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srl t0, t0, 2
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and t0, t0, 0x7 /* t0 <- core */
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li t1, 0x1
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sll t0, t1, t0
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nor t0, t0, zero /* t0 <- ~(1 << core) */
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li t2, SYS_CPU_COHERENT_BASE(0)
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add t2, t2, t3 /* t2 <- SYS offset for node */
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lw t1, 0(t2)
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and t1, t1, t0
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sw t1, 0(t2)
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/* read back to ensure complete */
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lw t1, 0(t2)
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sync
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/* Configure LSU on Non-0 Cores. */
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xlp_config_lsu
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/* FALL THROUGH */
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/*
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* Wake up sibling threads from the initial thread in
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* a core.
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*/
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EXPORT(nlm_boot_siblings)
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/* core L1D flush before enable threads */
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xlp_flush_l1_dcache
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/* Enable hw threads by writing to MAP_THREADMODE of the core */
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li t0, CKSEG1ADDR(RESET_DATA_PHYS)
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lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
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li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
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mfcr t2, t0
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or t2, t2, t1
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mtcr t2, t0
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/*
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* The new hardware thread starts at the next instruction
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* For all the cases other than core 0 thread 0, we will
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* jump to the secondary wait function.
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*/
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mfc0 v0, CP0_EBASE, 1
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andi v0, 0x3ff /* v0 <- node/core */
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/* Init MMU in the first thread after changing THREAD_MODE
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* register (Ax Errata?)
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*/
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andi v1, v0, 0x3 /* v1 <- thread id */
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bnez v1, 2f
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nop
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li t0, MMU_SETUP
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li t1, 0
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mtcr t1, t0
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_ehb
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2: beqz v0, 4f /* boot cpu (cpuid == 0)? */
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nop
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/* setup status reg */
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move t1, zero
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#ifdef CONFIG_64BIT
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ori t1, ST0_KX
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#endif
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mtc0 t1, CP0_STATUS
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/* mark CPU ready */
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PTR_LA t1, nlm_cpu_ready
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sll v1, v0, 2
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PTR_ADDU t1, v1
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li t2, 1
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sw t2, 0(t1)
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/* Wait until NMI hits */
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3: wait
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j 3b
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nop
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/*
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* For the boot CPU, we have to restore registers and
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* return
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*/
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4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
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li t1, 0xfadebeef
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dmtc0 t1, $4, 2 /* restore SP from UserLocal */
|
||||
PTR_SUBU sp, t0, PT_SIZE
|
||||
RESTORE_ALL
|
||||
jr ra
|
||||
nop
|
||||
EXPORT(nlm_reset_entry_end)
|
||||
.set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
|
||||
|
||||
FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
|
||||
xlp_config_lsu
|
||||
dmtc0 sp, $4, 2 /* SP saved in UserLocal */
|
||||
SAVE_ALL
|
||||
sync
|
||||
|
||||
@ -137,6 +137,7 @@ void xlp_wakeup_secondary_cpus()
|
||||
* In case of u-boot, the secondaries are in reset
|
||||
* first wakeup core 0 threads
|
||||
*/
|
||||
nlm_init_boot_cpu();
|
||||
xlp_boot_core0_siblings();
|
||||
|
||||
/* now get other cores out of reset */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user