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omap2/3: Make get_irqnr_and_base common for mach-omap2 multiboot

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Make get_irqnr_and_base common for mach-omap2 multiboot

Thanks to a tip from Russell King <rmk+kernel@arm.linux.org.uk>,
this also optimizes the code for non-multiboot configurations by
using get_irqnr_preamble.

Note that this will only work currently for 24xx and 34xx.
Support for 44xx can be added later on for basic multiboot,
and similar patch should be done for mach-omap1/entry-macro.S.

Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren 2010-02-15 09:26:51 -08:00
parent be26a3df0b
commit 9556175183
1 changed files with 57 additions and 20 deletions
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77
arch/arm/mach-omap2/include/mach/entry-macro.S
View File

@ -17,47 +17,84 @@
#include <plat/omap24xx.h>
#include <plat/omap34xx.h>
/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
#elif defined(CONFIG_ARCH_OMAP34XX)
#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
#endif
#if defined(CONFIG_ARCH_OMAP4)
#include <plat/omap44xx.h>
#endif
#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */
#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
#ifndef CONFIG_ARCH_OMAP4
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */
#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */
.pushsection .data
omap_irq_base: .word 0
.popsection
#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_ARCH_OMAP3)
/* Configure the interrupt base on the first interrupt */
.macro get_irqnr_preamble, base, tmp
9:
ldr \base, =omap_irq_base @ irq base address
ldr \base, [\base, #0] @ irq base value
cmp \base, #0 @ already configured?
bne 9998f @ nothing to do
mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
and \tmp, \tmp, #0x000f0000 @ only check architecture
cmp \tmp, #0x00060000 @ is v6?
beq 2400f @ found v6 so it's omap24xx
cmp \tmp, #0x000f0000 @ is cortex?
beq 3400f @ found v7 so it's omap34xx
2400: ldr \base, =OMAP2_IRQ_BASE
ldr \tmp, =omap_irq_base
str \base, [\tmp, #0]
b 9b
3400: ldr \base, =OMAP3_IRQ_BASE
ldr \tmp, =omap_irq_base
str \base, [\tmp, #0]
b 9b
9998:
.endm
#else
.macro get_irqnr_preamble, base, tmp
#ifdef CONFIG_ARCH_OMAP2
ldr \base, =OMAP2_IRQ_BASE
#else
ldr \base, =OMAP3_IRQ_BASE
#endif
.endm
#endif
/* Check the pending interrupts. Note that base already set */
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =OMAP2_VA_IC_BASE
ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
cmp \irqnr, #0x0
bne 2222f
bne 9999f
ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
cmp \irqnr, #0x0
bne 2222f
bne 9999f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
2222:
9999:
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
.endm
#else
#endif
#ifdef CONFIG_ARCH_OMAP4
#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
.macro get_irqnr_preamble, base, tmp
.endm
/*
* The interrupt numbering scheme is defined in the
* interrupt controller spec. To wit: