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riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC

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The Andes hart-level interrupt controller (Andes INTC) allows AX45MP
cores to handle custom local interrupts, such as the performance
counter overflow interrupt.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240222083946.3977135-6-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Yu Chien Peter Lin 2024-02-22 16:39:41 +08:00 committed by Palmer Dabbelt
parent b88727d554
commit 95113bb705
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1 changed files with 1 additions and 1 deletions
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arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
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@ -39,7 +39,7 @@
cpu0_intc: interrupt-controller { cpu0_intc: interrupt-controller {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "riscv,cpu-intc"; compatible = "andestech,cpu-intc", "riscv,cpu-intc";
interrupt-controller; interrupt-controller;
}; };
}; };