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MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions
MIPSR6 CPUs do not support unaligned load/store instructions
(LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
Currently the MIPS tree has some special cases to avoid these
instructions, and the code is testing for !CONFIG_CPU_MIPSR6.
This patch declares a new Kconfig variable:
CONFIG_CPU_HAS_LOAD_STORE_LR.
This variable indicates that the CPU supports these instructions.
Then, the patch does the following:
- Carefully selects this option on all CPUs except MIPSR6.
- Switches all the special cases to test for the new variable,
and inverts the logic:
'#ifndef CONFIG_CPU_MIPSR6' turns into
'#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR'
and vice-versa.
Also, when this variable is NOT selected (e.g. MIPSR6),
CONFIG_GENERIC_CSUM will default to 'y', to compile generic
C checksum code (instead of special assembly code that uses the
unsupported instructions).
This commit should not affect any existing CPU, and is required
for future Lexra CPU support, that misses these instructions too.
Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20808/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
This commit is contained in:
Yasha Cherikovsky
Paul Burton
parent
d9df9fb901
commit
932afdeec1
@ -1150,6 +1150,7 @@ config NO_IOPORT_MAP
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config GENERIC_CSUM
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bool
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default y if !CPU_HAS_LOAD_STORE_LR
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config GENERIC_ISA_DMA
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bool
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@ -1368,6 +1369,7 @@ config CPU_LOONGSON3
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_HUGEPAGES
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select CPU_HAS_LOAD_STORE_LR
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select WEAK_ORDERING
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select WEAK_REORDERING_BEYOND_LLSC
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select MIPS_PGD_C0_CONTEXT
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@ -1444,6 +1446,7 @@ config CPU_MIPS32_R1
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bool "MIPS32 Release 1"
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depends on SYS_HAS_CPU_MIPS32_R1
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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help
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@ -1461,6 +1464,7 @@ config CPU_MIPS32_R2
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bool "MIPS32 Release 2"
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depends on SYS_HAS_CPU_MIPS32_R2
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_MSA
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@ -1479,7 +1483,6 @@ config CPU_MIPS32_R6
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_MSA
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select GENERIC_CSUM
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select HAVE_KVM
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select MIPS_O32_FP64_SUPPORT
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help
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@ -1492,6 +1495,7 @@ config CPU_MIPS64_R1
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bool "MIPS64 Release 1"
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depends on SYS_HAS_CPU_MIPS64_R1
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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@ -1511,6 +1515,7 @@ config CPU_MIPS64_R2
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bool "MIPS64 Release 2"
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depends on SYS_HAS_CPU_MIPS64_R2
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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@ -1532,7 +1537,6 @@ config CPU_MIPS64_R6
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_MSA
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select GENERIC_CSUM
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select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
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select HAVE_KVM
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help
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@ -1545,6 +1549,7 @@ config CPU_R3000
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bool "R3000"
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depends on SYS_HAS_CPU_R3000
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select CPU_HAS_WB
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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help
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@ -1559,12 +1564,14 @@ config CPU_TX39XX
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bool "R39XX"
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depends on SYS_HAS_CPU_TX39XX
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_HAS_LOAD_STORE_LR
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config CPU_VR41XX
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bool "R41xx"
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depends on SYS_HAS_CPU_VR41XX
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_HAS_LOAD_STORE_LR
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help
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The options selects support for the NEC VR4100 series of processors.
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Only choose this option if you have one of these processors as a
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@ -1576,6 +1583,7 @@ config CPU_R4300
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depends on SYS_HAS_CPU_R4300
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_HAS_LOAD_STORE_LR
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help
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MIPS Technologies R4300-series processors.
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@ -1585,6 +1593,7 @@ config CPU_R4X00
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HUGEPAGES
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select CPU_HAS_LOAD_STORE_LR
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help
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MIPS Technologies R4000-series processors other than 4300, including
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the R4000, R4400, R4600, and 4700.
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@ -1593,6 +1602,7 @@ config CPU_TX49XX
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bool "R49XX"
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depends on SYS_HAS_CPU_TX49XX
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HUGEPAGES
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@ -1603,6 +1613,7 @@ config CPU_R5000
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HUGEPAGES
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select CPU_HAS_LOAD_STORE_LR
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help
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MIPS Technologies R5000-series processors other than the Nevada.
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@ -1612,6 +1623,7 @@ config CPU_R5432
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HUGEPAGES
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select CPU_HAS_LOAD_STORE_LR
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config CPU_R5500
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bool "R5500"
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@ -1619,6 +1631,7 @@ config CPU_R5500
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HUGEPAGES
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select CPU_HAS_LOAD_STORE_LR
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help
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NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
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instruction set.
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@ -1629,6 +1642,7 @@ config CPU_NEVADA
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HUGEPAGES
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select CPU_HAS_LOAD_STORE_LR
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help
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QED / PMC-Sierra RM52xx-series ("Nevada") processors.
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@ -1636,6 +1650,7 @@ config CPU_R8000
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bool "R8000"
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depends on SYS_HAS_CPU_R8000
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_64BIT_KERNEL
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help
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MIPS Technologies R8000 processors. Note these processors are
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@ -1645,6 +1660,7 @@ config CPU_R10000
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bool "R10000"
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depends on SYS_HAS_CPU_R10000
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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@ -1656,6 +1672,7 @@ config CPU_RM7000
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bool "RM7000"
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depends on SYS_HAS_CPU_RM7000
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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@ -1664,6 +1681,7 @@ config CPU_RM7000
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config CPU_SB1
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bool "SB1"
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depends on SYS_HAS_CPU_SB1
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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@ -1674,6 +1692,7 @@ config CPU_CAVIUM_OCTEON
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bool "Cavium Octeon processor"
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depends on SYS_HAS_CPU_CAVIUM_OCTEON
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_64BIT_KERNEL
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select WEAK_ORDERING
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select CPU_SUPPORTS_HIGHMEM
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@ -1703,6 +1722,7 @@ config CPU_BMIPS
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select WEAK_ORDERING
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select CPU_SUPPORTS_HIGHMEM
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_CPUFREQ
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select MIPS_EXTERNAL_TIMER
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help
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@ -1711,6 +1731,7 @@ config CPU_BMIPS
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config CPU_XLR
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bool "Netlogic XLR SoC"
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depends on SYS_HAS_CPU_XLR
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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@ -1729,6 +1750,7 @@ config CPU_XLP
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select WEAK_ORDERING
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select WEAK_REORDERING_BEYOND_LLSC
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_MIPSR2
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select CPU_SUPPORTS_HUGEPAGES
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select MIPS_ASID_BITS_VARIABLE
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@ -1834,12 +1856,14 @@ config CPU_LOONGSON2
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_HUGEPAGES
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select ARCH_HAS_PHYS_TO_DMA
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select CPU_HAS_LOAD_STORE_LR
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config CPU_LOONGSON1
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bool
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select CPU_MIPS32
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select CPU_MIPSR1
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_CPUFREQ
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@ -2453,6 +2477,13 @@ config XKS01
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config CPU_HAS_RIXI
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bool
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config CPU_HAS_LOAD_STORE_LR
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bool
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help
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CPU has support for unaligned load and store instructions:
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LWL, LWR, SWL, SWR (Load/store word left/right).
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LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit systems).
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#
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# Vectored interrupt mode is an R2 feature
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#
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@ -130,7 +130,7 @@ do { \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
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#define _LoadW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -151,8 +151,8 @@ do { \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has no lwl instruction */
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#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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/* For CPUs without lwl instruction */
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#define _LoadW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -186,7 +186,7 @@ do { \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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#define _LoadHWU(addr, value, res, type) \
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do { \
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@ -212,7 +212,7 @@ do { \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
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#define _LoadWU(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -255,8 +255,8 @@ do { \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has not lwl and ldl instructions */
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#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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/* For CPUs without lwl and ldl instructions */
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#define _LoadWU(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -339,7 +339,7 @@ do { \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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#define _StoreHW(addr, value, res, type) \
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@ -365,7 +365,7 @@ do { \
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: "r" (value), "r" (addr), "i" (-EFAULT));\
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
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#define _StoreW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -406,8 +406,7 @@ do { \
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: "r" (value), "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has no swl and sdl instructions */
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#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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#define _StoreW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -483,7 +482,7 @@ do { \
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: "memory"); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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#else /* __BIG_ENDIAN */
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@ -509,7 +508,7 @@ do { \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
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#define _LoadW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -530,8 +529,8 @@ do { \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has no lwl instruction */
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#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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/* For CPUs without lwl instruction */
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#define _LoadW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -565,7 +564,7 @@ do { \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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#define _LoadHWU(addr, value, res, type) \
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@ -592,7 +591,7 @@ do { \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
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#define _LoadWU(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -635,8 +634,8 @@ do { \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has not lwl and ldl instructions */
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#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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/* For CPUs without lwl and ldl instructions */
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#define _LoadWU(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -718,7 +717,7 @@ do { \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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#define _StoreHW(addr, value, res, type) \
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do { \
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@ -743,7 +742,7 @@ do { \
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: "r" (value), "r" (addr), "i" (-EFAULT));\
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
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#define _StoreW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -784,8 +783,8 @@ do { \
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: "r" (value), "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has no swl and sdl instructions */
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#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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/* For CPUs without swl and sdl instructions */
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#define _StoreW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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@ -861,7 +860,7 @@ do { \
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: "memory"); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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#endif
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|
||||
#define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel)
|
||||
|
||||
@ -297,7 +297,7 @@
|
||||
and t0, src, ADDRMASK
|
||||
PREFS( 0, 2*32(src) )
|
||||
PREFD( 1, 2*32(dst) )
|
||||
#ifndef CONFIG_CPU_MIPSR6
|
||||
#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
|
||||
bnez t1, .Ldst_unaligned\@
|
||||
nop
|
||||
bnez t0, .Lsrc_unaligned_dst_aligned\@
|
||||
@ -385,7 +385,7 @@
|
||||
bne rem, len, 1b
|
||||
.set noreorder
|
||||
|
||||
#ifndef CONFIG_CPU_MIPSR6
|
||||
#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
|
||||
/*
|
||||
* src and dst are aligned, need to copy rem bytes (rem < NBYTES)
|
||||
* A loop would do only a byte at a time with possible branch
|
||||
@ -487,7 +487,7 @@
|
||||
bne len, rem, 1b
|
||||
.set noreorder
|
||||
|
||||
#endif /* !CONFIG_CPU_MIPSR6 */
|
||||
#endif /* CONFIG_CPU_HAS_LOAD_STORE_LR */
|
||||
.Lcopy_bytes_checklen\@:
|
||||
beqz len, .Ldone\@
|
||||
nop
|
||||
@ -516,7 +516,7 @@
|
||||
jr ra
|
||||
nop
|
||||
|
||||
#ifdef CONFIG_CPU_MIPSR6
|
||||
#ifndef CONFIG_CPU_HAS_LOAD_STORE_LR
|
||||
.Lcopy_unaligned_bytes\@:
|
||||
1:
|
||||
COPY_BYTE(0)
|
||||
@ -530,7 +530,7 @@
|
||||
ADD src, src, 8
|
||||
b 1b
|
||||
ADD dst, dst, 8
|
||||
#endif /* CONFIG_CPU_MIPSR6 */
|
||||
#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
|
||||
.if __memcpy == 1
|
||||
END(memcpy)
|
||||
.set __memcpy, 0
|
||||
|
||||
@ -112,7 +112,7 @@
|
||||
.set at
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_CPU_MIPSR6
|
||||
#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
|
||||
R10KCBARRIER(0(ra))
|
||||
#ifdef __MIPSEB__
|
||||
EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
|
||||
@ -122,7 +122,7 @@
|
||||
PTR_SUBU a0, t0 /* long align ptr */
|
||||
PTR_ADDU a2, t0 /* correct size */
|
||||
|
||||
#else /* CONFIG_CPU_MIPSR6 */
|
||||
#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
|
||||
#define STORE_BYTE(N) \
|
||||
EX(sb, a1, N(a0), .Lbyte_fixup\@); \
|
||||
beqz t0, 0f; \
|
||||
@ -145,7 +145,7 @@
|
||||
ori a0, STORMASK
|
||||
xori a0, STORMASK
|
||||
PTR_ADDIU a0, STORSIZE
|
||||
#endif /* CONFIG_CPU_MIPSR6 */
|
||||
#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
|
||||
1: ori t1, a2, 0x3f /* # of full blocks */
|
||||
xori t1, 0x3f
|
||||
beqz t1, .Lmemset_partial\@ /* no block to fill */
|
||||
@ -185,7 +185,7 @@
|
||||
andi a2, STORMASK /* At most one long to go */
|
||||
|
||||
beqz a2, 1f
|
||||
#ifndef CONFIG_CPU_MIPSR6
|
||||
#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
|
||||
PTR_ADDU a0, a2 /* What's left */
|
||||
R10KCBARRIER(0(ra))
|
||||
#ifdef __MIPSEB__
|
||||
@ -230,7 +230,7 @@
|
||||
.hidden __memset
|
||||
.endif
|
||||
|
||||
#ifdef CONFIG_CPU_MIPSR6
|
||||
#ifndef CONFIG_CPU_HAS_LOAD_STORE_LR
|
||||
.Lbyte_fixup\@:
|
||||
/*
|
||||
* unset_bytes = (#bytes - (#unaligned bytes)) - (-#unaligned bytes remaining + 1) + 1
|
||||
@ -239,7 +239,7 @@
|
||||
PTR_SUBU a2, t0
|
||||
jr ra
|
||||
PTR_ADDIU a2, 1
|
||||
#endif /* CONFIG_CPU_MIPSR6 */
|
||||
#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
|
||||
|
||||
.Lfirst_fixup\@:
|
||||
/* unset_bytes already in a2 */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user