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powerpc: sstep: Add support for maddhd, maddhdu, maddld instructions
This adds emulation support for the following integer instructions: * Multiply-Add High Doubleword (maddhd) * Multiply-Add High Doubleword Unsigned (maddhdu) * Multiply-Add Low Doubleword (maddld) As suggested by Michael, this uses a raw .long for specifying the instruction word when using inline assembly to retain compatibility with older binutils. Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -335,6 +335,9 @@
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#define PPC_INST_MULLW 0x7c0001d6
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#define PPC_INST_MULHWU 0x7c000016
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#define PPC_INST_MULLI 0x1c000000
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#define PPC_INST_MADDHD 0x10000030
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#define PPC_INST_MADDHDU 0x10000031
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#define PPC_INST_MADDLD 0x10000033
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#define PPC_INST_DIVWU 0x7c000396
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#define PPC_INST_DIVD 0x7c0003d2
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#define PPC_INST_RLWINM 0x54000000
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@ -377,6 +380,7 @@
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/* macros to insert fields into opcodes */
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#define ___PPC_RA(a) (((a) & 0x1f) << 16)
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#define ___PPC_RB(b) (((b) & 0x1f) << 11)
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#define ___PPC_RC(c) (((c) & 0x1f) << 6)
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#define ___PPC_RS(s) (((s) & 0x1f) << 21)
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#define ___PPC_RT(t) ___PPC_RS(t)
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#define ___PPC_R(r) (((r) & 0x1) << 16)
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@ -396,7 +400,7 @@
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#define __PPC_WS(w) (((w) & 0x1f) << 11)
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#define __PPC_SH(s) __PPC_WS(s)
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#define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4))
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#define __PPC_MB(s) (((s) & 0x1f) << 6)
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#define __PPC_MB(s) ___PPC_RC(s)
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#define __PPC_ME(s) (((s) & 0x1f) << 1)
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#define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20))
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#define __PPC_ME64(s) __PPC_MB64(s)
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@ -438,6 +442,15 @@
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#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_INST_STQCX | \
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___PPC_RT(t) | ___PPC_RA(a) | \
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___PPC_RB(b))
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#define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_INST_MADDHD | \
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___PPC_RT(t) | ___PPC_RA(a) | \
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___PPC_RB(b) | ___PPC_RC(c))
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#define PPC_MADDHDU(t, a, b, c) stringify_in_c(.long PPC_INST_MADDHDU | \
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___PPC_RT(t) | ___PPC_RA(a) | \
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___PPC_RB(b) | ___PPC_RC(c))
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#define PPC_MADDLD(t, a, b, c) stringify_in_c(.long PPC_INST_MADDLD | \
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___PPC_RT(t) | ___PPC_RA(a) | \
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___PPC_RB(b) | ___PPC_RC(c))
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#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
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___PPC_RB(b))
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#define PPC_MSGSYNC stringify_in_c(.long PPC_INST_MSGSYNC)
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@ -1169,7 +1169,7 @@ static nokprobe_inline int trap_compare(long v1, long v2)
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int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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unsigned int instr)
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{
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unsigned int opcode, ra, rb, rd, spr, u;
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unsigned int opcode, ra, rb, rc, rd, spr, u;
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unsigned long int imm;
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unsigned long int val, val2;
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unsigned int mb, me, sh;
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@ -1292,6 +1292,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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rd = (instr >> 21) & 0x1f;
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ra = (instr >> 16) & 0x1f;
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rb = (instr >> 11) & 0x1f;
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rc = (instr >> 6) & 0x1f;
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switch (opcode) {
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#ifdef __powerpc64__
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@ -1305,6 +1306,38 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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goto trap;
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return 1;
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#ifdef __powerpc64__
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case 4:
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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return -1;
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switch (instr & 0x3f) {
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case 48: /* maddhd */
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asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
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"=r" (op->val) : "r" (regs->gpr[ra]),
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"r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
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goto compute_done;
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case 49: /* maddhdu */
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asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
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"=r" (op->val) : "r" (regs->gpr[ra]),
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"r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
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goto compute_done;
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case 51: /* maddld */
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asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
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"=r" (op->val) : "r" (regs->gpr[ra]),
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"r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
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goto compute_done;
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}
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/*
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* There are other instructions from ISA 3.0 with the same
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* primary opcode which do not have emulation support yet.
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*/
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return -1;
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#endif
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case 7: /* mulli */
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op->val = regs->gpr[ra] * (short) instr;
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goto compute_done;
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