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mlxsw: reg: Add SMPE related fields to SFMR register

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SFMR register creates and configures FIDs. As preparation unified bridge
model, add some required fields for future use.

The device includes two main tables to support layer 2 multicast (i.e.,
MDB and flooding). These are the PGT (Port Group Table) and the
MPE (Multicast Port Egress) table.
- PGT is {MID -> (bitmap of local_port, SPME index)}
- MPE is {(Local port, SMPE index) -> eVID}

In Spectrum-2 and later ASICs, the SMPE index is an attribute of the FID
and programmed via new fields in SFMR register - 'smpe_valid' and 'smpe'.

Add the two mentioned fields for future use and increase the length of
the register accordingly.

Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Danielle Ratson <danieller@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Amit Cohen 2022-06-19 13:29:14 +03:00 committed by David S. Miller
parent 894b98d50b
commit 92e4e543b1
1 changed files with 20 additions and 1 deletions
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21
drivers/net/ethernet/mellanox/mlxsw/reg.h
View File

@ -1761,7 +1761,7 @@ static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port,
* Creates and configures FIDs.
*/
#define MLXSW_REG_SFMR_ID 0x201F
#define MLXSW_REG_SFMR_LEN 0x18
#define MLXSW_REG_SFMR_LEN 0x30
MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
@ -1858,6 +1858,25 @@ MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1);
*/
MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);
/* reg_sfmr_smpe_valid
* SMPE is valid.
* Access: RW
*
* Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on
* Spectrum-1.
*/
MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1);
/* reg_sfmr_smpe
* Switch multicast port to egress VID.
* Range is 0..cap_max_rmpe-1
* Access: RW
*
* Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on
* Spectrum-1.
*/
MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16);
static inline void mlxsw_reg_sfmr_pack(char *payload,
enum mlxsw_reg_sfmr_op op, u16 fid,
u16 fid_offset)