mirror of
https://github.com/torvalds/linux.git
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drm/msm updates for 6.2
Core: - MSM_INFO_GET_FLAGS support - Cleaned up MSM IOMMU wrapper code DPU: - Added support for XR30 and P010 image formats - Reworked MDSS/DPU schema, added SM8250 MDSS bindings - Added Qualcomm SM6115 support DP: - Dropped unsane sanity checks DSI: - Fix calculation of DSC pps payload DSI PHY: - DSI PHY support for QCM2290 HDMI: - Reworked dev init path -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEETHCElVyyY1bwuJV/izyKPgIpKNUFAmOB580ACgkQizyKPgIp KNWREgf/RKXld9uJhrQnTxpgMEfg/LjVhxzK6Bc6bEdVfuikdGm+3F+7ZrPqrofx GFHgVobjOgvOctdZ1ZmOxpNpaHft3wsFWAnwV2wbAB2ZGdxQk5xIHrZCt0sSgJX6 kH4BkEK7R2rE1PLq/HMfy0GZzsAtaQuxdVlXFdU/ys0sMowjd9D7FI59pSpTrFFe pCQrZGyNsYrZIiYJjfuYddE53TlZXx+P4It4SnnM88WCB6TDKCReOMaIgfCdq9zr /5wDSScl/6bjBcdA6JCtjICHbWkN3Df7RdmZuW9uAJNO+r1kYQbRVfA0hFdrt54G b6MC+0c6xiWx7bngGsIixe6vaiqU3g== =0Uyp -----END PGP SIGNATURE----- Merge tag 'drm-msm-display-for-6.2' of https://gitlab.freedesktop.org/lumag/msm into drm-next drm/msm updates for 6.2 Core: - MSM_INFO_GET_FLAGS support - Cleaned up MSM IOMMU wrapper code DPU: - Added support for XR30 and P010 image formats - Reworked MDSS/DPU schema, added SM8250 MDSS bindings - Added Qualcomm SM6115 support DP: - Dropped unsane sanity checks DSI: - Fix calculation of DSC pps payload DSI PHY: - DSI PHY support for QCM2290 HDMI: - Reworked dev init path Signed-off-by: Dave Airlie <airlied@redhat.com> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20221126102141.721353-1-dmitry.baryshkov@linaro.org
This commit is contained in:
Dave Airlie
commit
92e11ddb2c
@ -0,0 +1,52 @@
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%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dpu-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU common properties
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
- Rob Clark <robdclark@gmail.com>
|
||||
|
||||
description: |
|
||||
Common properties for QCom DPU display controller.
|
||||
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc.
|
||||
|
||||
patternProperties:
|
||||
"^port@[0-9a-f]+$":
|
||||
$ref: /schemas/graph.yaml#/properties/port
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||||
|
||||
# at least one port is required
|
||||
required:
|
||||
- port@0
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||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
additionalProperties: true
|
||||
@ -1,223 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
|
||||
title: Qualcomm Display DPU dt properties for MSM8998 target
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
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||||
|
||||
description: |
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS and DPU are mentioned for MSM8998 target.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,msm8998-mdss
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||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: mdss
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock
|
||||
- description: Display AXI clock
|
||||
- description: Display core clock
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||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
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||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
|
||||
|
||||
ranges: true
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
description: Node containing the properties of DPU.
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,msm8998-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for regdma register set
|
||||
- description: Address offset and size for vbif register set
|
||||
- description: Address offset and size for non-realtime vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: regdma
|
||||
- const: vbif
|
||||
- const: vbif_nrt
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display ahb clock
|
||||
- description: Display axi clock
|
||||
- description: Display mem-noc clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: mnoc
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. Each output port contains an endpoint that
|
||||
describes how it is connected to an external interface.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF1 (DSI1)
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF2 (DSI2)
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
mdss: display-subsystem@c900000 {
|
||||
compatible = "qcom,msm8998-mdss";
|
||||
reg = <0x0c900000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_AXI_CLK>,
|
||||
<&mmcc MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
|
||||
#address-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
iommus = <&mmss_smmu 0>;
|
||||
|
||||
power-domains = <&mmcc MDSS_GDSC>;
|
||||
ranges;
|
||||
|
||||
display-controller@c901000 {
|
||||
compatible = "qcom,msm8998-dpu";
|
||||
reg = <0x0c901000 0x8f000>,
|
||||
<0x0c9a8e00 0xf0>,
|
||||
<0x0c9b0000 0x2008>,
|
||||
<0x0c9b8000 0x1040>;
|
||||
reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_AXI_CLK>,
|
||||
<&mmcc MNOC_AHB_CLK>,
|
||||
<&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "mnoc", "core", "vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmpd MSM8998_VDDMX>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -1,222 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for QCM2290 target
|
||||
|
||||
maintainers:
|
||||
- Loic Poulain <loic.poulain@linaro.org>
|
||||
|
||||
description: |
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
|
||||
and DPU are mentioned for QCM2290 target.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,qcm2290-mdss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: mdss
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AXI clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
|
||||
|
||||
ranges: true
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: Interconnect path specifying the port ids for data bus
|
||||
|
||||
interconnect-names:
|
||||
const: mdp0-mem
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: MDSS_CORE reset
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
description: Node containing the properties of DPU.
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,qcm2290-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AXI clock from gcc
|
||||
- description: Display AHB clock from dispcc
|
||||
- description: Display core clock from dispcc
|
||||
- description: Display lut clock from dispcc
|
||||
- description: Display vsync clock from dispcc
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: iface
|
||||
- const: core
|
||||
- const: lut
|
||||
- const: vsync
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI. Each output port contains an endpoint that
|
||||
describes how it is connected to an external interface.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF1 (DSI1)
|
||||
|
||||
required:
|
||||
- port@0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,qcm2290.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
mdss: mdss@5e00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qcm2290-mdss";
|
||||
reg = <0x05e00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x420 0x2>,
|
||||
<&apps_smmu 0x421 0x0>;
|
||||
ranges;
|
||||
|
||||
mdss_mdp: display-controller@5e01000 {
|
||||
compatible = "qcom,qcm2290-dpu";
|
||||
reg = <0x05e01000 0x8f000>,
|
||||
<0x05eb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus", "iface", "core", "lut", "vsync";
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmpd QCM2290_VDDCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -1,235 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SC7180 target
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
description: |
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS and DPU are mentioned for SC7180 target.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-mdss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: mdss
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AHB clock from dispcc
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ahb
|
||||
- const: core
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
|
||||
|
||||
ranges: true
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: Interconnect path specifying the port ids for data bus
|
||||
|
||||
interconnect-names:
|
||||
const: mdp0-mem
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: MDSS_CORE reset
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
description: Node containing the properties of DPU.
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display hf axi clock
|
||||
- description: Display ahb clock
|
||||
- description: Display rotator clock
|
||||
- description: Display lut clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: iface
|
||||
- const: rot
|
||||
- const: lut
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. Each output port contains an endpoint that
|
||||
describes how it is connected to an external interface.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF1 (DSI1)
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF0 (DP)
|
||||
|
||||
required:
|
||||
- port@0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sdm845.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sc7180-mdss";
|
||||
reg = <0xae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "ahb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x2>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc7180-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ROT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus", "iface", "rot", "lut", "core",
|
||||
"vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dpu_intf0_out: endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -1,239 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SC7280
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
description: |
|
||||
Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS and DPU are mentioned for SC7280.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-mdss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: mdss
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AHB clock from dispcc
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ahb
|
||||
- const: core
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
|
||||
|
||||
ranges: true
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: Interconnect path specifying the port ids for data bus
|
||||
|
||||
interconnect-names:
|
||||
const: mdp0-mem
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: MDSS_CORE reset
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
description: Node containing the properties of DPU.
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display hf axi clock
|
||||
- description: Display sf axi clock
|
||||
- description: Display ahb clock
|
||||
- description: Display lut clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: nrt_bus
|
||||
- const: iface
|
||||
- const: lut
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. Each output port contains an endpoint that
|
||||
describes how it is connected to an external interface.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF1 (DSI)
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF5 (EDP)
|
||||
|
||||
required:
|
||||
- port@0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc7280.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sc7280-mdss";
|
||||
reg = <0xae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface",
|
||||
"ahb",
|
||||
"core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x900 0x402>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc7280-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SC7280_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf5_out: endpoint {
|
||||
remote-endpoint = <&edp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -1,217 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SDM845 target
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
description: |
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS and DPU are mentioned for SDM845 target.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-mdss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: mdss
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: core
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
|
||||
|
||||
ranges: true
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: MDSS_CORE reset
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
description: Node containing the properties of DPU.
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display ahb clock
|
||||
- description: Display axi clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. Each output port contains an endpoint that
|
||||
describes how it is connected to an external interface.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF1 (DSI1)
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF2 (DSI2)
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sdm845-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x880 0x8>,
|
||||
<&apps_smmu 0xc80 0x8>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sdm845-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -49,6 +49,7 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
deprecated: true
|
||||
const: dsi
|
||||
|
||||
"#address-cells": true
|
||||
@ -80,6 +81,9 @@ properties:
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
ports:
|
||||
$ref: "/schemas/graph.yaml#/properties/ports"
|
||||
description: |
|
||||
@ -131,7 +135,6 @@ required:
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- assigned-clocks
|
||||
- assigned-clock-parents
|
||||
- power-domains
|
||||
|
||||
@ -16,6 +16,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,dsi-phy-14nm
|
||||
- qcom,dsi-phy-14nm-2290
|
||||
- qcom,dsi-phy-14nm-660
|
||||
- qcom,dsi-phy-14nm-8953
|
||||
|
||||
|
||||
@ -2,37 +2,9 @@ Qualcomm adreno/snapdragon MDP5 display controller
|
||||
|
||||
Description:
|
||||
|
||||
This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
|
||||
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
|
||||
This is the bindings documentation for the MDP5 display
|
||||
controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
|
||||
|
||||
MDSS:
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdss" - MDSS
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "mdss_phys"
|
||||
* "vbif_phys"
|
||||
- interrupts: The interrupt signal from MDSS.
|
||||
- interrupt-controller: identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- power-domains: a power domain consumer specifier according to
|
||||
Documentation/devicetree/bindings/power/power_domain.txt
|
||||
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
* "iface"
|
||||
* "bus"
|
||||
* "vsync"
|
||||
- #address-cells: number of address cells for the MDSS children. Should be 1.
|
||||
- #size-cells: Should be 1.
|
||||
- ranges: parent bus address space is the same as the child bus address space.
|
||||
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut"
|
||||
|
||||
MDP5:
|
||||
Required properties:
|
||||
- compatible:
|
||||
|
||||
@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/mdss-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display MDSS common properties
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
- Rob Clark <robdclark@gmail.com>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: mdss
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
iommus:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
|
||||
|
||||
ranges: true
|
||||
|
||||
interconnects:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Interconnect path from mdp0 (or a single mdp) port to the data bus
|
||||
- description: Interconnect path from mdp1 port to the data bus
|
||||
|
||||
interconnect-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: mdp0-mem
|
||||
- const: mdp1-mem
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: MDSS_CORE reset
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: true
|
||||
196
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
Normal file
196
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
Normal file
@ -0,0 +1,196 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Mobile Display SubSystem (MDSS)
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
- Rob Clark <robdclark@gmail.com>
|
||||
|
||||
description:
|
||||
This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
|
||||
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,mdss
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: mdss_phys
|
||||
- const: vbif_phys
|
||||
- const: vbif_nrt_phys
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: |
|
||||
The MDSS power domain provided by GCC
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Display abh clock
|
||||
- description: Display axi clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: vsync
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
ranges: true
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: MDSS_CORE reset
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- "#interrupt-cells"
|
||||
- power-domains
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- ranges
|
||||
|
||||
patternProperties:
|
||||
"^mdp@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdp5
|
||||
|
||||
"^dsi@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,dsi-phy-14nm
|
||||
- qcom,dsi-phy-14nm-660
|
||||
- qcom,dsi-phy-14nm-8953
|
||||
- qcom,dsi-phy-20nm
|
||||
- qcom,dsi-phy-28nm-hpm
|
||||
- qcom,dsi-phy-28nm-lp
|
||||
|
||||
"^hdmi-phy@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,hdmi-phy-8084
|
||||
- qcom,hdmi-phy-8660
|
||||
- qcom,hdmi-phy-8960
|
||||
- qcom,hdmi-phy-8974
|
||||
- qcom,hdmi-phy-8996
|
||||
|
||||
"^hdmi-tx@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,hdmi-tx-8084
|
||||
- qcom,hdmi-tx-8660
|
||||
- qcom,hdmi-tx-8960
|
||||
- qcom,hdmi-tx-8974
|
||||
- qcom,hdmi-tx-8994
|
||||
- qcom,hdmi-tx-8996
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
mdss@1a00000 {
|
||||
compatible = "qcom,mdss";
|
||||
reg = <0x1a00000 0x1000>,
|
||||
<0x1ac8000 0x3000>;
|
||||
reg-names = "mdss_phys", "vbif_phys";
|
||||
|
||||
power-domains = <&gcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface",
|
||||
"bus",
|
||||
"vsync";
|
||||
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mdp@1a01000 {
|
||||
compatible = "qcom,mdp5";
|
||||
reg = <0x01a01000 0x89000>;
|
||||
reg-names = "mdp_phys";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_MDP_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface",
|
||||
"bus",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
iommus = <&apps_iommu 4>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdp5_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,95 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for MSM8998 target
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,msm8998-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for regdma register set
|
||||
- description: Address offset and size for vbif register set
|
||||
- description: Address offset and size for non-realtime vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: regdma
|
||||
- const: vbif
|
||||
- const: vbif_nrt
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display ahb clock
|
||||
- description: Display axi clock
|
||||
- description: Display mem-noc clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: mnoc
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@c901000 {
|
||||
compatible = "qcom,msm8998-dpu";
|
||||
reg = <0x0c901000 0x8f000>,
|
||||
<0x0c9a8e00 0xf0>,
|
||||
<0x0c9b0000 0x2008>,
|
||||
<0x0c9b8000 0x1040>;
|
||||
reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_AXI_CLK>,
|
||||
<&mmcc MNOC_AHB_CLK>,
|
||||
<&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "mnoc", "core", "vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmpd MSM8998_VDDMX>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,268 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm MSM8998 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS are mentioned for MSM8998 target.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,msm8998-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock
|
||||
- description: Display AXI clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,msm8998-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-10nm-8998
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@c900000 {
|
||||
compatible = "qcom,msm8998-mdss";
|
||||
reg = <0x0c900000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_AXI_CLK>,
|
||||
<&mmcc MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
|
||||
#address-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
iommus = <&mmss_smmu 0>;
|
||||
|
||||
power-domains = <&mmcc MDSS_GDSC>;
|
||||
ranges;
|
||||
|
||||
display-controller@c901000 {
|
||||
compatible = "qcom,msm8998-dpu";
|
||||
reg = <0x0c901000 0x8f000>,
|
||||
<0x0c9a8e00 0xf0>,
|
||||
<0x0c9b0000 0x2008>,
|
||||
<0x0c9b8000 0x1040>;
|
||||
reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_AXI_CLK>,
|
||||
<&mmcc MNOC_AHB_CLK>,
|
||||
<&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "mnoc", "core", "vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmpd MSM8998_VDDMX>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@c994000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0c994000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&mmcc MDSS_BYTE0_CLK>,
|
||||
<&mmcc MDSS_BYTE0_INTF_CLK>,
|
||||
<&mmcc MDSS_PCLK0_CLK>,
|
||||
<&mmcc MDSS_ESC0_CLK>,
|
||||
<&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmpd MSM8998_VDDCX>;
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@c994400 {
|
||||
compatible = "qcom,dsi-phy-10nm-8998";
|
||||
reg = <0x0c994400 0x200>,
|
||||
<0x0c994600 0x280>,
|
||||
<0x0c994a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>,
|
||||
<&rpmcc RPM_SMD_XO_CLK_SRC>;
|
||||
clock-names = "iface", "ref";
|
||||
|
||||
vdds-supply = <&pm8998_l1>;
|
||||
};
|
||||
|
||||
dsi@c996000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0c996000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <5>;
|
||||
|
||||
clocks = <&mmcc MDSS_BYTE1_CLK>,
|
||||
<&mmcc MDSS_BYTE1_INTF_CLK>,
|
||||
<&mmcc MDSS_PCLK1_CLK>,
|
||||
<&mmcc MDSS_ESC1_CLK>,
|
||||
<&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmpd MSM8998_VDDCX>;
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: phy@c996400 {
|
||||
compatible = "qcom,dsi-phy-10nm-8998";
|
||||
reg = <0x0c996400 0x200>,
|
||||
<0x0c996600 0x280>,
|
||||
<0x0c996a00 0x10e>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>,
|
||||
<&rpmcc RPM_SMD_XO_CLK_SRC>;
|
||||
clock-names = "iface", "ref";
|
||||
|
||||
vdds-supply = <&pm8998_l1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for QCM2290 target
|
||||
|
||||
maintainers:
|
||||
- Loic Poulain <loic.poulain@linaro.org>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,qcm2290-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AXI clock from gcc
|
||||
- description: Display AHB clock from dispcc
|
||||
- description: Display core clock from dispcc
|
||||
- description: Display lut clock from dispcc
|
||||
- description: Display vsync clock from dispcc
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: iface
|
||||
- const: core
|
||||
- const: lut
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@5e01000 {
|
||||
compatible = "qcom,qcm2290-dpu";
|
||||
reg = <0x05e01000 0x8f000>,
|
||||
<0x05eb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus", "iface", "core", "lut", "vsync";
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmpd QCM2290_VDDCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,198 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm QCM220 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Loic Poulain <loic.poulain@linaro.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
|
||||
are mentioned for QCM2290 target.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,qcm2290-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AXI clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 2
|
||||
|
||||
interconnects:
|
||||
maxItems: 1
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,qcm2290-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-ctrl-6g-qcm2290
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-14nm-2290
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,qcm2290.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
mdss@5e00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,qcm2290-mdss";
|
||||
reg = <0x05e00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x420 0x2>,
|
||||
<&apps_smmu 0x421 0x0>;
|
||||
ranges;
|
||||
|
||||
display-controller@5e01000 {
|
||||
compatible = "qcom,qcm2290-dpu";
|
||||
reg = <0x05e01000 0x8f000>,
|
||||
<0x05eb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus", "iface", "core", "lut", "vsync";
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmpd QCM2290_VDDCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@5e94000 {
|
||||
compatible = "qcom,dsi-ctrl-6g-qcm2290";
|
||||
reg = <0x05e94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmpd QCM2290_VDDCX>;
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@5e94400 {
|
||||
compatible = "qcom,dsi-phy-14nm-2290";
|
||||
reg = <0x05e94400 0x100>,
|
||||
<0x05e94500 0x300>,
|
||||
<0x05e94800 0x188>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
||||
clock-names = "iface", "ref";
|
||||
vcca-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,95 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SC7180 target
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display hf axi clock
|
||||
- description: Display ahb clock
|
||||
- description: Display rotator clock
|
||||
- description: Display lut clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: iface
|
||||
- const: rot
|
||||
- const: lut
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc7180-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ROT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus", "iface", "rot", "lut", "core",
|
||||
"vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,304 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SC7180 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS are mentioned for SC7180 target.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AHB clock from dispcc
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ahb
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
maxItems: 1
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-dp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-10nm
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sdm845.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sc7180-mdss";
|
||||
reg = <0xae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "ahb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x2>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc7180-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ROT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus", "iface", "rot", "lut", "core",
|
||||
"vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dpu_intf0_out: endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
|
||||
phys = <&dsi_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-187500000 {
|
||||
opp-hz = /bits/ 64 <187500000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-358000000 {
|
||||
opp-hz = /bits/ 64 <358000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_phy: phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-10nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
|
||||
displayport-controller@ae90000 {
|
||||
compatible = "qcom,sc7180-dp";
|
||||
|
||||
reg = <0xae90000 0x200>,
|
||||
<0xae90200 0x200>,
|
||||
<0xae90400 0xc00>,
|
||||
<0xae91000 0x400>,
|
||||
<0xae91400 0x400>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <12>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
|
||||
clock-names = "core_iface", "core_aux", "ctrl_link",
|
||||
"ctrl_link_iface", "stream_pixel";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
|
||||
assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
|
||||
operating-points-v2 = <&dp_opp_table>;
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dp_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dp_out: endpoint { };
|
||||
};
|
||||
};
|
||||
|
||||
dp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-270000000 {
|
||||
opp-hz = /bits/ 64 <270000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-540000000 {
|
||||
opp-hz = /bits/ 64 <540000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-810000000 {
|
||||
opp-hz = /bits/ 64 <810000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,98 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SC7280
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display hf axi clock
|
||||
- description: Display sf axi clock
|
||||
- description: Display ahb clock
|
||||
- description: Display lut clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: nrt_bus
|
||||
- const: iface
|
||||
- const: lut
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc7280-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SC7280_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&edp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,422 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SC7280 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS are mentioned for SC7280.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AHB clock from dispcc
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ahb
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
maxItems: 1
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-dp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^edp@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-edp
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7280-dsi-phy-7nm
|
||||
- qcom,sc7280-edp-phy
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc7280.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sc7280-mdss";
|
||||
reg = <0xae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface",
|
||||
"ahb",
|
||||
"core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x900 0x402>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc7280-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SC7280_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf5_out: endpoint {
|
||||
remote-endpoint = <&edp_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dpu_intf0_out: endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SC7280_CX>;
|
||||
|
||||
phys = <&mdss_dsi_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-187500000 {
|
||||
opp-hz = /bits/ 64 <187500000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-358000000 {
|
||||
opp-hz = /bits/ 64 <358000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy: phy@ae94400 {
|
||||
compatible = "qcom,sc7280-dsi-phy-7nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94900 0x280>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
|
||||
vdds-supply = <&vreg_dsi_supply>;
|
||||
};
|
||||
|
||||
edp@aea0000 {
|
||||
compatible = "qcom,sc7280-edp";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&edp_hot_plug_det>;
|
||||
|
||||
reg = <0xaea0000 0x200>,
|
||||
<0xaea0200 0x200>,
|
||||
<0xaea0400 0xc00>,
|
||||
<0xaea1000 0x400>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <14>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
|
||||
|
||||
phys = <&mdss_edp_phy>;
|
||||
phy-names = "dp";
|
||||
|
||||
operating-points-v2 = <&edp_opp_table>;
|
||||
power-domains = <&rpmhpd SC7280_CX>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
edp_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf5_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdss_edp_out: endpoint { };
|
||||
};
|
||||
};
|
||||
|
||||
edp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-270000000 {
|
||||
opp-hz = /bits/ 64 <270000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-540000000 {
|
||||
opp-hz = /bits/ 64 <540000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
|
||||
opp-810000000 {
|
||||
opp-hz = /bits/ 64 <810000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_edp_phy: phy@aec2a00 {
|
||||
compatible = "qcom,sc7280-edp-phy";
|
||||
|
||||
reg = <0xaec2a00 0x19c>,
|
||||
<0xaec2200 0xa0>,
|
||||
<0xaec2600 0xa0>,
|
||||
<0xaec2000 0x1c0>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_EDP_CLKREF_EN>;
|
||||
clock-names = "aux",
|
||||
"cfg_ahb";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
displayport-controller@ae90000 {
|
||||
compatible = "qcom,sc7280-dp";
|
||||
|
||||
reg = <0xae90000 0x200>,
|
||||
<0xae90200 0x200>,
|
||||
<0xae90400 0xc00>,
|
||||
<0xae91000 0x400>,
|
||||
<0xae91400 0x400>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <12>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
|
||||
assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
|
||||
operating-points-v2 = <&dp_opp_table>;
|
||||
power-domains = <&rpmhpd SC7280_CX>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dp_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dp_out: endpoint { };
|
||||
};
|
||||
};
|
||||
|
||||
dp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-270000000 {
|
||||
opp-hz = /bits/ 64 <270000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-540000000 {
|
||||
opp-hz = /bits/ 64 <540000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-810000000 {
|
||||
opp-hz = /bits/ 64 <810000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,90 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SDM845 target
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display GCC bus clock
|
||||
- description: Display ahb clock
|
||||
- description: Display axi clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: gcc-bus
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sdm845-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,270 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SDM845 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS are mentioned for SDM845 target.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 2
|
||||
|
||||
interconnects:
|
||||
maxItems: 2
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 2
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-10nm
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sdm845-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x880 0x8>,
|
||||
<&apps_smmu 0xc80 0x8>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sdm845-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-10nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
|
||||
dsi@ae96000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae96000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <5>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: phy@ae96400 {
|
||||
compatible = "qcom,dsi-phy-10nm";
|
||||
reg = <0x0ae96400 0x200>,
|
||||
<0x0ae96600 0x280>,
|
||||
<0x0ae96a00 0x10e>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,94 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SM6115 target
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm6115-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: MDP register set
|
||||
- description: VBIF register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AXI
|
||||
- description: Display AHB
|
||||
- description: Display core
|
||||
- description: Display lut
|
||||
- description: Display rotator
|
||||
- description: Display vsync
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: iface
|
||||
- const: core
|
||||
- const: lut
|
||||
- const: rot
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@5e01000 {
|
||||
compatible = "qcom,sm6115-dpu";
|
||||
reg = <0x05e01000 0x8f000>,
|
||||
<0x05eb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ROT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmpd SM6115_VDDCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,182 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM6115 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
|
||||
are mentioned for SM6115 target.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm6115-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AXI clock
|
||||
- description: Display core clock
|
||||
|
||||
iommus:
|
||||
maxItems: 2
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6115-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-ctrl-6g-qcm2290
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-14nm-2290
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
mdss@5e00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sm6115-mdss";
|
||||
reg = <0x05e00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x420 0x2>,
|
||||
<&apps_smmu 0x421 0x0>;
|
||||
ranges;
|
||||
|
||||
display-controller@5e01000 {
|
||||
compatible = "qcom,sm6115-dpu";
|
||||
reg = <0x05e01000 0x8f000>,
|
||||
<0x05eb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ROT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmpd SM6115_VDDCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@5e94000 {
|
||||
compatible = "qcom,dsi-ctrl-6g-qcm2290";
|
||||
reg = <0x05e94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmpd SM6115_VDDCX>;
|
||||
phys = <&dsi0_phy>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@5e94400 {
|
||||
compatible = "qcom,dsi-phy-14nm-2290";
|
||||
reg = <0x05e94400 0x100>,
|
||||
<0x05e94500 0x300>,
|
||||
<0x05e94800 0x188>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,92 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8250 Display DPU
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8250-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display ahb clock
|
||||
- description: Display hf axi clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8250.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm8250-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SM8250_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,330 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8250 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS are mentioned for SM8250 target.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8250-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display hf axi clock
|
||||
- description: Display sf axi clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: nrt_bus
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
maxItems: 2
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 2
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8250-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-7nm
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8250.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
compatible = "qcom,sm8250-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "nrt_bus", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x820 0x402>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm8250-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SM8250_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-345000000 {
|
||||
opp-hz = /bits/ 64 <345000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-460000000 {
|
||||
opp-hz = /bits/ 64 <460000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SM8250_MMCX>;
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-187500000 {
|
||||
opp-hz = /bits/ 64 <187500000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-358000000 {
|
||||
opp-hz = /bits/ 64 <358000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94900 0x260>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
|
||||
dsi@ae96000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae96000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <5>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SM8250_MMCX>;
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: phy@ae96400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0x0ae96400 0x200>,
|
||||
<0x0ae96600 0x280>,
|
||||
<0x0ae96900 0x260>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -500,7 +500,7 @@ static const struct adreno_gpu_funcs funcs = {
|
||||
#endif
|
||||
.gpu_state_get = a3xx_gpu_state_get,
|
||||
.gpu_state_put = adreno_gpu_state_put,
|
||||
.create_address_space = adreno_iommu_create_address_space,
|
||||
.create_address_space = adreno_create_address_space,
|
||||
.get_rptr = a3xx_get_rptr,
|
||||
},
|
||||
};
|
||||
|
||||
@ -635,7 +635,7 @@ static const struct adreno_gpu_funcs funcs = {
|
||||
#endif
|
||||
.gpu_state_get = a4xx_gpu_state_get,
|
||||
.gpu_state_put = adreno_gpu_state_put,
|
||||
.create_address_space = adreno_iommu_create_address_space,
|
||||
.create_address_space = adreno_create_address_space,
|
||||
.get_rptr = a4xx_get_rptr,
|
||||
},
|
||||
.get_timestamp = a4xx_get_timestamp,
|
||||
|
||||
@ -1705,7 +1705,7 @@ static const struct adreno_gpu_funcs funcs = {
|
||||
.gpu_busy = a5xx_gpu_busy,
|
||||
.gpu_state_get = a5xx_gpu_state_get,
|
||||
.gpu_state_put = a5xx_gpu_state_put,
|
||||
.create_address_space = adreno_iommu_create_address_space,
|
||||
.create_address_space = adreno_create_address_space,
|
||||
.get_rptr = a5xx_get_rptr,
|
||||
},
|
||||
.get_timestamp = a5xx_get_timestamp,
|
||||
|
||||
@ -1213,19 +1213,17 @@ static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
|
||||
|
||||
static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
|
||||
{
|
||||
struct iommu_domain *domain;
|
||||
struct msm_mmu *mmu;
|
||||
|
||||
domain = iommu_domain_alloc(&platform_bus_type);
|
||||
if (!domain)
|
||||
mmu = msm_iommu_new(gmu->dev, 0);
|
||||
if (!mmu)
|
||||
return -ENODEV;
|
||||
if (IS_ERR(mmu))
|
||||
return PTR_ERR(mmu);
|
||||
|
||||
mmu = msm_iommu_new(gmu->dev, domain);
|
||||
gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
|
||||
if (IS_ERR(gmu->aspace)) {
|
||||
iommu_domain_free(domain);
|
||||
if (IS_ERR(gmu->aspace))
|
||||
return PTR_ERR(gmu->aspace);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1786,43 +1786,16 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
struct iommu_domain *iommu;
|
||||
struct msm_mmu *mmu;
|
||||
struct msm_gem_address_space *aspace;
|
||||
u64 start, size;
|
||||
|
||||
iommu = iommu_domain_alloc(&platform_bus_type);
|
||||
if (!iommu)
|
||||
return NULL;
|
||||
unsigned long quirks = 0;
|
||||
|
||||
/*
|
||||
* This allows GPU to set the bus attributes required to use system
|
||||
* cache on behalf of the iommu page table walker.
|
||||
*/
|
||||
if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
|
||||
adreno_set_llc_attributes(iommu);
|
||||
quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
|
||||
|
||||
mmu = msm_iommu_new(&pdev->dev, iommu);
|
||||
if (IS_ERR(mmu)) {
|
||||
iommu_domain_free(iommu);
|
||||
return ERR_CAST(mmu);
|
||||
}
|
||||
|
||||
/*
|
||||
* Use the aperture start or SZ_16M, whichever is greater. This will
|
||||
* ensure that we align with the allocated pagetable range while still
|
||||
* allowing room in the lower 32 bits for GMEM and whatnot
|
||||
*/
|
||||
start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
|
||||
size = iommu->geometry.aperture_end - start + 1;
|
||||
|
||||
aspace = msm_gem_address_space_create(mmu, "gpu",
|
||||
start & GENMASK_ULL(48, 0), size);
|
||||
|
||||
if (IS_ERR(aspace) && !IS_ERR(mmu))
|
||||
mmu->funcs->destroy(mmu);
|
||||
|
||||
return aspace;
|
||||
return adreno_iommu_create_address_space(gpu, pdev, quirks);
|
||||
}
|
||||
|
||||
static struct msm_gem_address_space *
|
||||
|
||||
@ -191,37 +191,38 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
|
||||
return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
|
||||
}
|
||||
|
||||
void adreno_set_llc_attributes(struct iommu_domain *iommu)
|
||||
struct msm_gem_address_space *
|
||||
adreno_create_address_space(struct msm_gpu *gpu,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
iommu_set_pgtable_quirks(iommu, IO_PGTABLE_QUIRK_ARM_OUTER_WBWA);
|
||||
return adreno_iommu_create_address_space(gpu, pdev, 0);
|
||||
}
|
||||
|
||||
struct msm_gem_address_space *
|
||||
adreno_iommu_create_address_space(struct msm_gpu *gpu,
|
||||
struct platform_device *pdev)
|
||||
struct platform_device *pdev,
|
||||
unsigned long quirks)
|
||||
{
|
||||
struct iommu_domain *iommu;
|
||||
struct iommu_domain_geometry *geometry;
|
||||
struct msm_mmu *mmu;
|
||||
struct msm_gem_address_space *aspace;
|
||||
u64 start, size;
|
||||
|
||||
iommu = iommu_domain_alloc(&platform_bus_type);
|
||||
if (!iommu)
|
||||
return NULL;
|
||||
|
||||
mmu = msm_iommu_new(&pdev->dev, iommu);
|
||||
if (IS_ERR(mmu)) {
|
||||
iommu_domain_free(iommu);
|
||||
mmu = msm_iommu_new(&pdev->dev, quirks);
|
||||
if (IS_ERR_OR_NULL(mmu))
|
||||
return ERR_CAST(mmu);
|
||||
}
|
||||
|
||||
geometry = msm_iommu_get_geometry(mmu);
|
||||
if (IS_ERR(geometry))
|
||||
return ERR_CAST(geometry);
|
||||
|
||||
/*
|
||||
* Use the aperture start or SZ_16M, whichever is greater. This will
|
||||
* ensure that we align with the allocated pagetable range while still
|
||||
* allowing room in the lower 32 bits for GMEM and whatnot
|
||||
*/
|
||||
start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
|
||||
size = iommu->geometry.aperture_end - start + 1;
|
||||
start = max_t(u64, SZ_16M, geometry->aperture_start);
|
||||
size = geometry->aperture_end - start + 1;
|
||||
|
||||
aspace = msm_gem_address_space_create(mmu, "gpu",
|
||||
start & GENMASK_ULL(48, 0), size);
|
||||
|
||||
@ -335,10 +335,13 @@ void adreno_show_object(struct drm_printer *p, void **ptr, int len,
|
||||
* attached targets
|
||||
*/
|
||||
struct msm_gem_address_space *
|
||||
adreno_iommu_create_address_space(struct msm_gpu *gpu,
|
||||
struct platform_device *pdev);
|
||||
adreno_create_address_space(struct msm_gpu *gpu,
|
||||
struct platform_device *pdev);
|
||||
|
||||
void adreno_set_llc_attributes(struct iommu_domain *iommu);
|
||||
struct msm_gem_address_space *
|
||||
adreno_iommu_create_address_space(struct msm_gpu *gpu,
|
||||
struct platform_device *pdev,
|
||||
unsigned long quirks);
|
||||
|
||||
int adreno_read_speedbin(struct device *dev, u32 *speedbin);
|
||||
|
||||
|
||||
@ -434,6 +434,12 @@ static const struct dpu_format dpu_format_map[] = {
|
||||
DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
|
||||
DPU_FETCH_LINEAR, 2),
|
||||
|
||||
PSEUDO_YUV_FMT_LOOSE(P010,
|
||||
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
|
||||
C1_B_Cb, C2_R_Cr,
|
||||
DPU_CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
|
||||
DPU_FETCH_LINEAR, 2),
|
||||
|
||||
INTERLEAVED_YUV_FMT(VYUY,
|
||||
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
|
||||
C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
|
||||
@ -524,12 +530,26 @@ static const struct dpu_format dpu_format_map_ubwc[] = {
|
||||
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
|
||||
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
|
||||
|
||||
INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
|
||||
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
|
||||
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
|
||||
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
|
||||
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
|
||||
|
||||
PSEUDO_YUV_FMT_TILED(NV12,
|
||||
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
|
||||
C1_B_Cb, C2_R_Cr,
|
||||
DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV |
|
||||
DPU_FORMAT_FLAG_COMPRESSED,
|
||||
DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
|
||||
|
||||
PSEUDO_YUV_FMT_TILED(P010,
|
||||
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
|
||||
C1_B_Cb, C2_R_Cr,
|
||||
DPU_CHROMA_420, DPU_FORMAT_FLAG_DX |
|
||||
DPU_FORMAT_FLAG_YUV |
|
||||
DPU_FORMAT_FLAG_COMPRESSED,
|
||||
DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
|
||||
};
|
||||
|
||||
/* _dpu_get_v_h_subsample_rate - Get subsample rates for all formats we support
|
||||
@ -571,13 +591,15 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
|
||||
{DRM_FORMAT_XBGR8888, COLOR_FMT_RGBA8888_UBWC},
|
||||
{DRM_FORMAT_XRGB8888, COLOR_FMT_RGBA8888_UBWC},
|
||||
{DRM_FORMAT_ABGR2101010, COLOR_FMT_RGBA1010102_UBWC},
|
||||
{DRM_FORMAT_XRGB2101010, COLOR_FMT_RGBA1010102_UBWC},
|
||||
{DRM_FORMAT_XBGR2101010, COLOR_FMT_RGBA1010102_UBWC},
|
||||
{DRM_FORMAT_BGR565, COLOR_FMT_RGB565_UBWC},
|
||||
};
|
||||
int color_fmt = -1;
|
||||
int i;
|
||||
|
||||
if (fmt->base.pixel_format == DRM_FORMAT_NV12) {
|
||||
if (fmt->base.pixel_format == DRM_FORMAT_NV12 ||
|
||||
fmt->base.pixel_format == DRM_FORMAT_P010) {
|
||||
if (DPU_FORMAT_IS_DX(fmt)) {
|
||||
if (fmt->unpack_tight)
|
||||
color_fmt = COLOR_FMT_NV12_BPP10_UBWC;
|
||||
|
||||
@ -156,6 +156,7 @@ static const uint32_t plane_formats[] = {
|
||||
DRM_FORMAT_RGBX8888,
|
||||
DRM_FORMAT_BGRX8888,
|
||||
DRM_FORMAT_XBGR8888,
|
||||
DRM_FORMAT_XRGB2101010,
|
||||
DRM_FORMAT_RGB888,
|
||||
DRM_FORMAT_BGR888,
|
||||
DRM_FORMAT_RGB565,
|
||||
@ -184,6 +185,7 @@ static const uint32_t plane_formats_yuv[] = {
|
||||
DRM_FORMAT_RGBA8888,
|
||||
DRM_FORMAT_BGRX8888,
|
||||
DRM_FORMAT_BGRA8888,
|
||||
DRM_FORMAT_XRGB2101010,
|
||||
DRM_FORMAT_XRGB8888,
|
||||
DRM_FORMAT_XBGR8888,
|
||||
DRM_FORMAT_RGBX8888,
|
||||
@ -208,6 +210,7 @@ static const uint32_t plane_formats_yuv[] = {
|
||||
DRM_FORMAT_RGBX4444,
|
||||
DRM_FORMAT_BGRX4444,
|
||||
|
||||
DRM_FORMAT_P010,
|
||||
DRM_FORMAT_NV12,
|
||||
DRM_FORMAT_NV21,
|
||||
DRM_FORMAT_NV16,
|
||||
@ -318,6 +321,18 @@ static const struct dpu_caps sc7180_dpu_caps = {
|
||||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_caps sm6115_dpu_caps = {
|
||||
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
|
||||
.max_mixer_blendstages = 0x4,
|
||||
.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
|
||||
.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
|
||||
.ubwc_version = DPU_HW_UBWC_VER_20,
|
||||
.has_dim_layer = true,
|
||||
.has_idle_pc = true,
|
||||
.max_linewidth = 2160,
|
||||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_caps sm8150_dpu_caps = {
|
||||
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
|
||||
.max_mixer_blendstages = 0xb,
|
||||
@ -472,6 +487,19 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = {
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sm6115_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
.base = 0x0, .len = 0x494,
|
||||
.features = 0,
|
||||
.highest_bank_bit = 0x1,
|
||||
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
|
||||
.reg_off = 0x2ac, .bit_off = 0},
|
||||
.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
|
||||
.reg_off = 0x2ac, .bit_off = 8},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg sm8250_mdp[] = {
|
||||
{
|
||||
.name = "top_0", .id = MDP_TOP,
|
||||
@ -849,6 +877,16 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
|
||||
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
|
||||
_VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED3LITE);
|
||||
|
||||
static const struct dpu_sspp_cfg sm6115_sspp[] = {
|
||||
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
|
||||
sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
|
||||
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
|
||||
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
|
||||
_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
|
||||
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
|
||||
@ -1175,6 +1213,13 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
|
||||
-1),
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sc7280_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
|
||||
PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
|
||||
PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
|
||||
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
|
||||
};
|
||||
|
||||
static struct dpu_pingpong_cfg qcm2290_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
|
||||
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
@ -1198,13 +1243,6 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
|
||||
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg sc7280_pp[] = {
|
||||
PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
|
||||
PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
|
||||
PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
|
||||
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
|
||||
};
|
||||
|
||||
/*************************************************************
|
||||
* DSC sub blocks config
|
||||
*************************************************************/
|
||||
@ -1587,6 +1625,35 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
|
||||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm6115_perf_data = {
|
||||
.max_bw_low = 3100000,
|
||||
.max_bw_high = 4000000,
|
||||
.min_core_ib = 2400000,
|
||||
.min_llcc_ib = 800000,
|
||||
.min_dram_ib = 800000,
|
||||
.min_prefill_lines = 24,
|
||||
.danger_lut_tbl = {0xff, 0xffff, 0x0},
|
||||
.safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
|
||||
.qos_lut_tbl = {
|
||||
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
|
||||
.entries = sc7180_qos_linear
|
||||
},
|
||||
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
|
||||
.entries = sc7180_qos_macrotile
|
||||
},
|
||||
{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
|
||||
.entries = sc7180_qos_nrt
|
||||
},
|
||||
/* TODO: macrotile-qseed is different from macrotile */
|
||||
},
|
||||
.cdp_cfg = {
|
||||
{.rd_enable = 1, .wr_enable = 1},
|
||||
{.rd_enable = 1, .wr_enable = 0}
|
||||
},
|
||||
.clk_inefficiency_factor = 105,
|
||||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm8150_perf_data = {
|
||||
.max_bw_low = 12800000,
|
||||
.max_bw_high = 12800000,
|
||||
@ -1798,6 +1865,28 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
|
||||
.mdss_irqs = IRQ_SC7180_MASK,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
|
||||
.caps = &sm6115_dpu_caps,
|
||||
.mdp_count = ARRAY_SIZE(sm6115_mdp),
|
||||
.mdp = sm6115_mdp,
|
||||
.ctl_count = ARRAY_SIZE(qcm2290_ctl),
|
||||
.ctl = qcm2290_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sm6115_sspp),
|
||||
.sspp = sm6115_sspp,
|
||||
.mixer_count = ARRAY_SIZE(qcm2290_lm),
|
||||
.mixer = qcm2290_lm,
|
||||
.dspp_count = ARRAY_SIZE(qcm2290_dspp),
|
||||
.dspp = qcm2290_dspp,
|
||||
.pingpong_count = ARRAY_SIZE(qcm2290_pp),
|
||||
.pingpong = qcm2290_pp,
|
||||
.intf_count = ARRAY_SIZE(qcm2290_intf),
|
||||
.intf = qcm2290_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sm6115_perf_data,
|
||||
.mdss_irqs = IRQ_SC7180_MASK,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
|
||||
.caps = &sm8150_dpu_caps,
|
||||
.mdp_count = ARRAY_SIZE(sdm845_mdp),
|
||||
@ -1932,6 +2021,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
|
||||
{ .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg},
|
||||
{ .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
|
||||
{ .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
|
||||
{ .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
|
||||
{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
|
||||
{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
|
||||
};
|
||||
|
||||
@ -44,6 +44,7 @@
|
||||
#define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */
|
||||
#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
|
||||
#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
|
||||
#define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */
|
||||
#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
|
||||
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
|
||||
|
||||
|
||||
@ -42,7 +42,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
|
||||
u32 initial_lines)
|
||||
{
|
||||
struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
|
||||
u32 data, lsb, bpp;
|
||||
u32 data;
|
||||
u32 slice_last_group_size;
|
||||
u32 det_thresh_flatness;
|
||||
bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
|
||||
@ -56,14 +56,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
|
||||
data = (initial_lines << 20);
|
||||
data |= ((slice_last_group_size - 1) << 18);
|
||||
/* bpp is 6.4 format, 4 LSBs bits are for fractional part */
|
||||
data |= dsc->bits_per_pixel << 12;
|
||||
lsb = dsc->bits_per_pixel % 4;
|
||||
bpp = dsc->bits_per_pixel / 4;
|
||||
bpp *= 4;
|
||||
bpp <<= 4;
|
||||
bpp |= lsb;
|
||||
|
||||
data |= bpp << 8;
|
||||
data |= (dsc->bits_per_pixel << 8);
|
||||
data |= (dsc->block_pred_enable << 7);
|
||||
data |= (dsc->line_buf_depth << 3);
|
||||
data |= (dsc->simple_422 << 2);
|
||||
|
||||
@ -194,7 +194,7 @@ struct dpu_debugfs_regset32 {
|
||||
struct dpu_kms *dpu_kms;
|
||||
};
|
||||
|
||||
static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
|
||||
static int dpu_regset32_show(struct seq_file *s, void *data)
|
||||
{
|
||||
struct dpu_debugfs_regset32 *regset = s->private;
|
||||
struct dpu_kms *dpu_kms = regset->dpu_kms;
|
||||
@ -227,19 +227,7 @@ static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dpu_debugfs_open_regset32(struct inode *inode,
|
||||
struct file *file)
|
||||
{
|
||||
return single_open(file, _dpu_debugfs_show_regset32, inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations dpu_fops_regset32 = {
|
||||
.open = dpu_debugfs_open_regset32,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
DEFINE_SHOW_ATTRIBUTE(dpu_regset32);
|
||||
|
||||
void dpu_debugfs_create_regset32(const char *name, umode_t mode,
|
||||
void *parent,
|
||||
@ -259,7 +247,7 @@ void dpu_debugfs_create_regset32(const char *name, umode_t mode,
|
||||
regset->blk_len = length;
|
||||
regset->dpu_kms = dpu_kms;
|
||||
|
||||
debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32);
|
||||
debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops);
|
||||
}
|
||||
|
||||
static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
|
||||
@ -1304,6 +1292,7 @@ static const struct of_device_id dpu_dt_match[] = {
|
||||
{ .compatible = "qcom,sc7180-dpu", },
|
||||
{ .compatible = "qcom,sc7280-dpu", },
|
||||
{ .compatible = "qcom,sc8180x-dpu", },
|
||||
{ .compatible = "qcom,sm6115-dpu", },
|
||||
{ .compatible = "qcom,sm8150-dpu", },
|
||||
{ .compatible = "qcom,sm8250-dpu", },
|
||||
{}
|
||||
|
||||
@ -69,9 +69,11 @@ static const uint32_t qcom_compressed_supported_formats[] = {
|
||||
DRM_FORMAT_ARGB8888,
|
||||
DRM_FORMAT_XBGR8888,
|
||||
DRM_FORMAT_XRGB8888,
|
||||
DRM_FORMAT_XRGB2101010,
|
||||
DRM_FORMAT_BGR565,
|
||||
|
||||
DRM_FORMAT_NV12,
|
||||
DRM_FORMAT_P010,
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@ -387,7 +387,7 @@ static int mdp4_kms_init(struct drm_device *dev)
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct mdp4_kms *mdp4_kms;
|
||||
struct msm_kms *kms = NULL;
|
||||
struct iommu_domain *iommu;
|
||||
struct msm_mmu *mmu;
|
||||
struct msm_gem_address_space *aspace;
|
||||
int irq, ret;
|
||||
u32 major, minor;
|
||||
@ -499,10 +499,15 @@ static int mdp4_kms_init(struct drm_device *dev)
|
||||
mdp4_disable(mdp4_kms);
|
||||
mdelay(16);
|
||||
|
||||
iommu = iommu_domain_alloc(pdev->dev.bus);
|
||||
if (iommu) {
|
||||
struct msm_mmu *mmu = msm_iommu_new(&pdev->dev, iommu);
|
||||
|
||||
mmu = msm_iommu_new(&pdev->dev, 0);
|
||||
if (IS_ERR(mmu)) {
|
||||
ret = PTR_ERR(mmu);
|
||||
goto fail;
|
||||
} else if (!mmu) {
|
||||
DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
|
||||
"contig buffers for scanout\n");
|
||||
aspace = NULL;
|
||||
} else {
|
||||
aspace = msm_gem_address_space_create(mmu,
|
||||
"mdp4", 0x1000, 0x100000000 - 0x1000);
|
||||
|
||||
@ -514,10 +519,6 @@ static int mdp4_kms_init(struct drm_device *dev)
|
||||
}
|
||||
|
||||
kms->aspace = aspace;
|
||||
} else {
|
||||
DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
|
||||
"contig buffers for scanout\n");
|
||||
aspace = NULL;
|
||||
}
|
||||
|
||||
ret = modeset_init(mdp4_kms);
|
||||
|
||||
@ -203,7 +203,7 @@ static int mdp5_set_split_display(struct msm_kms *kms,
|
||||
slave_encoder);
|
||||
}
|
||||
|
||||
static void mdp5_destroy(struct platform_device *pdev);
|
||||
static void mdp5_destroy(struct mdp5_kms *mdp5_kms);
|
||||
|
||||
static void mdp5_kms_destroy(struct msm_kms *kms)
|
||||
{
|
||||
@ -223,7 +223,7 @@ static void mdp5_kms_destroy(struct msm_kms *kms)
|
||||
}
|
||||
|
||||
mdp_kms_destroy(&mdp5_kms->base);
|
||||
mdp5_destroy(mdp5_kms->pdev);
|
||||
mdp5_destroy(mdp5_kms);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
@ -559,6 +559,8 @@ static int mdp5_kms_init(struct drm_device *dev)
|
||||
int irq, i, ret;
|
||||
|
||||
ret = mdp5_init(to_platform_device(dev->dev), dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* priv->kms would have been populated by the MDP5 driver */
|
||||
kms = priv->kms;
|
||||
@ -632,9 +634,8 @@ fail:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mdp5_destroy(struct platform_device *pdev)
|
||||
static void mdp5_destroy(struct mdp5_kms *mdp5_kms)
|
||||
{
|
||||
struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
|
||||
int i;
|
||||
|
||||
if (mdp5_kms->ctlm)
|
||||
@ -648,7 +649,7 @@ static void mdp5_destroy(struct platform_device *pdev)
|
||||
kfree(mdp5_kms->intfs[i]);
|
||||
|
||||
if (mdp5_kms->rpm_enabled)
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
pm_runtime_disable(&mdp5_kms->pdev->dev);
|
||||
|
||||
drm_atomic_private_obj_fini(&mdp5_kms->glob_state);
|
||||
drm_modeset_lock_fini(&mdp5_kms->glob_state_lock);
|
||||
@ -797,8 +798,6 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
|
||||
goto fail;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, mdp5_kms);
|
||||
|
||||
spin_lock_init(&mdp5_kms->resource_lock);
|
||||
|
||||
mdp5_kms->dev = dev;
|
||||
@ -839,6 +838,9 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
|
||||
*/
|
||||
clk_set_rate(mdp5_kms->core_clk, 200000000);
|
||||
|
||||
/* set uninit-ed kms */
|
||||
priv->kms = &mdp5_kms->base.base;
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
mdp5_kms->rpm_enabled = true;
|
||||
|
||||
@ -890,13 +892,10 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
/* set uninit-ed kms */
|
||||
priv->kms = &mdp5_kms->base.base;
|
||||
|
||||
return 0;
|
||||
fail:
|
||||
if (mdp5_kms)
|
||||
mdp5_destroy(pdev);
|
||||
mdp5_destroy(mdp5_kms);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -953,7 +952,8 @@ static int mdp5_dev_remove(struct platform_device *pdev)
|
||||
static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
|
||||
struct msm_drm_private *priv = platform_get_drvdata(pdev);
|
||||
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
|
||||
|
||||
DBG("");
|
||||
|
||||
@ -963,7 +963,8 @@ static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
|
||||
static __maybe_unused int mdp5_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
|
||||
struct msm_drm_private *priv = platform_get_drvdata(pdev);
|
||||
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
|
||||
|
||||
DBG("");
|
||||
|
||||
|
||||
@ -1600,20 +1600,10 @@ error:
|
||||
int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
|
||||
struct drm_encoder *encoder)
|
||||
{
|
||||
struct msm_drm_private *priv;
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct dp_display_private *dp_priv;
|
||||
int ret;
|
||||
|
||||
if (WARN_ON(!encoder) || WARN_ON(!dp_display) || WARN_ON(!dev))
|
||||
return -EINVAL;
|
||||
|
||||
priv = dev->dev_private;
|
||||
|
||||
if (priv->num_bridges == ARRAY_SIZE(priv->bridges)) {
|
||||
DRM_DEV_ERROR(dev->dev, "too many bridges\n");
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
dp_display->drm_dev = dev;
|
||||
|
||||
dp_priv = container_of(dp_display, struct dp_display_private, dp_display);
|
||||
|
||||
@ -49,23 +49,26 @@ static int dp_aux_link_power_up(struct drm_dp_aux *aux,
|
||||
struct dp_link_info *link)
|
||||
{
|
||||
u8 value;
|
||||
int err;
|
||||
ssize_t len;
|
||||
int i;
|
||||
|
||||
if (link->revision < 0x11)
|
||||
return 0;
|
||||
|
||||
err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
|
||||
if (err < 0)
|
||||
return err;
|
||||
len = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
|
||||
if (len < 0)
|
||||
return len;
|
||||
|
||||
value &= ~DP_SET_POWER_MASK;
|
||||
value |= DP_SET_POWER_D0;
|
||||
|
||||
err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
usleep_range(1000, 2000);
|
||||
/* retry for 1ms to give the sink time to wake up */
|
||||
for (i = 0; i < 3; i++) {
|
||||
len = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
|
||||
usleep_range(1000, 2000);
|
||||
if (len == 1)
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -211,14 +211,9 @@ void __exit msm_dsi_unregister(void)
|
||||
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
|
||||
struct drm_encoder *encoder)
|
||||
{
|
||||
struct msm_drm_private *priv;
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
int ret;
|
||||
|
||||
if (WARN_ON(!encoder) || WARN_ON(!msm_dsi) || WARN_ON(!dev))
|
||||
return -EINVAL;
|
||||
|
||||
priv = dev->dev_private;
|
||||
|
||||
if (priv->num_bridges == ARRAY_SIZE(priv->bridges)) {
|
||||
DRM_DEV_ERROR(dev->dev, "too many bridges\n");
|
||||
return -ENOSPC;
|
||||
|
||||
@ -21,6 +21,7 @@
|
||||
|
||||
#include <video/mipi_display.h>
|
||||
|
||||
#include <drm/display/drm_dsc_helper.h>
|
||||
#include <drm/drm_of.h>
|
||||
|
||||
#include "dsi.h"
|
||||
@ -33,7 +34,7 @@
|
||||
|
||||
#define DSI_RESET_TOGGLE_DELAY_MS 20
|
||||
|
||||
static int dsi_populate_dsc_params(struct drm_dsc_config *dsc);
|
||||
static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
|
||||
|
||||
static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
|
||||
{
|
||||
@ -842,17 +843,15 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
|
||||
static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay)
|
||||
{
|
||||
struct drm_dsc_config *dsc = msm_host->dsc;
|
||||
u32 reg, intf_width, reg_ctrl, reg_ctrl2;
|
||||
u32 reg, reg_ctrl, reg_ctrl2;
|
||||
u32 slice_per_intf, total_bytes_per_intf;
|
||||
u32 pkt_per_line;
|
||||
u32 bytes_in_slice;
|
||||
u32 eol_byte_num;
|
||||
|
||||
/* first calculate dsc parameters and then program
|
||||
* compress mode registers
|
||||
*/
|
||||
intf_width = hdisplay;
|
||||
slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width);
|
||||
slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
|
||||
|
||||
/* If slice_per_pkt is greater than slice_per_intf
|
||||
* then default to 1. This can happen during partial
|
||||
@ -861,12 +860,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod
|
||||
if (slice_per_intf > dsc->slice_count)
|
||||
dsc->slice_count = 1;
|
||||
|
||||
slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
|
||||
bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8);
|
||||
|
||||
dsc->slice_chunk_size = bytes_in_slice;
|
||||
|
||||
total_bytes_per_intf = bytes_in_slice * slice_per_intf;
|
||||
total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
|
||||
|
||||
eol_byte_num = total_bytes_per_intf % 3;
|
||||
pkt_per_line = slice_per_intf / dsc->slice_count;
|
||||
@ -892,7 +886,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod
|
||||
reg_ctrl |= reg;
|
||||
|
||||
reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
|
||||
reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(bytes_in_slice);
|
||||
reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size);
|
||||
|
||||
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl);
|
||||
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
|
||||
@ -915,6 +909,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
|
||||
u32 va_end = va_start + mode->vdisplay;
|
||||
u32 hdisplay = mode->hdisplay;
|
||||
u32 wc;
|
||||
int ret;
|
||||
|
||||
DBG("");
|
||||
|
||||
@ -950,7 +945,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
|
||||
/* we do the calculations for dsc parameters here so that
|
||||
* panel can use these parameters
|
||||
*/
|
||||
dsi_populate_dsc_params(dsc);
|
||||
ret = dsi_populate_dsc_params(msm_host, dsc);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* Divide the display by 3 but keep back/font porch and
|
||||
* pulse width same
|
||||
@ -1754,18 +1751,20 @@ static char bpg_offset[DSC_NUM_BUF_RANGES] = {
|
||||
2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
|
||||
};
|
||||
|
||||
static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
|
||||
static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
|
||||
{
|
||||
int mux_words_size;
|
||||
int groups_per_line, groups_total;
|
||||
int min_rate_buffer_size;
|
||||
int hrd_delay;
|
||||
int pre_num_extra_mux_bits, num_extra_mux_bits;
|
||||
int slice_bits;
|
||||
int target_bpp_x16;
|
||||
int data;
|
||||
int final_value, final_scale;
|
||||
int i;
|
||||
u16 bpp = dsc->bits_per_pixel >> 4;
|
||||
|
||||
if (dsc->bits_per_pixel & 0xf) {
|
||||
DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (dsc->bits_per_component != 8) {
|
||||
DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n");
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
dsc->rc_model_size = 8192;
|
||||
dsc->first_line_bpg_offset = 12;
|
||||
@ -1783,16 +1782,21 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
|
||||
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
|
||||
dsc->rc_range_params[i].range_min_qp = min_qp[i];
|
||||
dsc->rc_range_params[i].range_max_qp = max_qp[i];
|
||||
dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i];
|
||||
/*
|
||||
* Range BPG Offset contains two's-complement signed values that fill
|
||||
* 8 bits, yet the registers and DCS PPS field are only 6 bits wide.
|
||||
*/
|
||||
dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK;
|
||||
}
|
||||
|
||||
dsc->initial_offset = 6144; /* Not bpp 12 */
|
||||
if (dsc->bits_per_pixel != 8)
|
||||
dsc->initial_offset = 6144; /* Not bpp 12 */
|
||||
if (bpp != 8)
|
||||
dsc->initial_offset = 2048; /* bpp = 12 */
|
||||
|
||||
mux_words_size = 48; /* bpc == 8/10 */
|
||||
if (dsc->bits_per_component == 12)
|
||||
mux_words_size = 64;
|
||||
if (dsc->bits_per_component <= 10)
|
||||
dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
|
||||
else
|
||||
dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
|
||||
|
||||
dsc->initial_xmit_delay = 512;
|
||||
dsc->initial_scale_value = 32;
|
||||
@ -1804,63 +1808,8 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
|
||||
dsc->flatness_max_qp = 12;
|
||||
dsc->rc_quant_incr_limit0 = 11;
|
||||
dsc->rc_quant_incr_limit1 = 11;
|
||||
dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
|
||||
|
||||
/* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
|
||||
* params are calculated
|
||||
*/
|
||||
groups_per_line = DIV_ROUND_UP(dsc->slice_width, 3);
|
||||
dsc->slice_chunk_size = dsc->slice_width * dsc->bits_per_pixel / 8;
|
||||
if ((dsc->slice_width * dsc->bits_per_pixel) % 8)
|
||||
dsc->slice_chunk_size++;
|
||||
|
||||
/* rbs-min */
|
||||
min_rate_buffer_size = dsc->rc_model_size - dsc->initial_offset +
|
||||
dsc->initial_xmit_delay * dsc->bits_per_pixel +
|
||||
groups_per_line * dsc->first_line_bpg_offset;
|
||||
|
||||
hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->bits_per_pixel);
|
||||
|
||||
dsc->initial_dec_delay = hrd_delay - dsc->initial_xmit_delay;
|
||||
|
||||
dsc->initial_scale_value = 8 * dsc->rc_model_size /
|
||||
(dsc->rc_model_size - dsc->initial_offset);
|
||||
|
||||
slice_bits = 8 * dsc->slice_chunk_size * dsc->slice_height;
|
||||
|
||||
groups_total = groups_per_line * dsc->slice_height;
|
||||
|
||||
data = dsc->first_line_bpg_offset * 2048;
|
||||
|
||||
dsc->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->slice_height - 1));
|
||||
|
||||
pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->bits_per_component + 4) - 2);
|
||||
|
||||
num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
|
||||
((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
|
||||
|
||||
data = 2048 * (dsc->rc_model_size - dsc->initial_offset + num_extra_mux_bits);
|
||||
dsc->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
|
||||
|
||||
/* bpp * 16 + 0.5 */
|
||||
data = dsc->bits_per_pixel * 16;
|
||||
data *= 2;
|
||||
data++;
|
||||
data /= 2;
|
||||
target_bpp_x16 = data;
|
||||
|
||||
data = (dsc->initial_xmit_delay * target_bpp_x16) / 16;
|
||||
final_value = dsc->rc_model_size - data + num_extra_mux_bits;
|
||||
dsc->final_offset = final_value;
|
||||
|
||||
final_scale = 8 * dsc->rc_model_size / (dsc->rc_model_size - final_value);
|
||||
|
||||
data = (final_scale - 9) * (dsc->nfl_bpg_offset + dsc->slice_bpg_offset);
|
||||
dsc->scale_increment_interval = (2048 * dsc->final_offset) / data;
|
||||
|
||||
dsc->scale_decrement_interval = groups_per_line / (dsc->initial_scale_value - 8);
|
||||
|
||||
return 0;
|
||||
return drm_dsc_compute_rc_parameters(dsc);
|
||||
}
|
||||
|
||||
static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
|
||||
|
||||
@ -549,6 +549,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
|
||||
#ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
|
||||
{ .compatible = "qcom,dsi-phy-14nm",
|
||||
.data = &dsi_phy_14nm_cfgs },
|
||||
{ .compatible = "qcom,dsi-phy-14nm-2290",
|
||||
.data = &dsi_phy_14nm_2290_cfgs },
|
||||
{ .compatible = "qcom,dsi-phy-14nm-660",
|
||||
.data = &dsi_phy_14nm_660_cfgs },
|
||||
{ .compatible = "qcom,dsi-phy-14nm-8953",
|
||||
|
||||
@ -50,6 +50,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
|
||||
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
|
||||
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
|
||||
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
|
||||
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
|
||||
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
|
||||
extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
|
||||
extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
|
||||
|
||||
@ -1081,3 +1081,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
|
||||
.io_start = { 0x1a94400, 0x1a96400 },
|
||||
.num_dsi_phy = 2,
|
||||
};
|
||||
|
||||
const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
|
||||
.has_phy_lane = true,
|
||||
.regulator_data = dsi_phy_14nm_17mA_regulators,
|
||||
.num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
|
||||
.ops = {
|
||||
.enable = dsi_14nm_phy_enable,
|
||||
.disable = dsi_14nm_phy_disable,
|
||||
.pll_init = dsi_pll_14nm_init,
|
||||
.save_pll_state = dsi_14nm_pll_save_state,
|
||||
.restore_pll_state = dsi_14nm_pll_restore_state,
|
||||
},
|
||||
.min_pll_rate = VCO_MIN_RATE,
|
||||
.max_pll_rate = VCO_MAX_RATE,
|
||||
.io_start = { 0x5e94400 },
|
||||
.num_dsi_phy = 1,
|
||||
};
|
||||
|
||||
@ -68,16 +68,17 @@ static void msm_hdmi_destroy(struct hdmi *hdmi)
|
||||
destroy_workqueue(hdmi->workq);
|
||||
msm_hdmi_hdcp_destroy(hdmi);
|
||||
|
||||
if (hdmi->i2c)
|
||||
msm_hdmi_i2c_destroy(hdmi->i2c);
|
||||
}
|
||||
|
||||
static void msm_hdmi_put_phy(struct hdmi *hdmi)
|
||||
{
|
||||
if (hdmi->phy_dev) {
|
||||
put_device(hdmi->phy_dev);
|
||||
hdmi->phy = NULL;
|
||||
hdmi->phy_dev = NULL;
|
||||
}
|
||||
|
||||
if (hdmi->i2c)
|
||||
msm_hdmi_i2c_destroy(hdmi->i2c);
|
||||
|
||||
platform_set_drvdata(hdmi->pdev, NULL);
|
||||
}
|
||||
|
||||
static int msm_hdmi_get_phy(struct hdmi *hdmi)
|
||||
@ -93,22 +94,18 @@ static int msm_hdmi_get_phy(struct hdmi *hdmi)
|
||||
}
|
||||
|
||||
phy_pdev = of_find_device_by_node(phy_node);
|
||||
if (phy_pdev)
|
||||
hdmi->phy = platform_get_drvdata(phy_pdev);
|
||||
|
||||
of_node_put(phy_node);
|
||||
|
||||
if (!phy_pdev) {
|
||||
DRM_DEV_ERROR(&pdev->dev, "phy driver is not ready\n");
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
if (!phy_pdev)
|
||||
return dev_err_probe(&pdev->dev, -EPROBE_DEFER, "phy driver is not ready\n");
|
||||
|
||||
hdmi->phy = platform_get_drvdata(phy_pdev);
|
||||
if (!hdmi->phy) {
|
||||
DRM_DEV_ERROR(&pdev->dev, "phy driver is not ready\n");
|
||||
put_device(&phy_pdev->dev);
|
||||
return -EPROBE_DEFER;
|
||||
return dev_err_probe(&pdev->dev, -EPROBE_DEFER, "phy driver is not ready\n");
|
||||
}
|
||||
|
||||
hdmi->phy_dev = get_device(&phy_pdev->dev);
|
||||
hdmi->phy_dev = &phy_pdev->dev;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -117,142 +114,10 @@ static int msm_hdmi_get_phy(struct hdmi *hdmi)
|
||||
* we are to EPROBE_DEFER we want to do it here, rather than later
|
||||
* at modeset_init() time
|
||||
*/
|
||||
static struct hdmi *msm_hdmi_init(struct platform_device *pdev)
|
||||
static int msm_hdmi_init(struct hdmi *hdmi)
|
||||
{
|
||||
struct hdmi_platform_config *config = pdev->dev.platform_data;
|
||||
struct hdmi *hdmi = NULL;
|
||||
struct resource *res;
|
||||
int i, ret;
|
||||
|
||||
hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
|
||||
if (!hdmi) {
|
||||
ret = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
hdmi->pdev = pdev;
|
||||
hdmi->config = config;
|
||||
spin_lock_init(&hdmi->reg_lock);
|
||||
|
||||
ret = drm_of_find_panel_or_bridge(pdev->dev.of_node, 1, 0, NULL, &hdmi->next_bridge);
|
||||
if (ret && ret != -ENODEV)
|
||||
goto fail;
|
||||
|
||||
hdmi->mmio = msm_ioremap(pdev, config->mmio_name);
|
||||
if (IS_ERR(hdmi->mmio)) {
|
||||
ret = PTR_ERR(hdmi->mmio);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* HDCP needs physical address of hdmi register */
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
config->mmio_name);
|
||||
if (!res) {
|
||||
ret = -EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
hdmi->mmio_phy_addr = res->start;
|
||||
|
||||
hdmi->qfprom_mmio = msm_ioremap(pdev, config->qfprom_mmio_name);
|
||||
if (IS_ERR(hdmi->qfprom_mmio)) {
|
||||
DRM_DEV_INFO(&pdev->dev, "can't find qfprom resource\n");
|
||||
hdmi->qfprom_mmio = NULL;
|
||||
}
|
||||
|
||||
hdmi->hpd_regs = devm_kcalloc(&pdev->dev,
|
||||
config->hpd_reg_cnt,
|
||||
sizeof(hdmi->hpd_regs[0]),
|
||||
GFP_KERNEL);
|
||||
if (!hdmi->hpd_regs) {
|
||||
ret = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
for (i = 0; i < config->hpd_reg_cnt; i++)
|
||||
hdmi->hpd_regs[i].supply = config->hpd_reg_names[i];
|
||||
|
||||
ret = devm_regulator_bulk_get(&pdev->dev, config->hpd_reg_cnt, hdmi->hpd_regs);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(&pdev->dev, "failed to get hpd regulator: %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
hdmi->pwr_regs = devm_kcalloc(&pdev->dev,
|
||||
config->pwr_reg_cnt,
|
||||
sizeof(hdmi->pwr_regs[0]),
|
||||
GFP_KERNEL);
|
||||
if (!hdmi->pwr_regs) {
|
||||
ret = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
for (i = 0; i < config->pwr_reg_cnt; i++)
|
||||
hdmi->pwr_regs[i].supply = config->pwr_reg_names[i];
|
||||
|
||||
ret = devm_regulator_bulk_get(&pdev->dev, config->pwr_reg_cnt, hdmi->pwr_regs);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(&pdev->dev, "failed to get pwr regulator: %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
hdmi->hpd_clks = devm_kcalloc(&pdev->dev,
|
||||
config->hpd_clk_cnt,
|
||||
sizeof(hdmi->hpd_clks[0]),
|
||||
GFP_KERNEL);
|
||||
if (!hdmi->hpd_clks) {
|
||||
ret = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
for (i = 0; i < config->hpd_clk_cnt; i++) {
|
||||
struct clk *clk;
|
||||
|
||||
clk = msm_clk_get(pdev, config->hpd_clk_names[i]);
|
||||
if (IS_ERR(clk)) {
|
||||
ret = PTR_ERR(clk);
|
||||
DRM_DEV_ERROR(&pdev->dev, "failed to get hpd clk: %s (%d)\n",
|
||||
config->hpd_clk_names[i], ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
hdmi->hpd_clks[i] = clk;
|
||||
}
|
||||
|
||||
hdmi->pwr_clks = devm_kcalloc(&pdev->dev,
|
||||
config->pwr_clk_cnt,
|
||||
sizeof(hdmi->pwr_clks[0]),
|
||||
GFP_KERNEL);
|
||||
if (!hdmi->pwr_clks) {
|
||||
ret = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
for (i = 0; i < config->pwr_clk_cnt; i++) {
|
||||
struct clk *clk;
|
||||
|
||||
clk = msm_clk_get(pdev, config->pwr_clk_names[i]);
|
||||
if (IS_ERR(clk)) {
|
||||
ret = PTR_ERR(clk);
|
||||
DRM_DEV_ERROR(&pdev->dev, "failed to get pwr clk: %s (%d)\n",
|
||||
config->pwr_clk_names[i], ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
hdmi->pwr_clks[i] = clk;
|
||||
}
|
||||
|
||||
hdmi->hpd_gpiod = devm_gpiod_get_optional(&pdev->dev, "hpd", GPIOD_IN);
|
||||
/* This will catch e.g. -EPROBE_DEFER */
|
||||
if (IS_ERR(hdmi->hpd_gpiod)) {
|
||||
ret = PTR_ERR(hdmi->hpd_gpiod);
|
||||
DRM_DEV_ERROR(&pdev->dev, "failed to get hpd gpio: (%d)\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (!hdmi->hpd_gpiod)
|
||||
DBG("failed to get HPD gpio");
|
||||
|
||||
if (hdmi->hpd_gpiod)
|
||||
gpiod_set_consumer_name(hdmi->hpd_gpiod, "HDMI_HPD");
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
struct platform_device *pdev = hdmi->pdev;
|
||||
int ret;
|
||||
|
||||
hdmi->workq = alloc_ordered_workqueue("msm_hdmi", 0);
|
||||
|
||||
@ -264,25 +129,18 @@ static struct hdmi *msm_hdmi_init(struct platform_device *pdev)
|
||||
goto fail;
|
||||
}
|
||||
|
||||
ret = msm_hdmi_get_phy(hdmi);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(&pdev->dev, "failed to get phy\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
hdmi->hdcp_ctrl = msm_hdmi_hdcp_init(hdmi);
|
||||
if (IS_ERR(hdmi->hdcp_ctrl)) {
|
||||
dev_warn(&pdev->dev, "failed to init hdcp: disabled\n");
|
||||
hdmi->hdcp_ctrl = NULL;
|
||||
}
|
||||
|
||||
return hdmi;
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
if (hdmi)
|
||||
msm_hdmi_destroy(hdmi);
|
||||
msm_hdmi_destroy(hdmi);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Second part of initialization, the drm/kms level modeset_init,
|
||||
@ -297,7 +155,6 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
|
||||
struct drm_device *dev, struct drm_encoder *encoder)
|
||||
{
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct platform_device *pdev = hdmi->pdev;
|
||||
int ret;
|
||||
|
||||
if (priv->num_bridges == ARRAY_SIZE(priv->bridges)) {
|
||||
@ -337,13 +194,6 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
|
||||
|
||||
drm_connector_attach_encoder(hdmi->connector, hdmi->encoder);
|
||||
|
||||
hdmi->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
|
||||
if (!hdmi->irq) {
|
||||
ret = -EINVAL;
|
||||
DRM_DEV_ERROR(dev->dev, "failed to get irq\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(dev->dev, hdmi->irq,
|
||||
msm_hdmi_irq, IRQF_TRIGGER_HIGH,
|
||||
"hdmi_isr", hdmi);
|
||||
@ -363,8 +213,6 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
|
||||
|
||||
priv->bridges[priv->num_bridges++] = hdmi->bridge;
|
||||
|
||||
platform_set_drvdata(pdev, hdmi);
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
@ -392,7 +240,7 @@ fail:
|
||||
static const char *hpd_reg_names_8960[] = {"core-vdda"};
|
||||
static const char *hpd_clk_names_8960[] = {"core", "master_iface", "slave_iface"};
|
||||
|
||||
static struct hdmi_platform_config hdmi_tx_8960_config = {
|
||||
static const struct hdmi_platform_config hdmi_tx_8960_config = {
|
||||
HDMI_CFG(hpd_reg, 8960),
|
||||
HDMI_CFG(hpd_clk, 8960),
|
||||
};
|
||||
@ -402,7 +250,7 @@ static const char *pwr_clk_names_8x74[] = {"extp", "alt_iface"};
|
||||
static const char *hpd_clk_names_8x74[] = {"iface", "core", "mdp_core"};
|
||||
static unsigned long hpd_clk_freq_8x74[] = {0, 19200000, 0};
|
||||
|
||||
static struct hdmi_platform_config hdmi_tx_8974_config = {
|
||||
static const struct hdmi_platform_config hdmi_tx_8974_config = {
|
||||
HDMI_CFG(pwr_reg, 8x74),
|
||||
HDMI_CFG(pwr_clk, 8x74),
|
||||
HDMI_CFG(hpd_clk, 8x74),
|
||||
@ -517,26 +365,12 @@ static int msm_hdmi_register_audio_driver(struct hdmi *hdmi, struct device *dev)
|
||||
static int msm_hdmi_bind(struct device *dev, struct device *master, void *data)
|
||||
{
|
||||
struct msm_drm_private *priv = dev_get_drvdata(master);
|
||||
struct hdmi_platform_config *hdmi_cfg;
|
||||
struct hdmi *hdmi;
|
||||
struct device_node *of_node = dev->of_node;
|
||||
struct hdmi *hdmi = dev_get_drvdata(dev);
|
||||
int err;
|
||||
|
||||
hdmi_cfg = (struct hdmi_platform_config *)
|
||||
of_device_get_match_data(dev);
|
||||
if (!hdmi_cfg) {
|
||||
DRM_DEV_ERROR(dev, "unknown hdmi_cfg: %pOFn\n", of_node);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
hdmi_cfg->mmio_name = "core_physical";
|
||||
hdmi_cfg->qfprom_mmio_name = "qfprom_physical";
|
||||
|
||||
dev->platform_data = hdmi_cfg;
|
||||
|
||||
hdmi = msm_hdmi_init(to_platform_device(dev));
|
||||
if (IS_ERR(hdmi))
|
||||
return PTR_ERR(hdmi);
|
||||
err = msm_hdmi_init(hdmi);
|
||||
if (err)
|
||||
return err;
|
||||
priv->hdmi = hdmi;
|
||||
|
||||
err = msm_hdmi_register_audio_driver(hdmi, dev);
|
||||
@ -569,12 +403,150 @@ static const struct component_ops msm_hdmi_ops = {
|
||||
|
||||
static int msm_hdmi_dev_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct hdmi_platform_config *config;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct hdmi *hdmi;
|
||||
struct resource *res;
|
||||
int i, ret;
|
||||
|
||||
config = of_device_get_match_data(dev);
|
||||
if (!config)
|
||||
return -EINVAL;
|
||||
|
||||
hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
|
||||
if (!hdmi)
|
||||
return -ENOMEM;
|
||||
|
||||
hdmi->pdev = pdev;
|
||||
hdmi->config = config;
|
||||
spin_lock_init(&hdmi->reg_lock);
|
||||
|
||||
ret = drm_of_find_panel_or_bridge(pdev->dev.of_node, 1, 0, NULL, &hdmi->next_bridge);
|
||||
if (ret && ret != -ENODEV)
|
||||
return ret;
|
||||
|
||||
hdmi->mmio = msm_ioremap(pdev, "core_physical");
|
||||
if (IS_ERR(hdmi->mmio))
|
||||
return PTR_ERR(hdmi->mmio);
|
||||
|
||||
/* HDCP needs physical address of hdmi register */
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"core_physical");
|
||||
if (!res)
|
||||
return -EINVAL;
|
||||
hdmi->mmio_phy_addr = res->start;
|
||||
|
||||
hdmi->qfprom_mmio = msm_ioremap(pdev, "qfprom_physical");
|
||||
if (IS_ERR(hdmi->qfprom_mmio)) {
|
||||
DRM_DEV_INFO(&pdev->dev, "can't find qfprom resource\n");
|
||||
hdmi->qfprom_mmio = NULL;
|
||||
}
|
||||
|
||||
hdmi->irq = platform_get_irq(pdev, 0);
|
||||
if (hdmi->irq < 0)
|
||||
return hdmi->irq;
|
||||
|
||||
hdmi->hpd_regs = devm_kcalloc(&pdev->dev,
|
||||
config->hpd_reg_cnt,
|
||||
sizeof(hdmi->hpd_regs[0]),
|
||||
GFP_KERNEL);
|
||||
if (!hdmi->hpd_regs)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < config->hpd_reg_cnt; i++)
|
||||
hdmi->hpd_regs[i].supply = config->hpd_reg_names[i];
|
||||
|
||||
ret = devm_regulator_bulk_get(&pdev->dev, config->hpd_reg_cnt, hdmi->hpd_regs);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to get hpd regulators\n");
|
||||
|
||||
hdmi->pwr_regs = devm_kcalloc(&pdev->dev,
|
||||
config->pwr_reg_cnt,
|
||||
sizeof(hdmi->pwr_regs[0]),
|
||||
GFP_KERNEL);
|
||||
if (!hdmi->pwr_regs)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < config->pwr_reg_cnt; i++)
|
||||
hdmi->pwr_regs[i].supply = config->pwr_reg_names[i];
|
||||
|
||||
ret = devm_regulator_bulk_get(&pdev->dev, config->pwr_reg_cnt, hdmi->pwr_regs);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to get pwr regulators\n");
|
||||
|
||||
hdmi->hpd_clks = devm_kcalloc(&pdev->dev,
|
||||
config->hpd_clk_cnt,
|
||||
sizeof(hdmi->hpd_clks[0]),
|
||||
GFP_KERNEL);
|
||||
if (!hdmi->hpd_clks)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < config->hpd_clk_cnt; i++) {
|
||||
struct clk *clk;
|
||||
|
||||
clk = msm_clk_get(pdev, config->hpd_clk_names[i]);
|
||||
if (IS_ERR(clk))
|
||||
return dev_err_probe(dev, PTR_ERR(clk),
|
||||
"failed to get hpd clk: %s\n",
|
||||
config->hpd_clk_names[i]);
|
||||
|
||||
hdmi->hpd_clks[i] = clk;
|
||||
}
|
||||
|
||||
hdmi->pwr_clks = devm_kcalloc(&pdev->dev,
|
||||
config->pwr_clk_cnt,
|
||||
sizeof(hdmi->pwr_clks[0]),
|
||||
GFP_KERNEL);
|
||||
if (!hdmi->pwr_clks)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < config->pwr_clk_cnt; i++) {
|
||||
struct clk *clk;
|
||||
|
||||
clk = msm_clk_get(pdev, config->pwr_clk_names[i]);
|
||||
if (IS_ERR(clk))
|
||||
return dev_err_probe(dev, PTR_ERR(clk),
|
||||
"failed to get pwr clk: %s\n",
|
||||
config->pwr_clk_names[i]);
|
||||
|
||||
hdmi->pwr_clks[i] = clk;
|
||||
}
|
||||
|
||||
hdmi->hpd_gpiod = devm_gpiod_get_optional(&pdev->dev, "hpd", GPIOD_IN);
|
||||
/* This will catch e.g. -EPROBE_DEFER */
|
||||
if (IS_ERR(hdmi->hpd_gpiod))
|
||||
return dev_err_probe(dev, PTR_ERR(hdmi->hpd_gpiod),
|
||||
"failed to get hpd gpio\n");
|
||||
|
||||
if (!hdmi->hpd_gpiod)
|
||||
DBG("failed to get HPD gpio");
|
||||
|
||||
if (hdmi->hpd_gpiod)
|
||||
gpiod_set_consumer_name(hdmi->hpd_gpiod, "HDMI_HPD");
|
||||
|
||||
ret = msm_hdmi_get_phy(hdmi);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(&pdev->dev, "failed to get phy\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_pm_runtime_enable(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, hdmi);
|
||||
|
||||
return component_add(&pdev->dev, &msm_hdmi_ops);
|
||||
}
|
||||
|
||||
static int msm_hdmi_dev_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct hdmi *hdmi = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
component_del(&pdev->dev, &msm_hdmi_ops);
|
||||
|
||||
msm_hdmi_put_phy(hdmi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -86,9 +86,6 @@ struct hdmi {
|
||||
|
||||
/* platform config data (ie. from DT, or pdata) */
|
||||
struct hdmi_platform_config {
|
||||
const char *mmio_name;
|
||||
const char *qfprom_mmio_name;
|
||||
|
||||
/* regulators that need to be on for hpd: */
|
||||
const char **hpd_reg_names;
|
||||
int hpd_reg_cnt;
|
||||
|
||||
@ -277,7 +277,6 @@ static int msm_drm_uninit(struct device *dev)
|
||||
|
||||
struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
|
||||
{
|
||||
struct iommu_domain *domain;
|
||||
struct msm_gem_address_space *aspace;
|
||||
struct msm_mmu *mmu;
|
||||
struct device *mdp_dev = dev->dev;
|
||||
@ -293,22 +292,21 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
|
||||
else
|
||||
iommu_dev = mdss_dev;
|
||||
|
||||
domain = iommu_domain_alloc(iommu_dev->bus);
|
||||
if (!domain) {
|
||||
mmu = msm_iommu_new(iommu_dev, 0);
|
||||
if (IS_ERR(mmu))
|
||||
return ERR_CAST(mmu);
|
||||
|
||||
if (!mmu) {
|
||||
drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
mmu = msm_iommu_new(iommu_dev, domain);
|
||||
if (IS_ERR(mmu)) {
|
||||
iommu_domain_free(domain);
|
||||
return ERR_CAST(mmu);
|
||||
}
|
||||
|
||||
aspace = msm_gem_address_space_create(mmu, "mdp_kms",
|
||||
0x1000, 0x100000000 - 0x1000);
|
||||
if (IS_ERR(aspace))
|
||||
if (IS_ERR(aspace)) {
|
||||
dev_err(mdp_dev, "aspace create, error %pe\n", aspace);
|
||||
mmu->funcs->destroy(mmu);
|
||||
}
|
||||
|
||||
return aspace;
|
||||
}
|
||||
@ -819,6 +817,7 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
|
||||
case MSM_INFO_GET_OFFSET:
|
||||
case MSM_INFO_GET_IOVA:
|
||||
case MSM_INFO_SET_IOVA:
|
||||
case MSM_INFO_GET_FLAGS:
|
||||
/* value returned as immediate, not pointer, so len==0: */
|
||||
if (args->len)
|
||||
return -EINVAL;
|
||||
@ -846,6 +845,15 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
|
||||
case MSM_INFO_SET_IOVA:
|
||||
ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
|
||||
break;
|
||||
case MSM_INFO_GET_FLAGS:
|
||||
if (obj->import_attach) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
/* Hide internal kernel-only flags: */
|
||||
args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS;
|
||||
ret = 0;
|
||||
break;
|
||||
case MSM_INFO_SET_NAME:
|
||||
/* length check should leave room for terminating null: */
|
||||
if (args->len >= sizeof(msm_obj->name)) {
|
||||
|
||||
@ -186,6 +186,13 @@ int msm_iommu_pagetable_params(struct msm_mmu *mmu,
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu)
|
||||
{
|
||||
struct msm_iommu *iommu = to_msm_iommu(mmu);
|
||||
|
||||
return &iommu->domain->geometry;
|
||||
}
|
||||
|
||||
static const struct msm_mmu_funcs pagetable_funcs = {
|
||||
.map = msm_iommu_pagetable_map,
|
||||
.unmap = msm_iommu_pagetable_unmap,
|
||||
@ -367,17 +374,23 @@ static const struct msm_mmu_funcs funcs = {
|
||||
.resume_translation = msm_iommu_resume_translation,
|
||||
};
|
||||
|
||||
struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain)
|
||||
struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks)
|
||||
{
|
||||
struct iommu_domain *domain;
|
||||
struct msm_iommu *iommu;
|
||||
int ret;
|
||||
|
||||
domain = iommu_domain_alloc(dev->bus);
|
||||
if (!domain)
|
||||
return ERR_PTR(-ENODEV);
|
||||
return NULL;
|
||||
|
||||
iommu_set_pgtable_quirks(domain, quirks);
|
||||
|
||||
iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
|
||||
if (!iommu)
|
||||
if (!iommu) {
|
||||
iommu_domain_free(domain);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
iommu->domain = domain;
|
||||
msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU);
|
||||
@ -386,6 +399,7 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain)
|
||||
|
||||
ret = iommu_attach_device(iommu->domain, dev);
|
||||
if (ret) {
|
||||
iommu_domain_free(domain);
|
||||
kfree(iommu);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
#define HW_REV 0x0
|
||||
#define HW_INTR_STATUS 0x0010
|
||||
|
||||
#define UBWC_DEC_HW_VERSION 0x58
|
||||
#define UBWC_STATIC 0x144
|
||||
#define UBWC_CTRL_2 0x150
|
||||
#define UBWC_PREDICTION_MODE 0x154
|
||||
@ -174,9 +175,63 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define UBWC_1_0 0x10000000
|
||||
#define UBWC_2_0 0x20000000
|
||||
#define UBWC_3_0 0x30000000
|
||||
#define UBWC_4_0 0x40000000
|
||||
|
||||
static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss,
|
||||
u32 ubwc_static)
|
||||
{
|
||||
writel_relaxed(ubwc_static, msm_mdss->mmio + UBWC_STATIC);
|
||||
}
|
||||
|
||||
static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss,
|
||||
unsigned int ubwc_version,
|
||||
u32 ubwc_swizzle,
|
||||
u32 highest_bank_bit,
|
||||
u32 macrotile_mode)
|
||||
{
|
||||
u32 value = (ubwc_swizzle & 0x1) |
|
||||
(highest_bank_bit & 0x3) << 4 |
|
||||
(macrotile_mode & 0x1) << 12;
|
||||
|
||||
if (ubwc_version == UBWC_3_0)
|
||||
value |= BIT(10);
|
||||
|
||||
if (ubwc_version == UBWC_1_0)
|
||||
value |= BIT(8);
|
||||
|
||||
writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
|
||||
}
|
||||
|
||||
static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss,
|
||||
unsigned int ubwc_version,
|
||||
u32 ubwc_swizzle,
|
||||
u32 ubwc_static,
|
||||
u32 highest_bank_bit,
|
||||
u32 macrotile_mode)
|
||||
{
|
||||
u32 value = (ubwc_swizzle & 0x7) |
|
||||
(ubwc_static & 0x1) << 3 |
|
||||
(highest_bank_bit & 0x7) << 4 |
|
||||
(macrotile_mode & 0x1) << 12;
|
||||
|
||||
writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
|
||||
|
||||
if (ubwc_version == UBWC_3_0) {
|
||||
writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
|
||||
writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
|
||||
} else {
|
||||
writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
|
||||
writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
|
||||
}
|
||||
}
|
||||
|
||||
static int msm_mdss_enable(struct msm_mdss *msm_mdss)
|
||||
{
|
||||
int ret;
|
||||
u32 hw_rev;
|
||||
|
||||
/*
|
||||
* Several components have AXI clocks that can only be turned on if
|
||||
@ -198,26 +253,39 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
|
||||
if (msm_mdss->is_mdp5)
|
||||
return 0;
|
||||
|
||||
hw_rev = readl_relaxed(msm_mdss->mmio + HW_REV);
|
||||
dev_dbg(msm_mdss->dev, "HW_REV: 0x%x\n", hw_rev);
|
||||
dev_dbg(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
|
||||
readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION));
|
||||
|
||||
/*
|
||||
* ubwc config is part of the "mdss" region which is not accessible
|
||||
* from the rest of the driver. hardcode known configurations here
|
||||
*
|
||||
* Decoder version can be read from the UBWC_DEC_HW_VERSION reg,
|
||||
* UBWC_n and the rest of params comes from hw_catalog.
|
||||
* Unforunately this driver can not access hw catalog, so we have to
|
||||
* hardcode them here.
|
||||
*/
|
||||
switch (readl_relaxed(msm_mdss->mmio + HW_REV)) {
|
||||
switch (hw_rev) {
|
||||
case DPU_HW_VER_500:
|
||||
case DPU_HW_VER_501:
|
||||
writel_relaxed(0x420, msm_mdss->mmio + UBWC_STATIC);
|
||||
msm_mdss_setup_ubwc_dec_30(msm_mdss, UBWC_3_0, 0, 2, 0);
|
||||
break;
|
||||
case DPU_HW_VER_600:
|
||||
/* TODO: 0x102e for LP_DDR4 */
|
||||
writel_relaxed(0x103e, msm_mdss->mmio + UBWC_STATIC);
|
||||
writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
|
||||
writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
|
||||
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
|
||||
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
|
||||
break;
|
||||
case DPU_HW_VER_620:
|
||||
writel_relaxed(0x1e, msm_mdss->mmio + UBWC_STATIC);
|
||||
/* UBWC_2_0 */
|
||||
msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
|
||||
break;
|
||||
case DPU_HW_VER_630:
|
||||
/* UBWC_2_0 */
|
||||
msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x11f);
|
||||
break;
|
||||
case DPU_HW_VER_720:
|
||||
writel_relaxed(0x101e, msm_mdss->mmio + UBWC_STATIC);
|
||||
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -445,6 +513,7 @@ static const struct of_device_id mdss_dt_match[] = {
|
||||
{ .compatible = "qcom,sc7180-mdss" },
|
||||
{ .compatible = "qcom,sc7280-mdss" },
|
||||
{ .compatible = "qcom,sc8180x-mdss" },
|
||||
{ .compatible = "qcom,sm6115-mdss" },
|
||||
{ .compatible = "qcom,sm8150-mdss" },
|
||||
{ .compatible = "qcom,sm8250-mdss" },
|
||||
{}
|
||||
|
||||
@ -40,7 +40,7 @@ static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev,
|
||||
mmu->type = type;
|
||||
}
|
||||
|
||||
struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain);
|
||||
struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks);
|
||||
struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu);
|
||||
|
||||
static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg,
|
||||
@ -58,5 +58,6 @@ void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
|
||||
|
||||
int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
|
||||
int *asid);
|
||||
struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu);
|
||||
|
||||
#endif /* __MSM_MMU_H__ */
|
||||
|
||||
@ -138,6 +138,7 @@ struct drm_msm_gem_new {
|
||||
#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
|
||||
#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
|
||||
#define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */
|
||||
#define MSM_INFO_GET_FLAGS 0x05 /* get the MSM_BO_x flags */
|
||||
|
||||
struct drm_msm_gem_info {
|
||||
__u32 handle; /* in */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user