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drm/radeon/kms/legacy: set common regs to sane value
The DDX and radeonfb always set these regs to a sane value. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -1675,6 +1675,17 @@ int r100_gpu_reset(struct radeon_device *rdev)
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return 0;
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}
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void r100_set_common_regs(struct radeon_device *rdev)
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{
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/* set these so they don't interfere with anything */
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WREG32(RADEON_OV0_SCALE_CNTL, 0);
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WREG32(RADEON_SUBPIC_CNTL, 0);
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WREG32(RADEON_VIPH_CONTROL, 0);
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WREG32(RADEON_I2C_CNTL_1, 0);
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WREG32(RADEON_DVI_I2C_CNTL_1, 0);
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WREG32(RADEON_CAP0_TRIG_CNTL, 0);
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WREG32(RADEON_CAP1_TRIG_CNTL, 0);
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}
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/*
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* VRAM info
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@ -3129,6 +3140,9 @@ static int r100_startup(struct radeon_device *rdev)
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{
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int r;
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/* set common regs */
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r100_set_common_regs(rdev);
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/* program mc */
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r100_mc_program(rdev);
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/* Resume clock */
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r100_clock_startup(rdev);
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@ -1186,6 +1186,9 @@ static int r300_startup(struct radeon_device *rdev)
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{
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int r;
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/* set common regs */
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r100_set_common_regs(rdev);
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/* program mc */
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r300_mc_program(rdev);
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/* Resume clock */
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r300_clock_startup(rdev);
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@ -169,6 +169,9 @@ static int r420_startup(struct radeon_device *rdev)
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{
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int r;
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/* set common regs */
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r100_set_common_regs(rdev);
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/* program mc */
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r300_mc_program(rdev);
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/* Resume clock */
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r420_clock_resume(rdev);
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@ -1046,6 +1046,7 @@ extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx);
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extern void r100_enable_bm(struct radeon_device *rdev);
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extern void r100_set_common_regs(struct radeon_device *rdev);
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/* rv200,rv250,rv280 */
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extern void r200_set_safe_registers(struct radeon_device *rdev);
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