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drm/amdgpu: drop AMDGPU_FENCE_SIGNALED_SEQ
It's causing issues with VMID handling and comparing the fence value two times actually doesn't make handling faster. Port of radeon commit "d6d5c5b8364bcc4d52cddc68bcb0a330d2af20f3". Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com>
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@ -84,9 +84,6 @@ extern int amdgpu_vm_block_size;
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#define AMDGPUFB_CONN_LIMIT 4
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#define AMDGPU_BIOS_NUM_SCRATCH 8
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/* fence seq are set to this number when signaled */
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#define AMDGPU_FENCE_SIGNALED_SEQ 0LL
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/* max number of rings */
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#define AMDGPU_MAX_RINGS 16
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#define AMDGPU_MAX_GFX_RINGS 1
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@ -463,11 +463,7 @@ bool amdgpu_fence_signaled(struct amdgpu_fence *fence)
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if (!fence)
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return true;
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if (fence->seq == AMDGPU_FENCE_SIGNALED_SEQ)
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return true;
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if (amdgpu_fence_seq_signaled(fence->ring, fence->seq)) {
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fence->seq = AMDGPU_FENCE_SIGNALED_SEQ;
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if (!fence_signal(&fence->base))
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FENCE_TRACE(&fence->base, "signaled from amdgpu_fence_signaled\n");
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return true;
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@ -637,15 +633,11 @@ int amdgpu_fence_wait(struct amdgpu_fence *fence, bool intr)
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long r;
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seq[fence->ring->idx] = fence->seq;
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if (seq[fence->ring->idx] == AMDGPU_FENCE_SIGNALED_SEQ)
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return 0;
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r = amdgpu_fence_wait_seq_timeout(fence->ring->adev, seq, intr, MAX_SCHEDULE_TIMEOUT);
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if (r < 0) {
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return r;
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}
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fence->seq = AMDGPU_FENCE_SIGNALED_SEQ;
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r = fence_signal(&fence->base);
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if (!r)
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FENCE_TRACE(&fence->base, "signaled from fence_wait\n");
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@ -682,10 +674,6 @@ int amdgpu_fence_wait_any(struct amdgpu_device *adev,
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seq[i] = fences[i]->seq;
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++num_rings;
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/* test if something was allready signaled */
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if (seq[i] == AMDGPU_FENCE_SIGNALED_SEQ)
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return 0;
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}
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/* nothing to wait for ? */
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