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gpio: sch: Add support for Intel Quark X1000 SoC

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Intel Quark X1000 provides a total of 16 GPIOs. The GPIOs are split between
the legacy I/O bridge and the GPIO controller.

GPIO-SCH is the GPIO pins on legacy bridge for Intel Quark SoC.
Intel Quark X1000 has 2 GPIOs powered by the core power well and 6 from
the suspend power well.

This piece of work is derived from Dan O'Donovan's initial work for Quark
X1000 enabling.

Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Chang Rebecca Swee Fun 2014-12-08 17:38:10 +08:00 committed by Linus Walleij
parent ae9ca493ee
commit 9202149025
2 changed files with 15 additions and 2 deletions
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11
drivers/gpio/Kconfig
View File

@ -395,25 +395,32 @@ config GPIO_VR41XX
Say yes here to support the NEC VR4100 series General-purpose I/O Uint Say yes here to support the NEC VR4100 series General-purpose I/O Uint
config GPIO_SCH config GPIO_SCH
tristate "Intel SCH/TunnelCreek/Centerton GPIO" tristate "Intel SCH/TunnelCreek/Centerton/Quark X1000 GPIO"
depends on PCI && X86 depends on PCI && X86
select MFD_CORE select MFD_CORE
select LPC_SCH select LPC_SCH
help help
Say yes here to support GPIO interface on Intel Poulsbo SCH, Say yes here to support GPIO interface on Intel Poulsbo SCH,
Intel Tunnel Creek processor or Intel Centerton processor. Intel Tunnel Creek processor, Intel Centerton processor or
Intel Quark X1000 SoC.
The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are
powered by the core power rail and are turned off during sleep powered by the core power rail and are turned off during sleep
modes (S3 and higher). The remaining four GPIOs are powered by modes (S3 and higher). The remaining four GPIOs are powered by
the Intel SCH suspend power supply. These GPIOs remain the Intel SCH suspend power supply. These GPIOs remain
active during S3. The suspend powered GPIOs can be used to wake the active during S3. The suspend powered GPIOs can be used to wake the
system from the Suspend-to-RAM state. system from the Suspend-to-RAM state.
The Intel Tunnel Creek processor has 5 GPIOs powered by the The Intel Tunnel Creek processor has 5 GPIOs powered by the
core power rail and 9 from suspend power supply. core power rail and 9 from suspend power supply.
The Intel Centerton processor has a total of 30 GPIO pins. The Intel Centerton processor has a total of 30 GPIO pins.
Twenty-one are powered by the core power rail and 9 from the Twenty-one are powered by the core power rail and 9 from the
suspend power supply. suspend power supply.
The Intel Quark X1000 SoC has 2 GPIOs powered by the core
power well and 6 from the suspend power well.
config GPIO_ICH config GPIO_ICH
tristate "Intel ICH GPIO" tristate "Intel ICH GPIO"
depends on PCI && X86 depends on PCI && X86

6
drivers/gpio/gpio-sch.c
View File

@ -230,6 +230,12 @@ static int sch_gpio_probe(struct platform_device *pdev)
sch->chip.ngpio = 30; sch->chip.ngpio = 30;
break; break;
case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
sch->core_base = 0;
sch->resume_base = 2;
sch->chip.ngpio = 8;
break;
default: default:
return -ENODEV; return -ENODEV;
} }