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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

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* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (21 commits)
  MIPS: Alchemy: PB1200: use SMC91X platform data.
  MIPS: Alchemy: MIPS hazard workarounds are not required.
  MIPS: Alchemy: provide cpu feature overrides.
  MIPS: Alchemy: unify CPU model constants.
  MIPS: Make a needlessly global symbol static in arch/mips/kernel/smp.c
  MIPS: Fix global namespace pollution in arch/mips/kernel/smp-up.c
  MIPS: Malta: make a needlessly global integer variable static
  MIPS: Use BUG_ON() where possible.
  MIPS: Convert obsolete irq_desc_t to struct irq_desc
  MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms
  MIPS: EMMA2RH: Set UART mapbase
  MIPS: EMMA2RH: Use set_irq_chip_and_handler_name
  MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO interrupts
  MIPS: Mark Eins: Fix cascading interrupt dispatcher
  MIPS: Au1000: convert to using gpiolib
  MIPS: Stop using <asm-generic/int-l64.h>.
  MIPS: Cavium: Add -Werror
  MIPS: Makefile: Add simple make install target.
  MIPS: Compat: Zero upper 32-bit of offset_high and offset_low.
  MIPS: __raw_spin_lock() may spin forever on ticket wrap.
  ...
This commit is contained in:
Linus Torvalds 2009-03-30 10:36:35 -07:00
commit 915db32ddb
46 changed files with 353 additions and 314 deletions
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12
arch/mips/Kconfig
View File

@ -77,7 +77,6 @@ config MIPS_COBALT
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
config MACH_DECSTATION
bool "DECstations"
@ -132,7 +131,6 @@ config MACH_JAZZ
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_100HZ
select GENERIC_HARDIRQS_NO__DO_IRQ
help
This a family of machines based on the MIPS R4030 chipset which was
used by several vendors to build RISC/os and Windows NT workstations.
@ -154,7 +152,6 @@ config LASAT
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
config LEMOTE_FULONG
bool "Lemote Fulong mini-PC"
@ -175,7 +172,6 @@ config LEMOTE_FULONG
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select CPU_HAS_WB
help
@ -250,7 +246,6 @@ config MACH_VR41XX
select CEVT_R4K
select CSRC_R4K
select SYS_HAS_CPU_VR41XX
select GENERIC_HARDIRQS_NO__DO_IRQ
config NXP_STB220
bool "NXP STB220 board"
@ -364,7 +359,6 @@ config SGI_IP27
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP
select GENERIC_HARDIRQS_NO__DO_IRQ
help
This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
workstations. To compile a Linux kernel that runs on these, say Y
@ -563,7 +557,6 @@ config MIKROTIK_RB532
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select GENERIC_HARDIRQS_NO__DO_IRQ
select HW_HAS_PCI
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
@ -700,8 +693,7 @@ config SCHED_OMIT_FRAME_POINTER
default y
config GENERIC_HARDIRQS_NO__DO_IRQ
bool
default n
def_bool y
#
# Select some configuration options automatically based on user selections.
@ -920,7 +912,6 @@ config SOC_PNX833X
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_GPIO
select CPU_MIPSR2_IRQ_VI
@ -939,7 +930,6 @@ config SOC_PNX8550
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_GPIO
config SWAP_IO_SPACE

6
arch/mips/Makefile
View File

@ -720,11 +720,17 @@ ifdef CONFIG_MIPS32_O32
$(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=32"
endif
install:
$(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
$(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
$(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
archclean:
@$(MAKE) $(clean)=arch/mips/boot
@$(MAKE) $(clean)=arch/mips/lasat
define archhelp
echo ' install - install kernel into $(INSTALL_PATH)'
echo ' vmlinux.ecoff - ECOFF boot image'
echo ' vmlinux.bin - Raw binary boot image'
echo ' vmlinux.srec - SREC boot image'

2
arch/mips/alchemy/Kconfig
View File

@ -134,4 +134,4 @@ config SOC_AU1X00
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION
select GENERIC_HARDIRQS_NO__DO_IRQ
select ARCH_REQUIRE_GPIOLIB

203
arch/mips/alchemy/common/gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
* Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
* Architecture specific GPIO support
*
* This program is free software; you can redistribute it and/or modify it
@ -27,122 +27,175 @@
* others have a second one : GPIO2
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/gpio.h>
#define gpio1 sys
struct au1000_gpio_chip {
struct gpio_chip chip;
void __iomem *regbase;
};
#if !defined(CONFIG_SOC_AU1000)
static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE;
#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
static int au1xxx_gpio2_read(unsigned gpio)
static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
{
gpio -= AU1XXX_GPIO_BASE;
return ((gpio2->pinstate >> gpio) & 0x01);
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
}
static void au1xxx_gpio2_write(unsigned gpio, int value)
static void au1000_gpio2_set(struct gpio_chip *chip,
unsigned offset, int value)
{
gpio -= AU1XXX_GPIO_BASE;
u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
gpch = container_of(chip, struct au1000_gpio_chip, chip);
local_irq_save(flags);
writel(mask, gpch->regbase + AU1000_GPIO2_OUT);
local_irq_restore(flags);
}
static int au1xxx_gpio2_direction_input(unsigned gpio)
static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
{
gpio -= AU1XXX_GPIO_BASE;
gpio2->dir &= ~(0x01 << gpio);
u32 mask = 1 << offset;
u32 tmp;
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
local_irq_save(flags);
tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
tmp &= ~mask;
writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
local_irq_restore(flags);
return 0;
}
static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
static int au1000_gpio2_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
gpio -= AU1XXX_GPIO_BASE;
gpio2->dir |= 0x01 << gpio;
gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
u32 mask = 1 << offset;
u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
u32 tmp;
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
local_irq_save(flags);
tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
tmp |= mask;
writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT);
local_irq_restore(flags);
return 0;
}
#endif /* !defined(CONFIG_SOC_AU1000) */
static int au1xxx_gpio1_read(unsigned gpio)
static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
{
return (gpio1->pinstaterd >> gpio) & 0x01;
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
return readl(gpch->regbase + AU1000_GPIO1_ST) & mask;
}
static void au1xxx_gpio1_write(unsigned gpio, int value)
static void au1000_gpio1_set(struct gpio_chip *chip,
unsigned offset, int value)
{
u32 mask = 1 << offset;
u32 reg_offset;
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
if (value)
gpio1->outputset = (0x01 << gpio);
reg_offset = AU1000_GPIO1_OUT;
else
/* Output a zero */
gpio1->outputclr = (0x01 << gpio);
reg_offset = AU1000_GPIO1_CLR;
local_irq_save(flags);
writel(mask, gpch->regbase + reg_offset);
local_irq_restore(flags);
}
static int au1xxx_gpio1_direction_input(unsigned gpio)
static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
{
gpio1->pininputen = (0x01 << gpio);
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
writel(mask, gpch->regbase + AU1000_GPIO1_ST);
return 0;
}
static int au1xxx_gpio1_direction_output(unsigned gpio, int value)
static int au1000_gpio1_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
gpio1->trioutclr = (0x01 & gpio);
au1xxx_gpio1_write(gpio, value);
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT);
au1000_gpio1_set(chip, offset, value);
return 0;
}
int au1xxx_gpio_get_value(unsigned gpio)
{
if (gpio >= AU1XXX_GPIO_BASE)
#if defined(CONFIG_SOC_AU1000)
return 0;
#else
return au1xxx_gpio2_read(gpio);
struct au1000_gpio_chip au1000_gpio_chip[] = {
[0] = {
.regbase = (void __iomem *)SYS_BASE,
.chip = {
.label = "au1000-gpio1",
.direction_input = au1000_gpio1_direction_input,
.direction_output = au1000_gpio1_direction_output,
.get = au1000_gpio1_get,
.set = au1000_gpio1_set,
.base = 0,
.ngpio = 32,
},
},
#if !defined(CONFIG_SOC_AU1000)
[1] = {
.regbase = (void __iomem *)GPIO2_BASE,
.chip = {
.label = "au1000-gpio2",
.direction_input = au1000_gpio2_direction_input,
.direction_output = au1000_gpio2_direction_output,
.get = au1000_gpio2_get,
.set = au1000_gpio2_set,
.base = AU1XXX_GPIO_BASE,
.ngpio = 32,
},
},
#endif
else
return au1xxx_gpio1_read(gpio);
}
EXPORT_SYMBOL(au1xxx_gpio_get_value);
};
void au1xxx_gpio_set_value(unsigned gpio, int value)
static int __init au1000_gpio_init(void)
{
if (gpio >= AU1XXX_GPIO_BASE)
#if defined(CONFIG_SOC_AU1000)
;
#else
au1xxx_gpio2_write(gpio, value);
#endif
else
au1xxx_gpio1_write(gpio, value);
}
EXPORT_SYMBOL(au1xxx_gpio_set_value);
int au1xxx_gpio_direction_input(unsigned gpio)
{
if (gpio >= AU1XXX_GPIO_BASE)
#if defined(CONFIG_SOC_AU1000)
return -ENODEV;
#else
return au1xxx_gpio2_direction_input(gpio);
gpiochip_add(&au1000_gpio_chip[0].chip);
#if !defined(CONFIG_SOC_AU1000)
gpiochip_add(&au1000_gpio_chip[1].chip);
#endif
return au1xxx_gpio1_direction_input(gpio);
return 0;
}
EXPORT_SYMBOL(au1xxx_gpio_direction_input);
arch_initcall(au1000_gpio_init);
int au1xxx_gpio_direction_output(unsigned gpio, int value)
{
if (gpio >= AU1XXX_GPIO_BASE)
#if defined(CONFIG_SOC_AU1000)
return -ENODEV;
#else
return au1xxx_gpio2_direction_output(gpio, value);
#endif
return au1xxx_gpio1_direction_output(gpio, value);
}
EXPORT_SYMBOL(au1xxx_gpio_direction_output);

10
arch/mips/alchemy/devboards/pb1200/platform.c
View File

@ -22,6 +22,7 @@
#include <linux/init.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/smc91x.h>
#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-au1x00/au1100_mmc.h>
@ -131,6 +132,12 @@ static struct platform_device ide_device = {
.resource = ide_resources
};
static struct smc91x_platdata smc_data = {
.flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource smc91c111_resources[] = {
[0] = {
.name = "smc91x-regs",
@ -146,6 +153,9 @@ static struct resource smc91c111_resources[] = {
};
static struct platform_device smc91c111_device = {
.dev = {
.platform_data = &smc_data,
},
.name = "smc91x",
.id = -1,
.num_resources = ARRAY_SIZE(smc91c111_resources),

2
arch/mips/cavium-octeon/Makefile
View File

@ -14,3 +14,5 @@ obj-y += dma-octeon.o flash_setup.o
obj-y += octeon-memcpy.o
obj-$(CONFIG_SMP) += smp.o
EXTRA_CFLAGS += -Werror

2
arch/mips/cavium-octeon/flash_setup.c
View File

@ -57,7 +57,7 @@ static int __init flash_init(void)
flash_map.bankwidth = 1;
flash_map.virt = ioremap(flash_map.phys, flash_map.size);
pr_notice("Bootbus flash: Setting flash for %luMB flash at "
"0x%08lx\n", flash_map.size >> 20, flash_map.phys);
"0x%08llx\n", flash_map.size >> 20, flash_map.phys);
simple_map_init(&flash_map);
mymtd = do_map_probe("cfi_probe", &flash_map);
if (mymtd) {

2
arch/mips/cavium-octeon/octeon-irq.c
View File

@ -31,7 +31,7 @@ static void octeon_irq_core_ack(unsigned int irq)
static void octeon_irq_core_eoi(unsigned int irq)
{
irq_desc_t *desc = irq_desc + irq;
struct irq_desc *desc = irq_desc + irq;
unsigned int bit = irq - OCTEON_IRQ_SW0;
/*
* If an IRQ is being processed while we are disabling it the

50
arch/mips/emma/markeins/irq.c
View File

@ -80,9 +80,9 @@ void emma2rh_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
&emma2rh_irq_controller,
handle_level_irq);
set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
&emma2rh_irq_controller,
handle_level_irq, "level");
}
static void emma2rh_sw_irq_enable(unsigned int irq)
@ -120,9 +120,9 @@ void emma2rh_sw_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i,
&emma2rh_sw_irq_controller,
handle_level_irq);
set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
&emma2rh_sw_irq_controller,
handle_level_irq, "level");
}
static void emma2rh_gpio_irq_enable(unsigned int irq)
@ -148,6 +148,12 @@ static void emma2rh_gpio_irq_disable(unsigned int irq)
}
static void emma2rh_gpio_irq_ack(unsigned int irq)
{
irq -= EMMA2RH_GPIO_IRQ_BASE;
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
}
static void emma2rh_gpio_irq_mask_ack(unsigned int irq)
{
u32 reg;
@ -159,27 +165,12 @@ static void emma2rh_gpio_irq_ack(unsigned int irq)
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
static void emma2rh_gpio_irq_end(unsigned int irq)
{
u32 reg;
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
irq -= EMMA2RH_GPIO_IRQ_BASE;
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg |= 1 << irq;
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
}
struct irq_chip emma2rh_gpio_irq_controller = {
.name = "emma2rh_gpio_irq",
.ack = emma2rh_gpio_irq_ack,
.mask = emma2rh_gpio_irq_disable,
.mask_ack = emma2rh_gpio_irq_ack,
.mask_ack = emma2rh_gpio_irq_mask_ack,
.unmask = emma2rh_gpio_irq_enable,
.end = emma2rh_gpio_irq_end,
};
void emma2rh_gpio_irq_init(void)
@ -187,8 +178,9 @@ void emma2rh_gpio_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
&emma2rh_gpio_irq_controller);
set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
&emma2rh_gpio_irq_controller,
handle_edge_irq, "edge");
}
static struct irqaction irq_cascade = {
@ -213,8 +205,7 @@ void emma2rh_irq_dispatch(void)
emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
#ifdef EMMA2RH_SW_CASCADE
if (intStatus &
(1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) {
u32 swIntStatus;
swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
& emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
@ -225,6 +216,8 @@ void emma2rh_irq_dispatch(void)
}
}
}
/* Skip S/W interrupt */
intStatus &= ~(1UL << EMMA2RH_SW_CASCADE);
#endif
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
@ -238,8 +231,7 @@ void emma2rh_irq_dispatch(void)
emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
#ifdef EMMA2RH_GPIO_CASCADE
if (intStatus &
(1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) {
u32 gpioIntStatus;
gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
& emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
@ -250,6 +242,8 @@ void emma2rh_irq_dispatch(void)
}
}
}
/* Skip GPIO interrupt */
intStatus &= ~(1UL << (EMMA2RH_GPIO_CASCADE % 32));
#endif
for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {

3
arch/mips/emma/markeins/platform.c
View File

@ -110,6 +110,7 @@ struct platform_device i2c_emma_devices[] = {
static struct plat_serial8250_port platform_serial_ports[] = {
[0] = {
.membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
.mapbase = EMMA2RH_PFUR0_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR0,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,
@ -117,6 +118,7 @@ static struct plat_serial8250_port platform_serial_ports[] = {
.flags = EMMA2RH_SERIAL_FLAGS,
}, [1] = {
.membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
.mapbase = EMMA2RH_PFUR1_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR1,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,
@ -124,6 +126,7 @@ static struct plat_serial8250_port platform_serial_ports[] = {
.flags = EMMA2RH_SERIAL_FLAGS,
}, [2] = {
.membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
.mapbase = EMMA2RH_PFUR2_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR2,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,

3
arch/mips/include/asm/cpu.h
View File

@ -209,8 +209,7 @@ enum cpu_type_enum {
* MIPS32 class processors
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
/*
* MIPS64 class processors

4
arch/mips/include/asm/hazards.h
View File

@ -87,7 +87,7 @@ do { \
: "=r" (tmp)); \
} while (0)
#elif defined(CONFIG_CPU_MIPSR1)
#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
/*
* These are slightly complicated by the fact that we guarantee R1 kernels to
@ -139,7 +139,7 @@ do { \
} while (0)
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
defined(CONFIG_CPU_R5500)
defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.

49
arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h Normal file
View File

@ -0,0 +1,49 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_fpu 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_mcheck 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 0
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 1
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_vint 0
#define cpu_has_veic 0
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */

70
arch/mips/include/asm/mach-au1x00/gpio.h
View File

@ -5,65 +5,29 @@
#define AU1XXX_GPIO_BASE 200
struct au1x00_gpio2 {
u32 dir;
u32 reserved;
u32 output;
u32 pinstate;
u32 inten;
u32 enable;
};
/* GPIO bank 1 offsets */
#define AU1000_GPIO1_TRI_OUT 0x0100
#define AU1000_GPIO1_OUT 0x0108
#define AU1000_GPIO1_ST 0x0110
#define AU1000_GPIO1_CLR 0x010C
extern int au1xxx_gpio_get_value(unsigned gpio);
extern void au1xxx_gpio_set_value(unsigned gpio, int value);
extern int au1xxx_gpio_direction_input(unsigned gpio);
extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
/* GPIO bank 2 offsets */
#define AU1000_GPIO2_DIR 0x00
#define AU1000_GPIO2_RSVD 0x04
#define AU1000_GPIO2_OUT 0x08
#define AU1000_GPIO2_ST 0x0C
#define AU1000_GPIO2_INT 0x10
#define AU1000_GPIO2_EN 0x14
#define GPIO2_OUT_EN_MASK 0x00010000
/* Wrappers for the arch-neutral GPIO API */
#define gpio_to_irq(gpio) NULL
static inline int gpio_request(unsigned gpio, const char *label)
{
/* Not yet implemented */
return 0;
}
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
static inline void gpio_free(unsigned gpio)
{
/* Not yet implemented */
}
#define gpio_cansleep __gpio_cansleep
static inline int gpio_direction_input(unsigned gpio)
{
return au1xxx_gpio_direction_input(gpio);
}
static inline int gpio_direction_output(unsigned gpio, int value)
{
return au1xxx_gpio_direction_output(gpio, value);
}
static inline int gpio_get_value(unsigned gpio)
{
return au1xxx_gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
au1xxx_gpio_set_value(gpio, value);
}
static inline int gpio_to_irq(unsigned gpio)
{
return gpio;
}
static inline int irq_to_gpio(unsigned irq)
{
return irq;
}
/* For cansleep */
#include <asm-generic/gpio.h>
#endif /* _AU1XXX_GPIO_H_ */

2
arch/mips/include/asm/mips-boards/generic.h
View File

@ -71,8 +71,6 @@
#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
extern int mips_revision_corid;
#define MIPS_REVISION_SCON_OTHER 0
#define MIPS_REVISION_SCON_SOCITSC 1
#define MIPS_REVISION_SCON_SOCITSCP 2

2
arch/mips/include/asm/smp-ops.h
View File

@ -15,6 +15,8 @@
#include <linux/cpumask.h>
struct task_struct;
struct plat_smp_ops {
void (*send_ipi_single)(int cpu, unsigned int action);
void (*send_ipi_mask)(cpumask_t mask, unsigned int action);

8
arch/mips/include/asm/spinlock.h
View File

@ -76,7 +76,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
"2: \n"
" .subsection 2 \n"
"4: andi %[ticket], %[ticket], 0x1fff \n"
"5: sll %[ticket], 5 \n"
" sll %[ticket], 5 \n"
" \n"
"6: bnez %[ticket], 6b \n"
" subu %[ticket], 1 \n"
@ -85,7 +85,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
" andi %[ticket], %[ticket], 0x1fff \n"
" beq %[ticket], %[my_ticket], 2b \n"
" subu %[ticket], %[my_ticket], %[ticket] \n"
" b 5b \n"
" b 4b \n"
" subu %[ticket], %[ticket], 1 \n"
" .previous \n"
" .set pop \n"
@ -113,7 +113,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
" ll %[ticket], %[ticket_ptr] \n"
" \n"
"4: andi %[ticket], %[ticket], 0x1fff \n"
"5: sll %[ticket], 5 \n"
" sll %[ticket], 5 \n"
" \n"
"6: bnez %[ticket], 6b \n"
" subu %[ticket], 1 \n"
@ -122,7 +122,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
" andi %[ticket], %[ticket], 0x1fff \n"
" beq %[ticket], %[my_ticket], 2b \n"
" subu %[ticket], %[my_ticket], %[ticket] \n"
" b 5b \n"
" b 4b \n"
" subu %[ticket], %[ticket], 1 \n"
" .previous \n"
" .set pop \n"

8
arch/mips/include/asm/types.h
View File

@ -4,12 +4,18 @@
* for more details.
*
* Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
* Copyright (C) 2008 Wind River Systems,
* written by Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_TYPES_H
#define _ASM_TYPES_H
#if _MIPS_SZLONG == 64
/*
* We don't use int-l64.h for the kernel anymore but still use it for
* userspace to avoid code changes.
*/
#if (_MIPS_SZLONG == 64) && !defined(__KERNEL__)
# include <asm-generic/int-l64.h>
#else
# include <asm-generic/int-ll64.h>

3
arch/mips/jazz/jazzdma.c
View File

@ -68,8 +68,7 @@ static int __init vdma_init(void)
*/
pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA,
get_order(VDMA_PGTBL_SIZE));
if (!pgtbl)
BUG();
BUG_ON(!pgtbl);
dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE);
pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl);

21
arch/mips/kernel/cpu-probe.c
View File

@ -183,13 +183,7 @@ void __init check_wait(void)
case CPU_TX49XX:
cpu_wait = r4k_wait_irqoff;
break;
case CPU_AU1000:
case CPU_AU1100:
case CPU_AU1500:
case CPU_AU1550:
case CPU_AU1200:
case CPU_AU1210:
case CPU_AU1250:
case CPU_ALCHEMY:
cpu_wait = au1k_wait;
break;
case CPU_20KC:
@ -783,37 +777,30 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
switch (c->processor_id & 0xff00) {
case PRID_IMP_AU1_REV1:
case PRID_IMP_AU1_REV2:
c->cputype = CPU_ALCHEMY;
switch ((c->processor_id >> 24) & 0xff) {
case 0:
c->cputype = CPU_AU1000;
__cpu_name[cpu] = "Au1000";
break;
case 1:
c->cputype = CPU_AU1500;
__cpu_name[cpu] = "Au1500";
break;
case 2:
c->cputype = CPU_AU1100;
__cpu_name[cpu] = "Au1100";
break;
case 3:
c->cputype = CPU_AU1550;
__cpu_name[cpu] = "Au1550";
break;
case 4:
c->cputype = CPU_AU1200;
__cpu_name[cpu] = "Au1200";
if ((c->processor_id & 0xff) == 2) {
c->cputype = CPU_AU1250;
if ((c->processor_id & 0xff) == 2)
__cpu_name[cpu] = "Au1250";
}
break;
case 5:
c->cputype = CPU_AU1210;
__cpu_name[cpu] = "Au1210";
break;
default:
panic("Unknown Au Core!");
__cpu_name[cpu] = "Au1xxx";
break;
}
break;

6
arch/mips/kernel/irq-msc01.c
View File

@ -140,14 +140,16 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma
switch (imp->im_type) {
case MSC01_IRQ_EDGE:
set_irq_chip(irqbase+n, &msc_edgeirq_type);
set_irq_chip_and_handler_name(irqbase + n,
&msc_edgeirq_type, handle_edge_irq, "edge");
if (cpu_has_veic)
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
else
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
break;
case MSC01_IRQ_LEVEL:
set_irq_chip(irqbase+n, &msc_levelirq_type);
set_irq_chip_and_handler_name(irqbase+n,
&msc_levelirq_type, handle_level_irq, "level");
if (cpu_has_veic)
MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
else

3
arch/mips/kernel/irq_cpu.c
View File

@ -112,7 +112,8 @@ void __init mips_cpu_irq_init(void)
*/
if (cpu_has_mipsmt)
for (i = irq_base; i < irq_base + 2; i++)
set_irq_chip(i, &mips_mt_cpu_irq_controller);
set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
handle_percpu_irq);
for (i = irq_base + 2; i < irq_base + 8; i++)
set_irq_chip_and_handler(i, &mips_cpu_irq_controller,

6
arch/mips/kernel/linux32.c
View File

@ -133,9 +133,9 @@ SYSCALL_DEFINE4(32_ftruncate64, unsigned long, fd, unsigned long, __dummy,
return sys_ftruncate(fd, merge_64(a2, a3));
}
SYSCALL_DEFINE5(32_llseek, unsigned long, fd, unsigned long, offset_high,
unsigned long, offset_low, loff_t __user *, result,
unsigned long, origin)
SYSCALL_DEFINE5(32_llseek, unsigned int, fd, unsigned int, offset_high,
unsigned int, offset_low, loff_t __user *, result,
unsigned int, origin)
{
return sys_llseek(fd, offset_high, offset_low, result, origin);
}

3
arch/mips/kernel/setup.c
View File

@ -277,7 +277,8 @@ static void __init bootmem_init(void)
* not selected. Once that done we can determine the low bound
* of usable memory.
*/
reserved_end = max(init_initrd(), PFN_UP(__pa_symbol(&_end)));
reserved_end = max(init_initrd(),
(unsigned long) PFN_UP(__pa_symbol(&_end)));
/*
* max_low_pfn is not a number of pages. The number of pages

14
arch/mips/kernel/smp-up.c
View File

@ -13,7 +13,7 @@
/*
* Send inter-processor interrupt
*/
void up_send_ipi_single(int cpu, unsigned int action)
static void up_send_ipi_single(int cpu, unsigned int action)
{
panic(KERN_ERR "%s called", __func__);
}
@ -27,31 +27,31 @@ static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action)
* After we've done initial boot, this function is called to allow the
* board code to clean up state, if needed
*/
void __cpuinit up_init_secondary(void)
static void __cpuinit up_init_secondary(void)
{
}
void __cpuinit up_smp_finish(void)
static void __cpuinit up_smp_finish(void)
{
}
/* Hook for after all CPUs are online */
void up_cpus_done(void)
static void up_cpus_done(void)
{
}
/*
* Firmware CPU startup hook
*/
void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle)
static void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle)
{
}
void __init up_smp_setup(void)
static void __init up_smp_setup(void)
{
}
void __init up_prepare_cpus(unsigned int max_cpus)
static void __init up_prepare_cpus(unsigned int max_cpus)
{
}

2
arch/mips/kernel/smp.c
View File

@ -44,7 +44,7 @@
#include <asm/mipsmtregs.h>
#endif /* CONFIG_MIPS_MT_SMTC */
volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
static volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */

3
arch/mips/kernel/traps.c
View File

@ -1277,8 +1277,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
u32 *w;
unsigned char *b;
if (!cpu_has_veic && !cpu_has_vint)
BUG();
BUG_ON(!cpu_has_veic && !cpu_has_vint);
if (addr == NULL) {
handler = (unsigned long) do_default_vi;

17
arch/mips/mm/c-r4k.c
View File

@ -1026,13 +1026,7 @@ static void __cpuinit probe_pcache(void)
c->icache.flags |= MIPS_CACHE_VTAG;
break;
case CPU_AU1000:
case CPU_AU1500:
case CPU_AU1100:
case CPU_AU1550:
case CPU_AU1200:
case CPU_AU1210:
case CPU_AU1250:
case CPU_ALCHEMY:
c->icache.flags |= MIPS_CACHE_IC_F_DC;
break;
}
@ -1244,7 +1238,7 @@ void au1x00_fixup_config_od(void)
/*
* Au1100 errata actually keeps silence about this bit, so we set it
* just in case for those revisions that require it to be set according
* to arch/mips/au1000/common/cputable.c
* to the (now gone) cpu table.
*/
case 0x02030200: /* Au1100 AB */
case 0x02030201: /* Au1100 BA */
@ -1314,11 +1308,10 @@ static void __cpuinit coherency_setup(void)
break;
/*
* We need to catch the early Alchemy SOCs with
* the write-only co_config.od bit and set it back to one...
* the write-only co_config.od bit and set it back to one on:
* Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
*/
case CPU_AU1000: /* rev. DA, HA, HB */
case CPU_AU1100: /* rev. AB, BA, BC ?? */
case CPU_AU1500: /* rev. AB */
case CPU_ALCHEMY:
au1x00_fixup_config_od();
break;

9
arch/mips/mm/highmem.c
View File

@ -17,8 +17,7 @@ void *__kmap(struct page *page)
void __kunmap(struct page *page)
{
if (in_interrupt())
BUG();
BUG_ON(in_interrupt());
if (!PageHighMem(page))
return;
kunmap_high(page);
@ -46,8 +45,7 @@ void *__kmap_atomic(struct page *page, enum km_type type)
idx = type + KM_TYPE_NR*smp_processor_id();
vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
#ifdef CONFIG_DEBUG_HIGHMEM
if (!pte_none(*(kmap_pte-idx)))
BUG();
BUG_ON(!pte_none(*(kmap_pte - idx)));
#endif
set_pte(kmap_pte-idx, mk_pte(page, kmap_prot));
local_flush_tlb_one((unsigned long)vaddr);
@ -66,8 +64,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type)
return;
}
if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN+idx))
BUG();
BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
/*
* force other mappings to Oops if they'll try to access

3
arch/mips/mm/init.c
View File

@ -307,8 +307,7 @@ void __init fixrange_init(unsigned long start, unsigned long end,
if (pmd_none(*pmd)) {
pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
set_pmd(pmd, __pmd((unsigned long)pte));
if (pte != pte_offset_kernel(pmd, 0))
BUG();
BUG_ON(pte != pte_offset_kernel(pmd, 0));
}
vaddr += PMD_SIZE;
}

9
arch/mips/mm/ioremap.c
View File

@ -27,8 +27,7 @@ static inline void remap_area_pte(pte_t * pte, unsigned long address,
end = address + size;
if (end > PMD_SIZE)
end = PMD_SIZE;
if (address >= end)
BUG();
BUG_ON(address >= end);
pfn = phys_addr >> PAGE_SHIFT;
do {
if (!pte_none(*pte)) {
@ -52,8 +51,7 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address,
if (end > PGDIR_SIZE)
end = PGDIR_SIZE;
phys_addr -= address;
if (address >= end)
BUG();
BUG_ON(address >= end);
do {
pte_t * pte = pte_alloc_kernel(pmd, address);
if (!pte)
@ -75,8 +73,7 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr,
phys_addr -= address;
dir = pgd_offset(&init_mm, address);
flush_cache_all();
if (address >= end)
BUG();
BUG_ON(address >= end);
do {
pud_t *pud;
pmd_t *pmd;

8
arch/mips/mm/tlbex.c
View File

@ -292,13 +292,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_R4300:
case CPU_5KC:
case CPU_TX49XX:
case CPU_AU1000:
case CPU_AU1100:
case CPU_AU1500:
case CPU_AU1550:
case CPU_AU1200:
case CPU_AU1210:
case CPU_AU1250:
case CPU_PR4450:
uasm_i_nop(p);
tlbw(p);
@ -321,6 +314,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_R5500:
if (m4kc_tlbp_war())
uasm_i_nop(p);
case CPU_ALCHEMY:
tlbw(p);
break;

2
arch/mips/mti-malta/malta-init.c
View File

@ -48,7 +48,7 @@ int *_prom_argv, *_prom_envp;
int init_debug = 0;
int mips_revision_corid;
static int mips_revision_corid;
int mips_revision_sconid;
/* Bonito64 system controller register base. */

2
arch/mips/sgi-ip27/ip27-berr.c
View File

@ -66,7 +66,7 @@ int ip27_be_handler(struct pt_regs *regs, int is_fixup)
printk("Slice %c got %cbe at 0x%lx\n", 'A' + cpu, data ? 'd' : 'i',
regs->cp0_epc);
printk("Hub information:\n");
printk("ERR_INT_PEND = 0x%06lx\n", LOCAL_HUB_L(PI_ERR_INT_PEND));
printk("ERR_INT_PEND = 0x%06llx\n", LOCAL_HUB_L(PI_ERR_INT_PEND));
errst0 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS0_B : PI_ERR_STATUS0_A);
errst1 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS1_B : PI_ERR_STATUS1_A);
dump_hub_information(errst0, errst1);

4
arch/mips/sgi-ip27/ip27-nmi.c
View File

@ -143,8 +143,8 @@ void nmi_dump_hub_irq(nasid_t nasid, int slice)
pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);
printk("PI_INT_MASK0: %16lx PI_INT_MASK1: %16lx\n", mask0, mask1);
printk("PI_INT_PEND0: %16lx PI_INT_PEND1: %16lx\n", pend0, pend1);
printk("PI_INT_MASK0: %16Lx PI_INT_MASK1: %16Lx\n", mask0, mask1);
printk("PI_INT_PEND0: %16Lx PI_INT_PEND1: %16Lx\n", pend0, pend1);
printk("\n\n");
}

63
arch/mips/sgi-ip32/ip32-irq.c
View File

@ -325,16 +325,11 @@ static void mask_and_ack_maceisa_irq(unsigned int irq)
{
unsigned long mace_int;
switch (irq) {
case MACEISA_PARALLEL_IRQ:
case MACEISA_SERIAL1_TDMAPR_IRQ:
case MACEISA_SERIAL2_TDMAPR_IRQ:
/* edge triggered */
mace_int = mace->perif.ctrl.istat;
mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
mace->perif.ctrl.istat = mace_int;
break;
}
/* edge triggered */
mace_int = mace->perif.ctrl.istat;
mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
mace->perif.ctrl.istat = mace_int;
disable_maceisa_irq(irq);
}
@ -344,7 +339,16 @@ static void end_maceisa_irq(unsigned irq)
enable_maceisa_irq(irq);
}
static struct irq_chip ip32_maceisa_interrupt = {
static struct irq_chip ip32_maceisa_level_interrupt = {
.name = "IP32 MACE ISA",
.ack = disable_maceisa_irq,
.mask = disable_maceisa_irq,
.mask_ack = disable_maceisa_irq,
.unmask = enable_maceisa_irq,
.end = end_maceisa_irq,
};
static struct irq_chip ip32_maceisa_edge_interrupt = {
.name = "IP32 MACE ISA",
.ack = mask_and_ack_maceisa_irq,
.mask = disable_maceisa_irq,
@ -500,27 +504,50 @@ void __init arch_init_irq(void)
for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
switch (irq) {
case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
set_irq_chip(irq, &ip32_mace_interrupt);
set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
handle_level_irq, "level");
break;
case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
set_irq_chip(irq, &ip32_macepci_interrupt);
set_irq_chip_and_handler_name(irq,
&ip32_macepci_interrupt, handle_level_irq,
"level");
break;
case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
set_irq_chip(irq, &crime_edge_interrupt);
set_irq_chip_and_handler_name(irq,
&crime_edge_interrupt, handle_edge_irq, "edge");
break;
case CRIME_CPUERR_IRQ:
case CRIME_MEMERR_IRQ:
set_irq_chip(irq, &crime_level_interrupt);
set_irq_chip_and_handler_name(irq,
&crime_level_interrupt, handle_level_irq,
"level");
break;
case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
set_irq_chip(irq, &crime_edge_interrupt);
set_irq_chip_and_handler_name(irq,
&crime_edge_interrupt, handle_edge_irq, "edge");
break;
case CRIME_VICE_IRQ:
set_irq_chip(irq, &crime_edge_interrupt);
set_irq_chip_and_handler_name(irq,
&crime_edge_interrupt, handle_edge_irq, "edge");
break;
case MACEISA_PARALLEL_IRQ:
case MACEISA_SERIAL1_TDMAPR_IRQ:
case MACEISA_SERIAL2_TDMAPR_IRQ:
set_irq_chip_and_handler_name(irq,
&ip32_maceisa_edge_interrupt, handle_edge_irq,
"edge");
break;
default:
set_irq_chip(irq, &ip32_maceisa_interrupt);
set_irq_chip_and_handler_name(irq,
&ip32_maceisa_level_interrupt, handle_level_irq,
"level");
break;
}
}

2
arch/mips/sgi-ip32/ip32-memory.c
View File

@ -36,7 +36,7 @@ void __init prom_meminit(void)
if (base + size > (256 << 20))
base += CRIME_HI_MEM_BASE;
printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n",
printk("CRIME MC: bank %u base 0x%016Lx size %LuMiB\n",
bank, base, size >> 20);
add_memory_region(base, size, BOOT_MEM_RAM);
}

2
arch/mips/sibyte/bcm1480/irq.c
View File

@ -236,7 +236,7 @@ void __init init_bcm1480_irqs(void)
int i;
for (i = 0; i < BCM1480_NR_IRQS; i++) {
set_irq_chip(i, &bcm1480_irq_type);
set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
bcm1480_irq_owner[i] = 0;
}
}

2
arch/mips/sibyte/sb1250/irq.c
View File

@ -220,7 +220,7 @@ void __init init_sb1250_irqs(void)
int i;
for (i = 0; i < SB1250_NR_IRQS; i++) {
set_irq_chip(i, &sb1250_irq_type);
set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
sb1250_irq_owner[i] = 0;
}
}

2
arch/mips/sni/a20r.c
View File

@ -219,7 +219,7 @@ void __init sni_a20r_irq_init(void)
int i;
for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
set_irq_chip(i, &a20r_irq_type);
set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
sni_hwint = a20r_hwint;
change_c0_status(ST0_IM, IE_IRQ0);
setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);

2
arch/mips/sni/pcimt.c
View File

@ -304,7 +304,7 @@ void __init sni_pcimt_irq_init(void)
mips_cpu_irq_init();
/* Actually we've got more interrupts to handle ... */
for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
set_irq_chip(i, &pcimt_irq_type);
set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq);
sni_hwint = sni_pcimt_hwint;
change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
}

4
arch/mips/sni/pcit.c
View File

@ -246,7 +246,7 @@ void __init sni_pcit_irq_init(void)
mips_cpu_irq_init();
for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
set_irq_chip(i, &pcit_irq_type);
set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
*(volatile u32 *)SNI_PCIT_INT_REG = 0;
sni_hwint = sni_pcit_hwint;
change_c0_status(ST0_IM, IE_IRQ1);
@ -259,7 +259,7 @@ void __init sni_pcit_cplus_irq_init(void)
mips_cpu_irq_init();
for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
set_irq_chip(i, &pcit_irq_type);
set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
sni_hwint = sni_pcit_hwint_cplus;
change_c0_status(ST0_IM, IE_IRQ0);

2
arch/mips/sni/rm200.c
View File

@ -487,7 +487,7 @@ void __init sni_rm200_irq_init(void)
mips_cpu_irq_init();
/* Actually we've got more interrupts to handle ... */
for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
set_irq_chip(i, &rm200_irq_type);
set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
sni_hwint = sni_rm200_hwint;
change_c0_status(ST0_IM, IE_IRQ0);
setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);

1
arch/mips/txx9/Kconfig
View File

@ -20,7 +20,6 @@ config MACH_TXX9
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
config TOSHIBA_JMR3927
bool "Toshiba JMR-TX3927 board"

2
drivers/net/meth.c
View File

@ -398,7 +398,7 @@ static void meth_rx(struct net_device* dev, unsigned long int_status)
int len = (status & 0xffff) - 4; /* omit CRC */
/* length sanity check */
if (len < 60 || len > 1518) {
printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2lx.\n",
printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2Lx.\n",
dev->name, priv->rx_write,
priv->rx_ring[priv->rx_write]->status.raw);
dev->stats.rx_errors++;

32
drivers/net/smc91x.h
View File

@ -346,38 +346,6 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
#define RPC_LSA_DEFAULT RPC_LED_TX_RX
#define RPC_LSB_DEFAULT RPC_LED_100_10
#elif defined(CONFIG_SOC_AU1X00)
#include <au1xxx.h>
/* We can only do 16-bit reads and writes in the static memory space. */
#define SMC_CAN_USE_8BIT 0
#define SMC_CAN_USE_16BIT 1
#define SMC_CAN_USE_32BIT 0
#define SMC_IO_SHIFT 0
#define SMC_NOWAIT 1
#define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
#define SMC_insw(a, r, p, l) \
do { \
unsigned long _a = (unsigned long)((a) + (r)); \
int _l = (l); \
u16 *_p = (u16 *)(p); \
while (_l-- > 0) \
*_p++ = au_readw(_a); \
} while(0)
#define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
#define SMC_outsw(a, r, p, l) \
do { \
unsigned long _a = (unsigned long)((a) + (r)); \
int _l = (l); \
const u16 *_p = (const u16 *)(p); \
while (_l-- > 0) \
au_writew(*_p++ , _a); \
} while(0)
#define SMC_IRQ_FLAGS (0)
#elif defined(CONFIG_ARCH_VERSATILE)
#define SMC_CAN_USE_8BIT 1