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Merge branch 'pci/ctrl/brcmstb'
- Remove unnecessary forward declarations (Jim Quinlan) - Prevent config space access when link is down (Jim Quinlan) - Split post-link up initialization to brcm_pcie_start_link() (Jim Quinlan) - Enable child bus device regulators described under Root Ports in DT (Jim Quinlan) - Disable/enable regulators in suspend/resume (Jim Quinlan) - Rename .map_bus() functions to end with 'map_bus' as they do in other drivers (Jim Quinlan) * pci/ctrl/brcmstb: PCI: brcmstb: Rename .map_bus() functions to end with 'map_bus' PCI: brcmstb: Disable/enable regulators in suspend/resume PCI: brcmstb: Enable child bus device regulators from DT PCI: brcmstb: Split post-link up initialization to brcm_pcie_start_link() PCI: brcmstb: Prevent config space access when link is down PCI: brcmstb: Remove unnecessary forward declarations
This commit is contained in:
Bjorn Helgaas
commit
9154b00f51
@ -24,6 +24,7 @@
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#include <linux/pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/printk.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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@ -190,11 +191,6 @@
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/* Forward declarations */
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struct brcm_pcie;
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static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
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static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
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static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val);
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static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
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static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
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enum {
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RGR1_SW_INIT_1,
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@ -223,64 +219,9 @@ struct pcie_cfg_data {
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void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
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};
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static const int pcie_offsets[] = {
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[RGR1_SW_INIT_1] = 0x9210,
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[EXT_CFG_INDEX] = 0x9000,
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[EXT_CFG_DATA] = 0x9004,
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};
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static const int pcie_offsets_bmips_7425[] = {
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[RGR1_SW_INIT_1] = 0x8010,
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[EXT_CFG_INDEX] = 0x8300,
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[EXT_CFG_DATA] = 0x8304,
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};
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static const struct pcie_cfg_data generic_cfg = {
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.offsets = pcie_offsets,
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.type = GENERIC,
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.perst_set = brcm_pcie_perst_set_generic,
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.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
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};
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static const struct pcie_cfg_data bcm7425_cfg = {
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.offsets = pcie_offsets_bmips_7425,
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.type = BCM7425,
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.perst_set = brcm_pcie_perst_set_generic,
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.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
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};
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static const struct pcie_cfg_data bcm7435_cfg = {
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.offsets = pcie_offsets,
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.type = BCM7435,
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.perst_set = brcm_pcie_perst_set_generic,
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.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
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};
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static const struct pcie_cfg_data bcm4908_cfg = {
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.offsets = pcie_offsets,
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.type = BCM4908,
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.perst_set = brcm_pcie_perst_set_4908,
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.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
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};
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static const int pcie_offset_bcm7278[] = {
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[RGR1_SW_INIT_1] = 0xc010,
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[EXT_CFG_INDEX] = 0x9000,
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[EXT_CFG_DATA] = 0x9004,
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};
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static const struct pcie_cfg_data bcm7278_cfg = {
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.offsets = pcie_offset_bcm7278,
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.type = BCM7278,
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.perst_set = brcm_pcie_perst_set_7278,
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.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
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};
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static const struct pcie_cfg_data bcm2711_cfg = {
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.offsets = pcie_offsets,
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.type = BCM2711,
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.perst_set = brcm_pcie_perst_set_generic,
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.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
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struct subdev_regulators {
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unsigned int num_supplies;
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struct regulator_bulk_data supplies[];
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};
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struct brcm_msi {
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@ -320,6 +261,8 @@ struct brcm_pcie {
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u32 hw_rev;
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void (*perst_set)(struct brcm_pcie *pcie, u32 val);
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void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
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struct subdev_regulators *sr;
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bool ep_wakeup_capable;
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};
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static inline bool is_bmips(const struct brcm_pcie *pcie)
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@ -741,52 +684,48 @@ static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
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return dla && plu;
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}
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static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
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int where)
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static void __iomem *brcm_pcie_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct brcm_pcie *pcie = bus->sysdata;
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void __iomem *base = pcie->base;
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int idx;
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/* Accesses to the RC go right to the RC registers if slot==0 */
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/* Accesses to the RC go right to the RC registers if !devfn */
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if (pci_is_root_bus(bus))
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return PCI_SLOT(devfn) ? NULL : base + where;
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return devfn ? NULL : base + PCIE_ECAM_REG(where);
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/* An access to our HW w/o link-up will cause a CPU Abort */
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if (!brcm_pcie_link_up(pcie))
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return NULL;
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/* For devices, write to the config space index register */
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idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
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writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
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return base + PCIE_EXT_CFG_DATA + where;
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return base + PCIE_EXT_CFG_DATA + PCIE_ECAM_REG(where);
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}
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static void __iomem *brcm_pcie_map_conf32(struct pci_bus *bus, unsigned int devfn,
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int where)
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static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct brcm_pcie *pcie = bus->sysdata;
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void __iomem *base = pcie->base;
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int idx;
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/* Accesses to the RC go right to the RC registers if slot==0 */
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/* Accesses to the RC go right to the RC registers if !devfn */
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if (pci_is_root_bus(bus))
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return PCI_SLOT(devfn) ? NULL : base + (where & ~0x3);
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return devfn ? NULL : base + PCIE_ECAM_REG(where);
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/* An access to our HW w/o link-up will cause a CPU Abort */
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if (!brcm_pcie_link_up(pcie))
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return NULL;
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/* For devices, write to the config space index register */
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idx = PCIE_ECAM_OFFSET(bus->number, devfn, (where & ~3));
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idx = PCIE_ECAM_OFFSET(bus->number, devfn, where);
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writel(idx, base + IDX_ADDR(pcie));
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return base + DATA_ADDR(pcie);
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}
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static struct pci_ops brcm_pcie_ops = {
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.map_bus = brcm_pcie_map_conf,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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static struct pci_ops brcm_pcie_ops32 = {
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.map_bus = brcm_pcie_map_conf32,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write32,
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};
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static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
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{
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u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
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@ -926,17 +865,13 @@ static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
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static int brcm_pcie_setup(struct brcm_pcie *pcie)
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{
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
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u64 rc_bar2_offset, rc_bar2_size;
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void __iomem *base = pcie->base;
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struct device *dev = pcie->dev;
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struct pci_host_bridge *bridge;
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struct resource_entry *entry;
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bool ssc_good = false;
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struct resource *res;
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int num_out_wins = 0;
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u16 nlw, cls, lnksta;
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int i, ret, memc;
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u32 tmp, burst, aspm_support;
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int num_out_wins = 0;
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int ret, memc;
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/* Reset the bridge */
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pcie->bridge_sw_init_set(pcie, 1);
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@ -1012,6 +947,11 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
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else
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pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
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if (!brcm_pcie_rc_mode(pcie)) {
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dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n");
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return -EINVAL;
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}
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/* disable the PCIe->GISB memory window (RC_BAR1) */
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tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);
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tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
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@ -1022,31 +962,27 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
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tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK;
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writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO);
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if (pcie->gen)
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brcm_pcie_set_gen(pcie, pcie->gen);
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/* Unassert the fundamental reset */
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pcie->perst_set(pcie, 0);
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/* Don't advertise L0s capability if 'aspm-no-l0s' */
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aspm_support = PCIE_LINK_STATE_L1;
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if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
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aspm_support |= PCIE_LINK_STATE_L0S;
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tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
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u32p_replace_bits(&tmp, aspm_support,
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PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
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writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
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/*
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* Give the RC/EP time to wake up, before trying to configure RC.
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* Intermittently check status for link-up, up to a total of 100ms.
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* For config space accesses on the RC, show the right class for
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* a PCIe-PCIe bridge (the default setting is to be EP mode).
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*/
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for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
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msleep(5);
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if (!brcm_pcie_link_up(pcie)) {
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dev_err(dev, "link down\n");
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return -ENODEV;
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}
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if (!brcm_pcie_rc_mode(pcie)) {
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dev_err(dev, "PCIe misconfigured; is in EP mode\n");
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return -EINVAL;
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}
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tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
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u32p_replace_bits(&tmp, 0x060400,
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PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
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writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
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bridge = pci_host_bridge_from_priv(pcie);
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resource_list_for_each_entry(entry, &bridge->windows) {
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res = entry->res;
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struct resource *res = entry->res;
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if (resource_type(res) != IORESOURCE_MEM)
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continue;
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@ -1075,23 +1011,41 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
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num_out_wins++;
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}
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/* Don't advertise L0s capability if 'aspm-no-l0s' */
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aspm_support = PCIE_LINK_STATE_L1;
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if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
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aspm_support |= PCIE_LINK_STATE_L0S;
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tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
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u32p_replace_bits(&tmp, aspm_support,
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PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
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writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
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/* PCIe->SCB endian mode for BAR */
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tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
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u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
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PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
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writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
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return 0;
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}
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static int brcm_pcie_start_link(struct brcm_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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void __iomem *base = pcie->base;
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u16 nlw, cls, lnksta;
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bool ssc_good = false;
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u32 tmp;
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int ret, i;
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/* Unassert the fundamental reset */
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pcie->perst_set(pcie, 0);
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/*
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* For config space accesses on the RC, show the right class for
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* a PCIe-PCIe bridge (the default setting is to be EP mode).
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* Give the RC/EP time to wake up, before trying to configure RC.
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* Intermittently check status for link-up, up to a total of 100ms.
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*/
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tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
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u32p_replace_bits(&tmp, 0x060400,
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PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
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writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
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for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
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msleep(5);
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if (!brcm_pcie_link_up(pcie)) {
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dev_err(dev, "link down\n");
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return -ENODEV;
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}
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if (pcie->gen)
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brcm_pcie_set_gen(pcie, pcie->gen);
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if (pcie->ssc) {
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ret = brcm_pcie_set_ssc(pcie);
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@ -1108,12 +1062,6 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
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pci_speed_string(pcie_link_speed[cls]), nlw,
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ssc_good ? "(SSC)" : "(!SSC)");
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/* PCIe->SCB endian mode for BAR */
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tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
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u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
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PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
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writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
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/*
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* Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
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* is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
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@ -1125,6 +1073,82 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
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return 0;
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}
|
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static const char * const supplies[] = {
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"vpcie3v3",
|
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"vpcie3v3aux",
|
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"vpcie12v",
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};
|
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|
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static void *alloc_subdev_regulators(struct device *dev)
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{
|
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const size_t size = sizeof(struct subdev_regulators) +
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sizeof(struct regulator_bulk_data) * ARRAY_SIZE(supplies);
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struct subdev_regulators *sr;
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int i;
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sr = devm_kzalloc(dev, size, GFP_KERNEL);
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if (sr) {
|
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sr->num_supplies = ARRAY_SIZE(supplies);
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for (i = 0; i < ARRAY_SIZE(supplies); i++)
|
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sr->supplies[i].supply = supplies[i];
|
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}
|
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|
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return sr;
|
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}
|
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|
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static int brcm_pcie_add_bus(struct pci_bus *bus)
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{
|
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struct brcm_pcie *pcie = bus->sysdata;
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struct device *dev = &bus->dev;
|
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struct subdev_regulators *sr;
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int ret;
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|
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if (!bus->parent || !pci_is_root_bus(bus->parent))
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return 0;
|
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|
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if (dev->of_node) {
|
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sr = alloc_subdev_regulators(dev);
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if (!sr) {
|
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dev_info(dev, "Can't allocate regulators for downstream device\n");
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goto no_regulators;
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}
|
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|
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pcie->sr = sr;
|
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|
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ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies);
|
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if (ret) {
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dev_info(dev, "No regulators for downstream device\n");
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goto no_regulators;
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}
|
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|
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ret = regulator_bulk_enable(sr->num_supplies, sr->supplies);
|
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if (ret) {
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dev_err(dev, "Can't enable regulators for downstream device\n");
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regulator_bulk_free(sr->num_supplies, sr->supplies);
|
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pcie->sr = NULL;
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}
|
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}
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no_regulators:
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brcm_pcie_start_link(pcie);
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return 0;
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}
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|
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static void brcm_pcie_remove_bus(struct pci_bus *bus)
|
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{
|
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struct brcm_pcie *pcie = bus->sysdata;
|
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struct subdev_regulators *sr = pcie->sr;
|
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struct device *dev = &bus->dev;
|
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|
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if (!sr)
|
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return;
|
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if (regulator_bulk_disable(sr->num_supplies, sr->supplies))
|
||||
dev_err(dev, "Failed to disable regulators for downstream device\n");
|
||||
regulator_bulk_free(sr->num_supplies, sr->supplies);
|
||||
pcie->sr = NULL;
|
||||
}
|
||||
|
||||
/* L23 is a low-power PCIe link state */
|
||||
static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
|
||||
{
|
||||
@ -1221,9 +1245,21 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
|
||||
pcie->bridge_sw_init_set(pcie, 1);
|
||||
}
|
||||
|
||||
static int brcm_pcie_suspend(struct device *dev)
|
||||
static int pci_dev_may_wakeup(struct pci_dev *dev, void *data)
|
||||
{
|
||||
bool *ret = data;
|
||||
|
||||
if (device_may_wakeup(&dev->dev)) {
|
||||
*ret = true;
|
||||
dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n");
|
||||
}
|
||||
return (int) *ret;
|
||||
}
|
||||
|
||||
static int brcm_pcie_suspend_noirq(struct device *dev)
|
||||
{
|
||||
struct brcm_pcie *pcie = dev_get_drvdata(dev);
|
||||
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
|
||||
int ret;
|
||||
|
||||
brcm_pcie_turn_off(pcie);
|
||||
@ -1241,12 +1277,31 @@ static int brcm_pcie_suspend(struct device *dev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (pcie->sr) {
|
||||
/*
|
||||
* Now turn off the regulators, but if at least one
|
||||
* downstream device is enabled as a wake-up source, do not
|
||||
* turn off regulators.
|
||||
*/
|
||||
pcie->ep_wakeup_capable = false;
|
||||
pci_walk_bus(bridge->bus, pci_dev_may_wakeup,
|
||||
&pcie->ep_wakeup_capable);
|
||||
if (!pcie->ep_wakeup_capable) {
|
||||
ret = regulator_bulk_disable(pcie->sr->num_supplies,
|
||||
pcie->sr->supplies);
|
||||
if (ret) {
|
||||
dev_err(dev, "Could not turn off regulators\n");
|
||||
reset_control_reset(pcie->rescal);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
clk_disable_unprepare(pcie->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int brcm_pcie_resume(struct device *dev)
|
||||
static int brcm_pcie_resume_noirq(struct device *dev)
|
||||
{
|
||||
struct brcm_pcie *pcie = dev_get_drvdata(dev);
|
||||
void __iomem *base;
|
||||
@ -1281,11 +1336,37 @@ static int brcm_pcie_resume(struct device *dev)
|
||||
if (ret)
|
||||
goto err_reset;
|
||||
|
||||
if (pcie->sr) {
|
||||
if (pcie->ep_wakeup_capable) {
|
||||
/*
|
||||
* We are resuming from a suspend. In the suspend we
|
||||
* did not disable the power supplies, so there is
|
||||
* no need to enable them (and falsely increase their
|
||||
* usage count).
|
||||
*/
|
||||
pcie->ep_wakeup_capable = false;
|
||||
} else {
|
||||
ret = regulator_bulk_enable(pcie->sr->num_supplies,
|
||||
pcie->sr->supplies);
|
||||
if (ret) {
|
||||
dev_err(dev, "Could not turn on regulators\n");
|
||||
goto err_reset;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ret = brcm_pcie_start_link(pcie);
|
||||
if (ret)
|
||||
goto err_regulator;
|
||||
|
||||
if (pcie->msi)
|
||||
brcm_msi_set_regs(pcie->msi);
|
||||
|
||||
return 0;
|
||||
|
||||
err_regulator:
|
||||
if (pcie->sr)
|
||||
regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
|
||||
err_reset:
|
||||
reset_control_rearm(pcie->rescal);
|
||||
err_disable_clk:
|
||||
@ -1316,6 +1397,66 @@ static int brcm_pcie_remove(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const int pcie_offsets[] = {
|
||||
[RGR1_SW_INIT_1] = 0x9210,
|
||||
[EXT_CFG_INDEX] = 0x9000,
|
||||
[EXT_CFG_DATA] = 0x9004,
|
||||
};
|
||||
|
||||
static const int pcie_offsets_bmips_7425[] = {
|
||||
[RGR1_SW_INIT_1] = 0x8010,
|
||||
[EXT_CFG_INDEX] = 0x8300,
|
||||
[EXT_CFG_DATA] = 0x8304,
|
||||
};
|
||||
|
||||
static const struct pcie_cfg_data generic_cfg = {
|
||||
.offsets = pcie_offsets,
|
||||
.type = GENERIC,
|
||||
.perst_set = brcm_pcie_perst_set_generic,
|
||||
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
|
||||
};
|
||||
|
||||
static const struct pcie_cfg_data bcm7425_cfg = {
|
||||
.offsets = pcie_offsets_bmips_7425,
|
||||
.type = BCM7425,
|
||||
.perst_set = brcm_pcie_perst_set_generic,
|
||||
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
|
||||
};
|
||||
|
||||
static const struct pcie_cfg_data bcm7435_cfg = {
|
||||
.offsets = pcie_offsets,
|
||||
.type = BCM7435,
|
||||
.perst_set = brcm_pcie_perst_set_generic,
|
||||
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
|
||||
};
|
||||
|
||||
static const struct pcie_cfg_data bcm4908_cfg = {
|
||||
.offsets = pcie_offsets,
|
||||
.type = BCM4908,
|
||||
.perst_set = brcm_pcie_perst_set_4908,
|
||||
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
|
||||
};
|
||||
|
||||
static const int pcie_offset_bcm7278[] = {
|
||||
[RGR1_SW_INIT_1] = 0xc010,
|
||||
[EXT_CFG_INDEX] = 0x9000,
|
||||
[EXT_CFG_DATA] = 0x9004,
|
||||
};
|
||||
|
||||
static const struct pcie_cfg_data bcm7278_cfg = {
|
||||
.offsets = pcie_offset_bcm7278,
|
||||
.type = BCM7278,
|
||||
.perst_set = brcm_pcie_perst_set_7278,
|
||||
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
|
||||
};
|
||||
|
||||
static const struct pcie_cfg_data bcm2711_cfg = {
|
||||
.offsets = pcie_offsets,
|
||||
.type = BCM2711,
|
||||
.perst_set = brcm_pcie_perst_set_generic,
|
||||
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
|
||||
};
|
||||
|
||||
static const struct of_device_id brcm_pcie_match[] = {
|
||||
{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
|
||||
{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
|
||||
@ -1328,6 +1469,22 @@ static const struct of_device_id brcm_pcie_match[] = {
|
||||
{},
|
||||
};
|
||||
|
||||
static struct pci_ops brcm_pcie_ops = {
|
||||
.map_bus = brcm_pcie_map_bus,
|
||||
.read = pci_generic_config_read,
|
||||
.write = pci_generic_config_write,
|
||||
.add_bus = brcm_pcie_add_bus,
|
||||
.remove_bus = brcm_pcie_remove_bus,
|
||||
};
|
||||
|
||||
static struct pci_ops brcm7425_pcie_ops = {
|
||||
.map_bus = brcm7425_pcie_map_bus,
|
||||
.read = pci_generic_config_read32,
|
||||
.write = pci_generic_config_write32,
|
||||
.add_bus = brcm_pcie_add_bus,
|
||||
.remove_bus = brcm_pcie_remove_bus,
|
||||
};
|
||||
|
||||
static int brcm_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node, *msi_np;
|
||||
@ -1414,12 +1571,22 @@ static int brcm_pcie_probe(struct platform_device *pdev)
|
||||
}
|
||||
}
|
||||
|
||||
bridge->ops = pcie->type == BCM7425 ? &brcm_pcie_ops32 : &brcm_pcie_ops;
|
||||
bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops;
|
||||
bridge->sysdata = pcie;
|
||||
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
return pci_host_probe(bridge);
|
||||
ret = pci_host_probe(bridge);
|
||||
if (!ret && !brcm_pcie_link_up(pcie))
|
||||
ret = -ENODEV;
|
||||
|
||||
if (ret) {
|
||||
brcm_pcie_remove(pdev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
__brcm_pcie_remove(pcie);
|
||||
return ret;
|
||||
@ -1428,8 +1595,8 @@ fail:
|
||||
MODULE_DEVICE_TABLE(of, brcm_pcie_match);
|
||||
|
||||
static const struct dev_pm_ops brcm_pcie_pm_ops = {
|
||||
.suspend = brcm_pcie_suspend,
|
||||
.resume = brcm_pcie_resume,
|
||||
.suspend_noirq = brcm_pcie_suspend_noirq,
|
||||
.resume_noirq = brcm_pcie_resume_noirq,
|
||||
};
|
||||
|
||||
static struct platform_driver brcm_pcie_driver = {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user