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drm/i915/uc: Reserve upper range of GGTT

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GuC and HuC depend on struct_mutex for device reinitialization. Moving
away from this dependency requires perma-pinning the firmware images in
GGTT.  The upper portion of the GuC address space has a sizeable hole
(several MB) that is inaccessible by GuC. Reserve this range within GGTT
as it can comfortably hold GuC/HuC firmware images.

v2: Reserve node rather than insert (Chris)
    Simpler determination of node start/size (Daniele)
    Move reserve/release out to intel_guc.* files

v3: Reserve starting at GUC_GGTT_TOP only and bail if this
    fails (Chris)

Signed-off-by: Fernando Pacheco <fernando.pacheco@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190419230015.18121-3-fernando.pacheco@intel.com
This commit is contained in:
Fernando Pacheco 2019-04-19 16:00:12 -07:00 committed by Chris Wilson
parent 95ebcda3ef
commit 911800765e
4 changed files with 42 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/gpu/drm/i915/i915_gem_gtt.c
View File

@ -2752,6 +2752,12 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
if (ret)
return ret;
if (USES_GUC(dev_priv)) {
ret = intel_guc_reserve_ggtt_top(&dev_priv->guc);
if (ret)
goto err_reserve;
}
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
@ -2766,12 +2772,14 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
ret = i915_gem_init_aliasing_ppgtt(dev_priv);
if (ret)
goto err;
goto err_appgtt;
}
return 0;
err:
err_appgtt:
intel_guc_release_ggtt_top(&dev_priv->guc);
err_reserve:
drm_mm_remove_node(&ggtt->error_capture);
return ret;
}
@ -2797,6 +2805,8 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
if (drm_mm_node_allocated(&ggtt->error_capture))
drm_mm_remove_node(&ggtt->error_capture);
intel_guc_release_ggtt_top(&dev_priv->guc);
if (drm_mm_initialized(&ggtt->vm.mm)) {
intel_vgt_deballoon(dev_priv);
i915_address_space_fini(&ggtt->vm);
@ -3371,17 +3381,6 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
if (ret)
return ret;
/* Trim the GGTT to fit the GuC mappable upper range (when enabled).
* This is easier than doing range restriction on the fly, as we
* currently don't have any bits spare to pass in this upper
* restriction!
*/
if (USES_GUC(dev_priv)) {
ggtt->vm.total = min_t(u64, ggtt->vm.total, GUC_GGTT_TOP);
ggtt->mappable_end =
min_t(u64, ggtt->mappable_end, ggtt->vm.total);
}
if ((ggtt->vm.total - 1) >> 32) {
DRM_ERROR("We never expected a Global GTT with more than 32bits"
" of address space! Found %lldM!\n",

1
drivers/gpu/drm/i915/i915_gem_gtt.h
View File

@ -384,6 +384,7 @@ struct i915_ggtt {
u32 pin_bias;
struct drm_mm_node error_capture;
struct drm_mm_node uc_fw;
};
struct i915_hw_ppgtt {

27
drivers/gpu/drm/i915/intel_guc.c
View File

@ -721,3 +721,30 @@ u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
{
return guc_to_i915(guc)->wopcm.guc.size;
}
int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
{
struct drm_i915_private *i915 = guc_to_i915(guc);
struct i915_ggtt *ggtt = &i915->ggtt;
u64 size;
int ret;
size = ggtt->vm.total - GUC_GGTT_TOP;
ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
PIN_NOEVICT);
if (ret)
DRM_DEBUG_DRIVER("GuC: failed to reserve top of ggtt\n");
return ret;
}
void intel_guc_release_ggtt_top(struct intel_guc *guc)
{
struct drm_i915_private *i915 = guc_to_i915(guc);
struct i915_ggtt *ggtt = &i915->ggtt;
if (drm_mm_node_allocated(&ggtt->uc_fw))
drm_mm_remove_node(&ggtt->uc_fw);
}

2
drivers/gpu/drm/i915/intel_guc.h
View File

@ -173,6 +173,8 @@ int intel_guc_suspend(struct intel_guc *guc);
int intel_guc_resume(struct intel_guc *guc);
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
int intel_guc_reserve_ggtt_top(struct intel_guc *guc);
void intel_guc_release_ggtt_top(struct intel_guc *guc);
static inline int intel_guc_sanitize(struct intel_guc *guc)
{