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drm/amd/pm: fix gpu reset failure by MP1 state setting

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Instead of blocking varied unsupported MP1 state in upper level,
defer and skip such MP1 state handling in specific ASIC.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Guchun Chen 2021-03-23 13:41:00 +08:00 committed by Alex Deucher
parent c93ebea0cb
commit 9113a0fb61
2 changed files with 7 additions and 6 deletions
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3
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
View File

@ -1027,9 +1027,6 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
int ret = 0;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
if (mp1_state == PP_MP1_STATE_NONE)
return 0;
if (pp_funcs && pp_funcs->set_mp1_state) {
ret = pp_funcs->set_mp1_state(
adev->powerplay.pp_handle,

10
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
View File

@ -3113,14 +3113,18 @@ static int sienna_cichlid_system_features_control(struct smu_context *smu,
static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
enum pp_mp1_state mp1_state)
{
int ret;
switch (mp1_state) {
case PP_MP1_STATE_UNLOAD:
return smu_cmn_set_mp1_state(smu, mp1_state);
ret = smu_cmn_set_mp1_state(smu, mp1_state);
break;
default:
return -EINVAL;
/* Ignore others */
ret = 0;
}
return 0;
return ret;
}
static const struct pptable_funcs sienna_cichlid_ppt_funcs = {