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perf/x86/amd/uncore: Rename cpufeatures macro for cache counters
In Family 17h, L3 is the last level cache as opposed to L2 in previous families. Avoid this name confusion and rename X86_FEATURE_PERFCTR_L2 to X86_FEATURE_PERFCTR_LLC to indicate the performance counter on the last level of cache. Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/016311029fdecdc3fdc13b7ed865c6cbf48b2f15.1497452002.git.Janakarajan.Natarajan@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -555,7 +555,7 @@ static int __init amd_uncore_init(void)
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ret = 0;
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}
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if (boot_cpu_has(X86_FEATURE_PERFCTR_L2)) {
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if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) {
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amd_uncore_llc = alloc_percpu(struct amd_uncore *);
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if (!amd_uncore_llc) {
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ret = -ENOMEM;
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@ -177,7 +177,7 @@
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#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
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#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
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#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */
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#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */
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#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */
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#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */
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/*
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