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drm/i915: Re-order the PCU opcodes
Let's keep that list sorted! Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -6644,15 +6644,15 @@ enum skl_disp_power_wells {
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#define GEN6_PCODE_MAILBOX 0x138124
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#define GEN6_PCODE_READY (1<<31)
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#define GEN6_READ_OC_PARAMS 0xc
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#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
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#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
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#define GEN6_PCODE_WRITE_RC6VIDS 0x4
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#define GEN6_PCODE_READ_RC6VIDS 0x5
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#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
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#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
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#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
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#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
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#define GEN6_READ_OC_PARAMS 0xc
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#define GEN6_PCODE_READ_D_COMP 0x10
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#define GEN6_PCODE_WRITE_D_COMP 0x11
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#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
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#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
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#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
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#define DISPLAY_IPS_CONTROL 0x19
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#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
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