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ASoC: pxa: ac97: use normal MMIO accessors
To avoid dereferencing hardwired constant pointers from a global header file, change the driver to use devm_platform_ioremap_resource for getting an __iomem pointer, and then using readl/writel on that. Each pointer dereference gets changed by a search&replace, which leads to a few overlong lines, but seems less risky than trying to clean up the code at the same time. Cc: alsa-devel@alsa-project.org Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
4d2dba6b6e
commit
8ff064521f
@ -21,15 +21,17 @@
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#include <sound/pxa2xx-lib.h>
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#include <mach/regs-ac97.h>
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#include <linux/platform_data/asoc-pxa.h>
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#include "pxa2xx-ac97-regs.h"
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static DEFINE_MUTEX(car_mutex);
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static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
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static volatile long gsr_bits;
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static struct clk *ac97_clk;
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static struct clk *ac97conf_clk;
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static int reset_gpio;
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static void __iomem *ac97_reg_base;
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extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
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@ -46,7 +48,7 @@ extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
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int pxa2xx_ac97_read(int slot, unsigned short reg)
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{
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int val = -ENODEV;
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volatile u32 *reg_addr;
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u32 __iomem *reg_addr;
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if (slot > 0)
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return -ENODEV;
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@ -55,31 +57,33 @@ int pxa2xx_ac97_read(int slot, unsigned short reg)
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/* set up primary or secondary codec space */
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if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
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reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
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reg_addr = ac97_reg_base +
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(slot ? SMC_REG_BASE : PMC_REG_BASE);
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else
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reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
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reg_addr = ac97_reg_base +
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(slot ? SAC_REG_BASE : PAC_REG_BASE);
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reg_addr += (reg >> 1);
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/* start read access across the ac97 link */
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GSR = GSR_CDONE | GSR_SDONE;
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writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
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gsr_bits = 0;
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val = (*reg_addr & 0xffff);
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val = (readl(reg_addr) & 0xffff);
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if (reg == AC97_GPIO_STATUS)
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goto out;
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if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
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!((GSR | gsr_bits) & GSR_SDONE)) {
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if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1) <= 0 &&
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!((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE)) {
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printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
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__func__, reg, GSR | gsr_bits);
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__func__, reg, readl(ac97_reg_base + GSR) | gsr_bits);
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val = -ETIMEDOUT;
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goto out;
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}
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/* valid data now */
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GSR = GSR_CDONE | GSR_SDONE;
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writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
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gsr_bits = 0;
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val = (*reg_addr & 0xffff);
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val = (readl(reg_addr) & 0xffff);
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/* but we've just started another cycle... */
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wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
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wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1);
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out: mutex_unlock(&car_mutex);
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return val;
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@ -88,25 +92,27 @@ EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
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int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
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{
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volatile u32 *reg_addr;
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u32 __iomem *reg_addr;
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int ret = 0;
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mutex_lock(&car_mutex);
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/* set up primary or secondary codec space */
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if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
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reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
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reg_addr = ac97_reg_base +
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(slot ? SMC_REG_BASE : PMC_REG_BASE);
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else
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reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
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reg_addr = ac97_reg_base +
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(slot ? SAC_REG_BASE : PAC_REG_BASE);
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reg_addr += (reg >> 1);
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GSR = GSR_CDONE | GSR_SDONE;
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writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
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gsr_bits = 0;
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*reg_addr = val;
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if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
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!((GSR | gsr_bits) & GSR_CDONE)) {
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writel(val, reg_addr);
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if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE, 1) <= 0 &&
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!((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE)) {
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printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
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__func__, reg, GSR | gsr_bits);
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__func__, reg, readl(ac97_reg_base + GSR) | gsr_bits);
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ret = -EIO;
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}
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@ -120,17 +126,17 @@ static inline void pxa_ac97_warm_pxa25x(void)
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{
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gsr_bits = 0;
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GCR |= GCR_WARM_RST;
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writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
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}
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static inline void pxa_ac97_cold_pxa25x(void)
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{
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GCR &= GCR_COLD_RST; /* clear everything but nCRST */
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GCR &= ~GCR_COLD_RST; /* then assert nCRST */
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writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
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writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
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gsr_bits = 0;
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GCR = GCR_COLD_RST;
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writel(GCR_COLD_RST, ac97_reg_base + GCR);
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}
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#endif
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@ -142,15 +148,15 @@ static inline void pxa_ac97_warm_pxa27x(void)
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/* warm reset broken on Bulverde, so manually keep AC97 reset high */
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pxa27x_configure_ac97reset(reset_gpio, true);
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udelay(10);
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GCR |= GCR_WARM_RST;
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writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
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pxa27x_configure_ac97reset(reset_gpio, false);
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udelay(500);
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}
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static inline void pxa_ac97_cold_pxa27x(void)
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{
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GCR &= GCR_COLD_RST; /* clear everything but nCRST */
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GCR &= ~GCR_COLD_RST; /* then assert nCRST */
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writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
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writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
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gsr_bits = 0;
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@ -158,7 +164,7 @@ static inline void pxa_ac97_cold_pxa27x(void)
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clk_prepare_enable(ac97conf_clk);
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udelay(5);
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clk_disable_unprepare(ac97conf_clk);
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GCR = GCR_COLD_RST | GCR_WARM_RST;
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writel(GCR_COLD_RST | GCR_WARM_RST, ac97_reg_base + GCR);
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}
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#endif
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@ -168,26 +174,26 @@ static inline void pxa_ac97_warm_pxa3xx(void)
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gsr_bits = 0;
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/* Can't use interrupts */
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GCR |= GCR_WARM_RST;
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writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
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}
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static inline void pxa_ac97_cold_pxa3xx(void)
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{
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/* Hold CLKBPB for 100us */
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GCR = 0;
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GCR = GCR_CLKBPB;
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writel(0, ac97_reg_base + GCR);
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writel(GCR_CLKBPB, ac97_reg_base + GCR);
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udelay(100);
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GCR = 0;
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writel(0, ac97_reg_base + GCR);
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GCR &= GCR_COLD_RST; /* clear everything but nCRST */
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GCR &= ~GCR_COLD_RST; /* then assert nCRST */
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writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
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writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
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gsr_bits = 0;
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/* Can't use interrupts on PXA3xx */
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GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
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writel(readl(ac97_reg_base + GCR) & (~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN)), ac97_reg_base + GCR);
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GCR = GCR_WARM_RST | GCR_COLD_RST;
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writel(GCR_WARM_RST | GCR_COLD_RST, ac97_reg_base + GCR);
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}
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#endif
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@ -213,10 +219,10 @@ bool pxa2xx_ac97_try_warm_reset(void)
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#endif
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snd_BUG();
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while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
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while (!((readl(ac97_reg_base + GSR) | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
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mdelay(1);
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gsr = GSR | gsr_bits;
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gsr = readl(ac97_reg_base + GSR) | gsr_bits;
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if (!(gsr & (GSR_PCR | GSR_SCR))) {
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printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
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__func__, gsr);
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@ -250,10 +256,10 @@ bool pxa2xx_ac97_try_cold_reset(void)
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#endif
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snd_BUG();
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while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
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while (!((readl(ac97_reg_base + GSR) | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
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mdelay(1);
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gsr = GSR | gsr_bits;
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gsr = readl(ac97_reg_base + GSR) | gsr_bits;
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if (!(gsr & (GSR_PCR | GSR_SCR))) {
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printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
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__func__, gsr);
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@ -268,8 +274,10 @@ EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
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void pxa2xx_ac97_finish_reset(void)
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{
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GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
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GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
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u32 gcr = readl(ac97_reg_base + GCR);
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gcr &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
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gcr |= GCR_SDONE_IE|GCR_CDONE_IE;
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writel(gcr, ac97_reg_base + GCR);
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
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@ -277,9 +285,9 @@ static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
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{
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long status;
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status = GSR;
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status = readl(ac97_reg_base + GSR);
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if (status) {
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GSR = status;
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writel(status, ac97_reg_base + GSR);
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gsr_bits |= status;
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wake_up(&gsr_wq);
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@ -287,9 +295,9 @@ static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
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since they tend to spuriously trigger when MMC is used
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(hardware bug? go figure)... */
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if (cpu_is_pxa27x()) {
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MISR = MISR_EOC;
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PISR = PISR_EOC;
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MCSR = MCSR_EOC;
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writel(MISR_EOC, ac97_reg_base + MISR);
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writel(PISR_EOC, ac97_reg_base + PISR);
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writel(MCSR_EOC, ac97_reg_base + MCSR);
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}
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return IRQ_HANDLED;
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@ -301,7 +309,7 @@ static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
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#ifdef CONFIG_PM
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int pxa2xx_ac97_hw_suspend(void)
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{
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GCR |= GCR_ACLINK_OFF;
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writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
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clk_disable_unprepare(ac97_clk);
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return 0;
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}
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@ -321,6 +329,12 @@ int pxa2xx_ac97_hw_probe(struct platform_device *dev)
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int irq;
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pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
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ac97_reg_base = devm_platform_ioremap_resource(dev, 0);
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if (IS_ERR(ac97_reg_base)) {
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dev_err(&dev->dev, "Missing MMIO resource\n");
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return PTR_ERR(ac97_reg_base);
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}
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if (pdata) {
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switch (pdata->reset_gpio) {
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case 95:
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@ -398,7 +412,7 @@ int pxa2xx_ac97_hw_probe(struct platform_device *dev)
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return 0;
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err_irq:
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GCR |= GCR_ACLINK_OFF;
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writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
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err_clk2:
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clk_put(ac97_clk);
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ac97_clk = NULL;
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@ -416,7 +430,7 @@ void pxa2xx_ac97_hw_remove(struct platform_device *dev)
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{
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if (cpu_is_pxa27x())
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gpio_free(reset_gpio);
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GCR |= GCR_ACLINK_OFF;
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writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
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free_irq(platform_get_irq(dev, 0), NULL);
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if (ac97conf_clk) {
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clk_put(ac97conf_clk);
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@ -430,13 +444,19 @@ EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
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u32 pxa2xx_ac97_read_modr(void)
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{
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return MODR;
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if (!ac97_reg_base)
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return 0;
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return readl(ac97_reg_base + MODR);
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_read_modr);
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u32 pxa2xx_ac97_read_misr(void)
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{
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return MISR;
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if (!ac97_reg_base)
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return 0;
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return readl(ac97_reg_base + MISR);
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_read_misr);
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@ -2,25 +2,23 @@
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#ifndef __ASM_ARCH_REGS_AC97_H
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#define __ASM_ARCH_REGS_AC97_H
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#include "pxa-regs.h"
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/*
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* AC97 Controller registers
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*/
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#define POCR __REG(0x40500000) /* PCM Out Control Register */
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#define POCR (0x0000) /* PCM Out Control Register */
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#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
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#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define PICR __REG(0x40500004) /* PCM In Control Register */
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#define PICR (0x0004) /* PCM In Control Register */
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#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
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#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define MCCR __REG(0x40500008) /* Mic In Control Register */
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#define MCCR (0x0008) /* Mic In Control Register */
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#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
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#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define GCR __REG(0x4050000C) /* Global Control Register */
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#define GCR (0x000C) /* Global Control Register */
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#ifdef CONFIG_PXA3xx
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#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
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#endif
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@ -36,21 +34,21 @@
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#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
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#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
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#define POSR __REG(0x40500010) /* PCM Out Status Register */
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#define POSR (0x0010) /* PCM Out Status Register */
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#define POSR_FIFOE (1 << 4) /* FIFO error */
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#define POSR_FSR (1 << 2) /* FIFO Service Request */
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#define PISR __REG(0x40500014) /* PCM In Status Register */
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#define PISR (0x0014) /* PCM In Status Register */
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#define PISR_FIFOE (1 << 4) /* FIFO error */
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#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
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#define PISR_FSR (1 << 2) /* FIFO Service Request */
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#define MCSR __REG(0x40500018) /* Mic In Status Register */
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#define MCSR (0x0018) /* Mic In Status Register */
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#define MCSR_FIFOE (1 << 4) /* FIFO error */
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#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
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#define MCSR_FSR (1 << 2) /* FIFO Service Request */
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#define GSR __REG(0x4050001C) /* Global Status Register */
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#define GSR (0x001C) /* Global Status Register */
|
||||
#define GSR_CDONE (1 << 19) /* Command Done */
|
||||
#define GSR_SDONE (1 << 18) /* Status Done */
|
||||
#define GSR_RDCS (1 << 15) /* Read Completion Status */
|
||||
@ -69,34 +67,34 @@
|
||||
#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
|
||||
#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
|
||||
|
||||
#define CAR __REG(0x40500020) /* CODEC Access Register */
|
||||
#define CAR (0x0020) /* CODEC Access Register */
|
||||
#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
|
||||
|
||||
#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
|
||||
#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
|
||||
#define PCDR (0x0040) /* PCM FIFO Data Register */
|
||||
#define MCDR (0x0060) /* Mic-in FIFO Data Register */
|
||||
|
||||
#define MOCR __REG(0x40500100) /* Modem Out Control Register */
|
||||
#define MOCR (0x0100) /* Modem Out Control Register */
|
||||
#define MOCR_FEIE (1 << 3) /* FIFO Error */
|
||||
#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define MICR __REG(0x40500108) /* Modem In Control Register */
|
||||
#define MICR (0x0108) /* Modem In Control Register */
|
||||
#define MICR_FEIE (1 << 3) /* FIFO Error */
|
||||
#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define MOSR __REG(0x40500110) /* Modem Out Status Register */
|
||||
#define MOSR (0x0110) /* Modem Out Status Register */
|
||||
#define MOSR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define MOSR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define MISR __REG(0x40500118) /* Modem In Status Register */
|
||||
#define MISR (0x0118) /* Modem In Status Register */
|
||||
#define MISR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
|
||||
#define MISR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
|
||||
#define MODR (0x0140) /* Modem FIFO Data Register */
|
||||
|
||||
#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
|
||||
#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
|
||||
#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
|
||||
#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
|
||||
#define PAC_REG_BASE (0x0200) /* Primary Audio Codec */
|
||||
#define SAC_REG_BASE (0x0300) /* Secondary Audio Codec */
|
||||
#define PMC_REG_BASE (0x0400) /* Primary Modem Codec */
|
||||
#define SMC_REG_BASE (0x0500) /* Secondary Modem Codec */
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_AC97_H */
|
||||
@ -21,7 +21,6 @@
|
||||
#include <sound/pxa2xx-lib.h>
|
||||
#include <sound/dmaengine_pcm.h>
|
||||
|
||||
#include <mach/regs-ac97.h>
|
||||
#include <linux/platform_data/asoc-pxa.h>
|
||||
|
||||
static void pxa2xx_ac97_legacy_reset(struct snd_ac97 *ac97)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user