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dts/imx: rename uart labels to consistent with hw spec

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UART1/UART2/... is more readable than UART0/UART1/... .
Remove redundant UART comments.

Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Richard Zhao 2011-12-14 09:26:45 +08:00 committed by Shawn Guo
parent 4d191868a6
commit 8f9ffecfa9
9 changed files with 36 additions and 36 deletions
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6
arch/arm/boot/dts/imx51-babbage.dts
View File

@ -40,7 +40,7 @@
status = "okay";
};
uart2: uart@7000c000 { /* UART3 */
uart3: uart@7000c000 {
fsl,uart-has-rtscts;
status = "okay";
};
@ -90,12 +90,12 @@
reg = <0x73fa8000 0x4000>;
};
uart0: uart@73fbc000 {
uart1: uart@73fbc000 {
fsl,uart-has-rtscts;
status = "okay";
};
uart1: uart@73fc0000 {
uart2: uart@73fc0000 {
status = "okay";
};
};

12
arch/arm/boot/dts/imx51.dtsi
View File

@ -14,9 +14,9 @@
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
};
tzic: tz-interrupt-controller@e0000000 {
@ -86,7 +86,7 @@
status = "disabled";
};
uart2: uart@7000c000 { /* UART3 */
uart3: uart@7000c000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x7000c000 0x4000>;
interrupts = <33>;
@ -171,14 +171,14 @@
status = "disabled";
};
uart0: uart@73fbc000 {
uart1: uart@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
status = "disabled";
};
uart1: uart@73fc0000 {
uart2: uart@73fc0000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fc0000 0x4000>;
interrupts = <32>;

2
arch/arm/boot/dts/imx53-ard.dts
View File

@ -44,7 +44,7 @@
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
uart1: uart@53fbc000 {
status = "okay";
};
};

2
arch/arm/boot/dts/imx53-evk.dts
View File

@ -75,7 +75,7 @@
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
uart1: uart@53fbc000 {
status = "okay";
};
};

2
arch/arm/boot/dts/imx53-qsb.dts
View File

@ -49,7 +49,7 @@
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
uart1: uart@53fbc000 {
status = "okay";
};
};

6
arch/arm/boot/dts/imx53-smd.dts
View File

@ -39,7 +39,7 @@
status = "okay";
};
uart2: uart@5000c000 { /* UART3 */
uart3: uart@5000c000 {
fsl,uart-has-rtscts;
status = "okay";
};
@ -90,11 +90,11 @@
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
uart1: uart@53fbc000 {
status = "okay";
};
uart1: uart@53fc0000 { /* UART2 */
uart2: uart@53fc0000 {
status = "okay";
};
};

20
arch/arm/boot/dts/imx53.dtsi
View File

@ -14,11 +14,11 @@
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
};
tzic: tz-interrupt-controller@0fffc000 {
@ -88,7 +88,7 @@
status = "disabled";
};
uart2: uart@5000c000 { /* UART3 */
uart3: uart@5000c000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x5000c000 0x4000>;
interrupts = <33>;
@ -173,14 +173,14 @@
status = "disabled";
};
uart0: uart@53fbc000 { /* UART1 */
uart1: uart@53fbc000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
status = "disabled";
};
uart1: uart@53fc0000 { /* UART2 */
uart2: uart@53fc0000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
@ -226,7 +226,7 @@
status = "disabled";
};
uart3: uart@53ff0000 { /* UART4 */
uart4: uart@53ff0000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
@ -241,7 +241,7 @@
reg = <0x60000000 0x10000000>;
ranges;
uart4: uart@63f90000 { /* UART5 */
uart5: uart@63f90000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x63f90000 0x4000>;
interrupts = <86>;

2
arch/arm/boot/dts/imx6q-sabreauto.dts
View File

@ -44,7 +44,7 @@
status = "okay";
};
uart3: uart@021f0000 { /* UART4 */
uart4: uart@021f0000 {
status = "okay";
};
};

20
arch/arm/boot/dts/imx6q.dtsi
View File

@ -14,11 +14,11 @@
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
};
cpus {
@ -165,7 +165,7 @@
status = "disabled";
};
uart0: uart@02020000 { /* UART1 */
uart1: uart@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
@ -543,28 +543,28 @@
interrupts = <0 18 0x04>;
};
uart1: uart@021e8000 { /* UART2 */
uart2: uart@021e8000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021e8000 0x4000>;
interrupts = <0 27 0x04>;
status = "disabled";
};
uart2: uart@021ec000 { /* UART3 */
uart3: uart@021ec000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021ec000 0x4000>;
interrupts = <0 28 0x04>;
status = "disabled";
};
uart3: uart@021f0000 { /* UART4 */
uart4: uart@021f0000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f0000 0x4000>;
interrupts = <0 29 0x04>;
status = "disabled";
};
uart4: uart@021f4000 { /* UART5 */
uart5: uart@021f4000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts = <0 30 0x04>;