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sky2: GPIO register

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The General Purpose I/O register is yet another hardware workaround
catchall. Enable workaround that vendor driver does to stay
but for bug compatiable.

Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger 2007-06-04 17:23:25 -07:00 committed by Jeff Garzik
parent 451af33552
commit 8f70920f2f
2 changed files with 19 additions and 0 deletions
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5
drivers/net/sky2.c
View File

@ -230,6 +230,11 @@ static void sky2_power_on(struct sky2_hw *hw)
sky2_pci_write32(hw, PCI_DEV_REG5, reg);
sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
/* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
reg = sky2_read32(hw, B2_GP_IO);
reg |= GLB_GPIO_STAT_RACE_DIS;
sky2_write32(hw, B2_GP_IO, reg);
}
}

14
drivers/net/sky2.h
View File

@ -441,6 +441,20 @@ enum {
TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
};
/* B2_GPIO */
enum {
GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */
GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */
GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */
GLB_GPIO_TEST_SEL_BASE = 1<<11,
GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */
GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */
};
/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
enum {
CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */