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mailbox: tegra-hsp: Add tegra_hsp_sm_ops
This patch introduces tegra_hsp_sm_ops to abstract send & receive API's for shared mailboxes. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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1b3418ac64
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@ -67,8 +67,14 @@ struct tegra_hsp_doorbell {
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unsigned int index;
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};
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struct tegra_hsp_sm_ops {
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void (*send)(struct tegra_hsp_channel *channel, void *data);
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void (*recv)(struct tegra_hsp_channel *channel);
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};
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struct tegra_hsp_mailbox {
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struct tegra_hsp_channel channel;
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const struct tegra_hsp_sm_ops *ops;
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unsigned int index;
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bool producer;
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};
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@ -208,8 +214,7 @@ static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
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{
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struct tegra_hsp *hsp = data;
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unsigned long bit, mask;
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u32 status, value;
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void *msg;
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u32 status;
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status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
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@ -245,25 +250,8 @@ static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
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for_each_set_bit(bit, &mask, hsp->num_sm) {
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struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
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if (!mb->producer) {
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value = tegra_hsp_channel_readl(&mb->channel,
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HSP_SM_SHRD_MBOX);
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value &= ~HSP_SM_SHRD_MBOX_FULL;
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msg = (void *)(unsigned long)value;
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mbox_chan_received_data(mb->channel.chan, msg);
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/*
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* Need to clear all bits here since some producers,
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* such as TCU, depend on fields in the register
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* getting cleared by the consumer.
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*
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* The mailbox API doesn't give the consumers a way
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* of doing that explicitly, so we have to make sure
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* we cover all possible cases.
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*/
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tegra_hsp_channel_writel(&mb->channel, 0x0,
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HSP_SM_SHRD_MBOX);
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}
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if (!mb->producer)
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mb->ops->recv(&mb->channel);
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}
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return IRQ_HANDLED;
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@ -372,21 +360,52 @@ static const struct mbox_chan_ops tegra_hsp_db_ops = {
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.shutdown = tegra_hsp_doorbell_shutdown,
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};
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static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
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static void tegra_hsp_sm_send32(struct tegra_hsp_channel *channel, void *data)
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{
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struct tegra_hsp_mailbox *mb = chan->con_priv;
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struct tegra_hsp *hsp = mb->channel.hsp;
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unsigned long flags;
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u32 value;
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if (WARN_ON(!mb->producer))
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return -EPERM;
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/* copy data and mark mailbox full */
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value = (u32)(unsigned long)data;
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value |= HSP_SM_SHRD_MBOX_FULL;
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tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
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tegra_hsp_channel_writel(channel, value, HSP_SM_SHRD_MBOX);
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}
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static void tegra_hsp_sm_recv32(struct tegra_hsp_channel *channel)
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{
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u32 value;
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void *msg;
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value = tegra_hsp_channel_readl(channel, HSP_SM_SHRD_MBOX);
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value &= ~HSP_SM_SHRD_MBOX_FULL;
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msg = (void *)(unsigned long)value;
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mbox_chan_received_data(channel->chan, msg);
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/*
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* Need to clear all bits here since some producers, such as TCU, depend
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* on fields in the register getting cleared by the consumer.
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*
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* The mailbox API doesn't give the consumers a way of doing that
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* explicitly, so we have to make sure we cover all possible cases.
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*/
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tegra_hsp_channel_writel(channel, 0x0, HSP_SM_SHRD_MBOX);
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}
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static const struct tegra_hsp_sm_ops tegra_hsp_sm_32bit_ops = {
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.send = tegra_hsp_sm_send32,
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.recv = tegra_hsp_sm_recv32,
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};
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static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
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{
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struct tegra_hsp_mailbox *mb = chan->con_priv;
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struct tegra_hsp *hsp = mb->channel.hsp;
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unsigned long flags;
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if (WARN_ON(!mb->producer))
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return -EPERM;
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mb->ops->send(&mb->channel, data);
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/* enable EMPTY interrupt for the shared mailbox */
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spin_lock_irqsave(&hsp->lock, flags);
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@ -557,6 +576,7 @@ static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
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return ERR_PTR(-ENODEV);
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mb = &hsp->mailboxes[index];
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mb->ops = &tegra_hsp_sm_32bit_ops;
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if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
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mb->producer = false;
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