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ARM: at91: Rework ramc mapping code

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Adapt the ramc mapping code to handle multiple ram controllers in the DT.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Maxime Ripard 2014-07-03 15:58:49 +02:00 committed by Nicolas Ferre
parent 9e8be232b9
commit 8d248f0d3a
2 changed files with 14 additions and 19 deletions
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7
Documentation/devicetree/bindings/arm/atmel-at91.txt
View File

@ -63,7 +63,6 @@ RAMC SDRAM/DDR Controller required properties:
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
- reg: Should contain registers location and length
For at91sam9263 and at91sam9g45 you must specify 2 entries.
Examples:
@ -72,12 +71,6 @@ Examples:
reg = <0xffffe800 0x200>;
};
ramc0: ramc@ffffe400 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe400 0x200
0xffffe600 0x200>;
};
SHDWC Shutdown Controller
required properties:

26
arch/arm/mach-at91/setup.c
View File

@ -395,24 +395,26 @@ static void at91_dt_ramc(void)
{
struct device_node *np;
const struct of_device_id *of_id;
int idx = 0;
np = of_find_matching_node(NULL, ramc_ids);
if (!np)
for_each_matching_node(np, ramc_ids) {
at91_ramc_base[idx] = of_iomap(np, 0);
if (!at91_ramc_base[idx])
panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
idx++;
}
if (!idx)
panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
at91_ramc_base[0] = of_iomap(np, 0);
if (!at91_ramc_base[0])
panic(pr_fmt("unable to map ramc[0] cpu registers\n"));
/* the controller may have 2 banks */
at91_ramc_base[1] = of_iomap(np, 1);
of_id = of_match_node(ramc_ids, np);
if (!of_id)
if (!of_id) {
pr_warn("ramc no standby function available\n");
else
at91_pm_set_standby(of_id->data);
return;
}
of_node_put(np);
at91_pm_set_standby(of_id->data);
}
static struct of_device_id shdwc_ids[] = {