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powerpc/xive: Define xive_native_alloc_irq_on_chip()
This function allocates IRQ on a specific chip. VAS needs per chip IRQ allocation and will have IRQ handler per VAS instance. Signed-off-by: Haren Myneni <haren@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1587016720.2275.1047.camel@hbabu-laptop
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@ -5,6 +5,8 @@
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#ifndef _ASM_POWERPC_XIVE_H
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#define _ASM_POWERPC_XIVE_H
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#include <asm/opal-api.h>
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#define XIVE_INVALID_VP 0xffffffff
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#ifdef CONFIG_PPC_XIVE
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@ -108,7 +110,6 @@ void xive_native_free_vp_block(u32 vp_base);
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int xive_native_populate_irq_data(u32 hw_irq,
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struct xive_irq_data *data);
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void xive_cleanup_irq_data(struct xive_irq_data *xd);
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u32 xive_native_alloc_irq(void);
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void xive_native_free_irq(u32 irq);
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int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
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@ -137,6 +138,12 @@ int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle,
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u32 qindex);
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int xive_native_get_vp_state(u32 vp_id, u64 *out_state);
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bool xive_native_has_queue_state_support(void);
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extern u32 xive_native_alloc_irq_on_chip(u32 chip_id);
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static inline u32 xive_native_alloc_irq(void)
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{
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return xive_native_alloc_irq_on_chip(OPAL_XIVE_ANY_CHIP);
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}
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#else
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@ -280,12 +280,12 @@ static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
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}
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#endif /* CONFIG_SMP */
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u32 xive_native_alloc_irq(void)
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u32 xive_native_alloc_irq_on_chip(u32 chip_id)
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{
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s64 rc;
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for (;;) {
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rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);
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rc = opal_xive_allocate_irq(chip_id);
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if (rc != OPAL_BUSY)
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break;
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msleep(OPAL_BUSY_DELAY_MS);
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@ -294,7 +294,7 @@ u32 xive_native_alloc_irq(void)
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return 0;
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return rc;
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}
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EXPORT_SYMBOL_GPL(xive_native_alloc_irq);
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EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip);
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void xive_native_free_irq(u32 irq)
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{
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